JPS5826113B2 - MOS random access memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (MOS).
) is related to a random access memory configured by integrating.

Complementary connected insulated gate field effect transistor (CMOS)
) using random access memory (CMOS/RAM
) has attracted attention as a static RAM due to its low power consumption and high-speed operation.Furthermore, the RAM as a whole is resistant to power supply voltage fluctuations and has a large noise margin, making it comparable to CMOS.
It also has common characteristics.

FIG. 1 shows an example of this static type CMO8/RAM.

Usually, MOS memory cells are arranged in a matrix, but only two memory cells C1 and C2 are shown in FIG. 1.

The memory cells are C1<CMOS) transistors T, , T
6 inverter and CMOS) transistor T7. T
The cross-over from the gate part of one inverter pair to the drain part of the other inverter pair consisting of T9. T.

are respectively connected to the digit lines Di t DI.

MO8) transistor T9゜Tl for transfer gate
The gate of the word line decoder/driver W-D/D is connected to the word line decoder/driver W-D/D, and the output of W-D/D causes the contents of the memory cell C1 to be taken out to the digit lines , D, and D.

Digit line D1. One side of T1.
T2:T3. Connected to VDD by T4.

A sense circuit S1 is connected to the digit line D1, and a change in the potential of the digit line D1 is detected by this sense circuit and transmitted to the reading pass line BL and guided to the output buffer OB.

The sense circuit S1 is composed of a series connection of a MOS transistor Tll whose gate is connected to the digit line and a MOS transistor T1□ whose gate is connected to the output of DD/D.

The read pass line BL is connected to this sense circuit output and a MOS transistor T13 connected in parallel.
, T14 is connected to VSS.

The CMOS/RAM described above performs the following operations at the read operation timing shown in FIG. 2.

When address AD changes, CE pulse is 0 (-Vss)
Then, MOS) transistor T2. T3 is turned on and digit line D1°Dl is precharged to 1.

Further, the reading pass line BL is also precharged to 0 (=Vss) by turning on the MOS transistor T14.

When the address is determined and the memory cell C1 is selected by W-D/D and DD/D, the digit lines D1 and Dl are set to 1, O, or Oll depending on the contents of the memory cell.
begins to change.

At that time, in the sense circuit, only Sl having T1□ whose transistor is turned on by D-D/D is in operation.

When the potential of the digit line D1 changes from 1 to 0 in accordance with the contents of the memory cell C1, the MOS transistor Tll turns on and changes the read pass line BL from 0 to 1.

On the other hand, the potential of digit line D1 changes to 1 depending on the content of C1.
When changing from to O, the potential of Dl remains at 1 and does not change, so the MOS transistor T1□ remains off, and therefore the read pass line BL also remains at 0 and does not change.

When pursuing high-speed operation in such a CMOS/RAM, one of the limiting factors is the insufficiency of the current drawing ability of the memory cell.

For example, in FIG. 1, the speed at which the potential of digit line D1 changes from 1 to 0 depending on the contents of the memory cell is MO
S) Transistor T6. It is determined by the conductance of T9.

Therefore, transistor T9.MOS) as a transfer gate. T1o and MOS in the memory cell) transistor T6. Increasing the size of T8 to increase the conductance improves the speed, but on the other hand, increasing the size increases the memory cell area and reduces the degree of integration.

In particular, in a RAM system, memory cells occupy most of the area of the entire system, so the above-mentioned improvements are not desirable from the viewpoint of high integration.

The present invention has been made in view of the above points, and has been made to improve the read operation speed while maintaining high integration.
It is intended to provide an OS/RAM.

In order to realize high-speed MOS/RAM, the present invention has the following features:
Fig. 1 Sense circuit and MOS for each digit such as 81 and 82
) The overall sense circuit system consisting of transistors T13 and Tl4 has been devised, and its features are as follows.

That is, it has a plurality of MOS memory cells arranged,
A MOS/RAM in which the contents of a selected memory cell are read by detecting potential changes on a digit line using a sense circuit and outputting the detection output to a reading pass line.
The device is equipped with a MOS transistor circuit that detects changes in the potential of the readout pass line, and provides positive feedback to the pass line in order to detect changes in the output potential of the MOS transistor circuit and speed up the change in potential of the pass line. By connecting a MOS (MOS) transistor circuit that operates as
This speeds up the read operation of M.

An embodiment of the present invention as described above is shown in FIG.

In FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals,
New symbols have been added to parts that differ from those in Figure 1.

The difference from FIG. 1 is that it is equipped with a MOS transistor T
A current supply MOS transistor T18 that detects the output potential change of the OS transistor and operates to provide positive feedback to the pass line to speed up the potential change of the pass line is connected to the pass line, and is further connected to the current supply transistor T18. A MOS transistor T15 that controls the gate potential of T18 during precharging of the digit line or readout pass line in the transistor T15.
The point is that a parallel connection of t T16 is adopted.

MOS/RA with the configuration shown in FIG. 3 as an embodiment of the present invention
M performs the following operation at the timing of the read operation shown in FIG.

When the CE pulse becomes O when the address AD changes, M
OS) transistor T2. T3 turns on and digit line D
1. D1 is precharged to 1.

Further, the reading pass line BL is also precharged to O by turning on the MOS transistor TI4.

Furthermore, the gate potential of the transistor T18 (MO8) for current supply, which provides positive feedback to the change in the potential of the pass line during sensing, is precharged to 1 by the transistor T'to and is off. M.O.
S) The transistor T1□ is off because the pass line O is precharged.

At this time, the digit line potential sensing circuit also does not operate because the digit line is precharged to 1 and T1 is off.

When the address is determined and memory cell C□ is selected by W-D/D and D-D/D, digit line D1. D, begins to change to 1, O, or Oll, respectively.

In the sense circuit, only the transistor TI2 whose transistor is turned on by D-D/D is in an operating state.

The potential of the digit line becomes 1 depending on the contents of memory cell C1.
When it changes from 0 to 0, the MOS transistor Tll turns on and changes the read pass line BL from 0 to 1.

When the pass line changes from O to 1, the MOS transistor T1□ for detecting the pass line potential turns on, and therefore the MO
S) To change the gate potential of transistor T18 from 1 to 0, T□8 is also turned on, and the pass line is suddenly pulled up to 1.

On the other hand, when the potential of digit line D1 changes from 1 to O according to the contents of C2, the potential of Dl remains 1 and does not change, so transistor Tll (MOS) remains off, and therefore the readout pass line BL also remains O and does not change.

Therefore, the MOS) transistor TI for detecting the pass line potential
Since T also remains off and the gate potential of MOS transistor T18 remains at 1, the pass line becomes 0.
will be retained as is.

As described above, in the MO8/RAM according to the present invention, changes in the potential of the digit line during reading are detected by the digit line sense circuit, and changes in the potential of the pass line for subsequent reading are detected by the pass line potential detection transistor. Furthermore, the transistor for supplying current to the pass line provides positive feedback to the pass line potential, which increases the speed.
Moreover, these newly added transistors are pass line precharge transistors T13 j T'
As with t4, it is sufficient to provide one side of each pass line, and even if the size of these transistors is increased in order to increase the ability to supply current to the pass line, it hardly hinders the increase in the degree of integration of the entire RAM system.

In the above embodiment, the transistor that provides positive feedback to the pass line is of a current supply type, but if the conduction type of the structure of FIG. 3 is reversed as a whole, it becomes a current draw type.

In addition, the present invention can be modified in various ways without departing from its gist.

[Brief explanation of the drawing]

Figure 1 shows an example of the configuration of a conventional CMO8/RAM. FIG. 2 is a time chart for explaining the read operation. FIG. 3 shows an example of the configuration of MO3/RAM according to an embodiment of the present invention.

Claims (1)

[Claims] 1 It has a plurality of MOS memory cells arranged, and the contents of the selected memory cell are read out by detecting the potential change of the digit line with a sense circuit and outputting the detected output to the pass line for continuing reading. In the MOS random access memory, the pass line is input to the gate of the first conductivity type transistor, the drain of the first conductivity type transistor is connected to the gate of the second conductivity type transistor, and the second conductivity type transistor is connected to the gate of the second conductivity type transistor. A MOS characterized in that the drain of a conductivity type transistor is connected to the pass line for positive feedback.
random access memory.