JPS5825738A - Fm stereo demodulating circuit - Google Patents

Abstract

PURPOSE:To prevent the degradation of S/N ratio and the influence of beat interference or the like, by taking out respective voltage divided outputs of a resistance ladder circuit in series successively as a demodulation output signal after shifting the level of a composite signal to both polarities in a ratio of about 3:1. CONSTITUTION:A composite signal Ei supplied to an input terminal IN is supplied to two operational amplifiers OP1 and OP2 constituting a level shifting circuit and has the level shifted +3 times in the amplifier OP1 and has the level shifted -1 time in the amplifier OP2. Outputs of amplifiers OP1 and OP2 are applied to both terminals of a resistance ladder circuit LAD consisting of resistances r1-r7. Analog switches S1-S16 of the circuit LAD are controlled by the output pulse from a switching pulse generator SP so as to be turned on and off alternatively. Respective voltage divided outputs of the circuit LAD are led out to two operational amplifiers OP3 and OP4 alternatively, and staircase waves having a phase difference of 180 deg. are outputted to left and right output terminals OUTL and OUTR.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single FM stereo demodulation circuit that multiplies a composite signal by a switching signal and thereby performs an FM demodulation operation, and in particular reduces IM harmonics of the output signal. The present invention also relates to an FM stereo demodulation circuit that reduces crosstalk components.

As is well known, in a switching type FM stereo demodulation circuit, a 38 KHz sine wave synchronized with a subcarrier is preferably used as the switching signal S([).

However, in reality, it is difficult to obtain such a sine wave multiplier with ideal linearity. Therefore, conventionally, as shown in FIG.
2, the duty ratio is 50% as shown in FIG.
11 is multiplied by a rectangular waveform switching signal $(t) having a wave number of 38KH2, and the audio component included in the multiplication result is passed through a low-pass filter F1. I try to take it out by pressing F2.

In this case, the composite signal @El (excluding the pilot signal) is expressed as Ei - (L+R) + (L-R) sin ωt(ω
; subcarrier frequency) and a rectangular wave with a duty ratio of 50% used as the switching signal S(1) as 5(t)-1/2±(2/7N sin ωt±(2/
3π) sin 3ωt±......
The value of these multiplication results El-s(t) is Ei-s(t)-((L+R)+(L-R)
sinωt )−(1/2±(2/K′I sIn
ωt±(2/3π) sin 3ωt±・・・・・・)
becomes.

Therefore, the composite signal E1 is 3ω.

When storing frequency components such as 5ω, it has demodulation sensitivity for these as well.

In this way, if a square wave with a duty ratio of 50% is used as the switching signal @8(t), for example, 1
14KHz (38KHz x3), 190KH2 (3
As shown in FIG. 3, even for input signals such as 8KH2X5), the demodulation sensitivity is relatively high. Therefore, if frequency components such as 3ω and 5ω are included in the FM detection output, this will result in deterioration of the S/N ratio, beat interference, and the like.

Therefore, a method has been used to attenuate these bands in the 0M detection output using a filter, but this method reduces the flatness (both amplitude and 9 phases) up to 53KHz, which is the subcarrier region. As a result, the frequency characteristics of the demodulated bale's stereo separation signal deteriorates.
There is an i.

Furthermore, if the audio component (for example, the left side component) is extracted using a low-pass filter from the above multiplication result equation, it becomes (1/2 + 1/π) 1 + (1/2 - 1/π) R, and from the top of the equation, (1 /2-1/π)R crosstalk component is generated. As a result, if a square wave with a duty ratio of 50% is used as the switch jig signal @a(t) as described above, the maximum separation in principle cannot be improved to 13 dBJX. There are layers.

This invention was made to solve the above-mentioned problem (2), and its purpose is to
Even when frequency components such as 5ω are included, it prevents deterioration of the S/N ratio and effects such as beat interference, and also significantly reduces the aforementioned crosstalk components and improves stereo separation. It's about letting people know.

In order to achieve the above object, the present invention levels-shifts a composite signal to both polarities at a shift ratio of approximately 3:1, and then divides the signal into a plurality of voltages using a resistor ladder circuit.
Each divided voltage output of this resistor ladder circuit is reciprocated in synchronization with the subcarrier, and is sequentially extracted in series as a demodulated output signal.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

First, the basic principle of the stereo demodulation circuit according to the present invention will be explained with reference to FIGS. 4 and 5.

The basic principle of the circuit of the present invention is that, as shown in FIG.
The switching signal 5(t)- containing at least a frequency component of 2sinωt is multiplied by 5(t)-, and El(1+2sl) included in each multiplication result is
n ωt ) and El (1-2 sin ωt ) are respectively demodulated outputs.

and each of the above-mentioned switching signals 5(t).

s(t)'', for example, a substantially sinusoidal staircase wave with a diagonal ratio of +3 to -1 as shown in FIG. 5 is used.In addition, these switching signals s(t)
t ) and s(t ) = have the same frequency as the subcarrier. Such a switching signal @5 (
By multiplying the composite signal E: by t) and 8(t)', the crosstalk components included in the left and right demodulated outputs can be reduced to O in principle. This is proved as follows.

First, if the demodulated signal derived from the output terminal is fL(t), then fL(t) −Ei (1+2sln ωt)
becomes.

Further, the value of the composite signal E1 is expressed as Ei −L+R+ (L−R) sin cot.

−〇− Therefore, the above fL (t) is fL (t) −(L+R+ (L−R)sln ω
t ) x (1+2 sin ωt) −L (2+3 sin ωt −cos 2ωt)
+R(sin ωt +0082 ωt), and if the audio component is extracted from this using an LPF, it becomes fL(t)-21, which proves that the crosstalk from the right side system is completely removed.

Similarly, for Nishi-blade, Composite Shin @E1, (1-2
sin ωt), we get f R(t ) −(L+R(L-R) sin ωt
) x (1-2slnωt) −L (cos 2ωt −5in ωt) +R(
2-3slnωt-CO82ωt), and if the audio signal is extracted from this using an LPF, fR<t')-2R, which proves that the crosstalk component from the left system is completely removed.

Further, in the present invention, as each multiplication means shown in FIG. 4, a multiplication circuit constituted by a component level shift circuit, a resistance ladder circuit, and an analog multiplexer is used.

This multiplier circuit does not require consideration of multiplier nonlinearity, unlike when using conventional multipliers, and therefore
The composite signal E1 can be multiplied by a substantially sinusoidal staircase wave signal as shown in FIG.

Next, FIG. 6 is an electric circuit diagram showing a specific example of the FM stereo demodulation circuit according to the present invention (hereinafter referred to as the first embodiment), and FIG. 7 shows signals in each part of FIG. FIG. 3 is a waveform diagram showing the state. In the first picture, the input terminal IN
The composite signal E1 supplied to the two operational amplifiers OP1. Supplied to OP2.

The operational amplifier OP1 level-shifts the composite signal E1 by +3 times and outputs it, and the operational amplifier OP2 level-shifts the composite signal El by -1 times and outputs it. These operational amplifiers OP1. The output of OP2 is applied to both ends of a resistor ladder circuit LAD consisting of resistors "1" to "7".

At both ends of the resistor ladder LAD and at each connection point there is an analog switch $1 that constitutes the first analog multiplexer.
- S8 and analog switches 89 to 816 constituting a second analog multiplexer are respectively connected,
These analog multiplexers selectively lead out each divided voltage output of the resistor ladder circuit LAD to two operational amplifiers 110P3 and 110P4 respectively constituting a buffer. And these buffers 0P3. The output of OF2 is the left demodulation output terminal 0UTL and the right demodulation output terminal 0U.
It is output to TR.

On the other hand, the analog switches 81 to 816 constituting each of the analog multiplexers are selectively turned on or off by switching pulses output from a switching pulse generation circuit SP, which will be described later. The switching pulse generation circuit SP is configured as follows.

The oscillation frequency of the voltage controlled oscillation circuit (under JX, referred to as ■CO) 19- is determined by the BCD-U/D counter 2. BCD decimal decoder 3. Nant gate 4.5°6, D type flip-flop 7.8. Phase detector9. By a phase-locked loop consisting of 10 DC amplifiers,
It is locked to 532KHz.

The clock pulses output from the BC, D-UID input 92# and vCOI are counted and output as a BCD code.

The decoder 3 converts the BCD code output from the BCD-U/D counter 2 into decimal numbers 0 to 7 and outputs the converted code.

The RS flip 70 knob 11 resets the QO ratio output of the BCD decimal decoder 3 and is set by the Q7 output. The BCD-U/D counter 2 is controlled for up/down switching by the Q output of the RS flip 70 knob 11, Q (10).

As a result, the BCD-U/D counter 2 alternately repeats up-counting and down-counting every time it counts eight 532 KHz clock pulses output from the VCO1.

Therefore, a "1" pulse is output to each output terminal of the decoder 3, QO-Q7A, at the timing shown in FIG. These pulse signals are then supplied as switching pulses to the aforementioned analog switches 81 to 816.

On the other hand, from the Q output of type 0 flip 70 tube 7, ? As shown in the diagram, “1” is generated every half period of the subcarrier.
” or “0”, that is, Q(38) is output, and this rectangular wave Q(38) is further passed through the D-type flip 7.
The frequency is divided by 1/2 by the 0 knob 12, and the branch output Q(
P) is used to generate a cancellation signal for canceling the pilot signal.

According to the above configuration, the left III tone output terminal 0LITL
And to the right demodulation output terminal 0UTH, analog switches (81, 89), (82, 810), (83, 811
)-... are alternately derived every clock.For example, the resistance values of resistors 11 to r7 are all set to the same value, and the composite signal E+ is set to a constant DC voltage. If it is assumed that the left and right output terminals oUTL and 0UTR have a phase difference of 180 degrees from each other and the fundamental wave is the frequency of the subcarrier, a staircase wave is output as shown in FIG. . That is, if an arbitrary composite signal is El, and each staircase wave shown in No. 91 is s(t), S(t)', then the left demodulation output terminal 0UTL has Ei and the left 11th staircase wave S. (t) is output, and the right demodulation output terminal 0UTR receives Ei s(t), which is the multiplication result of El and the right staircase wave s(t) =.
t)' is output, multiplication with a switching signal is performed here, and stereo demodulation is performed.

In addition, the waveform of the staircase wave s(t) can be arbitrarily set by selecting the resistance value "1" to "7" as appropriate. If selected, the staircase wave 5(t) can be made into a substantially sinusoidal waveform as shown in FIG. 5. Also, FIG. This is a graph showing the demodulation sensitivity of the Earthquake Four Roads.As shown in Figure 3, in the conventional circuit, there is only a difference of about 10 dB between the fundamental wave ω component and the third harmonic 3ω component. Moreover, harmonic components such as the 5th and 7th harmonics are not attenuated much.
In the case of the circuit of the present invention, as shown in FIG. 8, there is a level difference of about 40 dB between the fundamental wave ω component and the third harmonic 3ω component, and furthermore, there is a level difference of about 40 dB between the fundamental wave ω component and the third harmonic 3ω component. It was also possible to significantly reduce this compared to the case of the conventional circuit.

Also, these switching signals @8(t), $(t)'
As mentioned above, (1+28Inωt)
, (1-2 sin ωt) 6 frequency teaching precepts! Therefore, as proven by the above formula, the demodulated outputs on the left and right sides are free from each other's crosstalk components, and the degree of stereo separation can be further improved. be.

Thus, the FM stereo recovery 13- open circuit according to this embodiment converts the composite signal @Ei with a shift ratio of +3 to -.
Shift the level to the positive side and negative side at the same time so that it becomes 1,
The voltage between these outputs is divided in advance into 8 levels by a resistor ladder circuit LAD, and each of these divided voltages is selectively applied to each demodulation output terminal 0UTL, 0UTR via analog switches 81 to 816. This is different from the conventional example in which a non-linear performance element is used as the multiplication means, and the composite signal E1 is
For any waveform switching signal @5(t), 5(
t)- can be accurately multiplied without distortion.

Therefore, ideal stereo demodulation operation can be achieved by increasing the number of voltage division levels mentioned above and selecting resistance values strictly to make the waveform of the staircase wave signal @s(t) more similar to a sine wave. It can be carried out.

Also, according to this four-way demodulation, as mentioned above, the third order.

Since the fifth-order and other low-order harmonic components can be significantly reduced, there is no need to provide a filter to remove these components before the *gs circuit, and this reduces the frequency of stereo separation. Dependencies can also be resolved.

Furthermore, as the switching signal waveform, (1+2
slnωt > (1-2slnωt) Since a switching signal containing frequency components such as It can be improved significantly.

Next, FIG. 9 is an electric circuit diagram showing another embodiment (hereinafter referred to as the second embodiment) of the present invention. In addition,
In FIG. 9, parts having the same configuration as those of the first embodiment are designated by the same reference numerals, and a description thereof will be omitted.

The feature of this second embodiment is that it facilitates quality control when selecting the resistive elements constituting each resistor ladder circuit, thereby preventing the generation of even-order harmonics caused by variations in the resistive element product range. It is something.

In FIG. 9, the composite signal @E: supplied to the input terminal IN is supplied to operational amplifiers 10P5 to OP8 of 411. When the analog switch 825 is on, +3·El is output to the output side of the operational amplifier OP5, and when the analog switch 825 is off, -El is output. Similarly, operational amplifier OP7
When the analog switch 826 is on, +3·El is output to the output side of the circuit, and when the analog switch 826 is off, -El is output.

And analog switch 825 and analog switch 8
At 26, Q (38) is the Q output of the RS flip 70 knob 15 that constitutes the switching pulse generation circuit SP.
and an inverted Q output (38) are supplied.

Therefore, on the output side of operational amplifier OP5, a rectangular wave having the frequency of the subcarrier and inverted between +3El and -Ei is output, and on the other hand, on the output side of operational amplifier OP7, a rectangular wave having the frequency of the subcarrier is outputted. A rectangular wave having the frequency of the carrier, inverted between +3·El and -E1, and having a phase difference of 180 degrees from the rectangular wave is output.

Operational amplifiers OP6 and OF2 each operate as a buffer, and El is always outputted to the output side thereof. The outputs of the operational amplifiers OP5 and OF2 are connected to a resistor ladder circuit 11LADI consisting of resistors "11 to "41, respectively.
is applied across the operational amplifiers OP7 and OF2.
Each output is applied to both ends of a resistance ladder circuit LAD made up of resistors r12 to r42.

The divided voltage output of the resistance ladder circuit LAD1 is led out to the left demodulation output terminal 0UTL by an analog multiplexer consisting of analog switches 817 to 820, and the divided voltage outputs of the resistance ladder circuit LA02 are output to the analog switches 821 to 824. The signal is output to the right rear output terminal 0UTR through an analog multiplexer consisting of a The analog switches 817 to 824 constituting each analog multiplexer are selectively controlled on and off by switching pulses supplied from the switching pulse generation circuit SP.

17- Next, the switching pulse generation circuit SP will be explained. The frequency of the voltage controlled oscillator (hereinafter referred to as VGO) 1 is determined by an up/down counter 2°BCD/DEC decoder 3. Nant Gate 13° 14, RS flip 70 knob 15. D-type flip 7078. Phase locked circuit consisting of phase detector 9 and DC amplifier 10
It is locked to 532KH2 by a loop.

The BCD-U/D counter 2 counts the clock pulses output from this vCOl and outputs it as an 8CD code.

The decoder '3 converts the BCD code output from the BCD-U/D counter 2 into decimal numbers 0 to 7 and outputs the converted code.

The RS flip-flop 11 resets the QO ratio output of the BCD decimal decoder 3 and is set at the 07 output. Then, the BCD/U/D counter 2 is switched from up to down by the Q output of the RS flip 70 knob 11.

As a result, BCD-u/D counter 2 converts the 532KHz clock pulse output from VC18-01 into 8
Each time you count, count up and count down alternately.

As a result, "1" is output to each output terminal QO-07 of the decoder 3 at the timing shown in FIG. and,
The respective outputs QO to Q7 of these decoders 3 are further logically summed via OR gates 17 to 19, and the outputs of these OR gates are connected to the aforementioned analog switches 817 to 824.
It becomes a switching pulse for .

On the other hand, on the output side of the RS flip 70 knob 15, as shown in FIG.
A square wave with a value of 0'' is output, and the RS flip 70 knob 1
Q (38), which is the Q output of 5, is the Q output of the aforementioned operational amplifier O
The signal is supplied to an analog switch 825 inserted on the input side of P5. Further, Q(38), which is the Q output of the RS flip 70 tube 15, is supplied to an analog switch 826 inserted on the input side of the operational amplifier OP7.

As a result, analog switches 825 and 826
This means that it alternately turns on and off in synchronization with the subcarrier.

According to the configuration of 4 or above, the composite signal E1 is always supplied to the output sides of the operational amplifier OP6 and the operational amplifier OP'8.
is output as is. On the other hand, the operational amplifier OP
5 and the output side of the operational amplifier 110P7, the composite signal E1 is level controlled to +3 times and -1 times every half period of the subcarrier and is outputted. And operational amplifier 10P
When the gain of the operational amplifier OP7 is set to +3 times, the gain of the operational amplifier OP7 is always set to 11 times.
Conversely, when the gain of operational amplifier OP5 is set to 11 times, the gain of operational amplifier OP7 is set to +3 times. That is, the output of the operational amplifier 10P5 and the output of the operational amplifier OP7 always have a phase difference of 180 degrees.

On the other hand, the analog switches 817 to S20 sequentially switch to 820 to 481 corresponding to the period in which the analog switch 825 is on and the period in which it is off.
9 → 818 → 817 → 818 → 819 → 820. Similarly, the analog switches 821 to 824 are turned on in sequence 824 → 823 in the period corresponding to when the analog switch 826 is on or off. →
It turns on as follows: s22→821→822→823→824.

Therefore, if we assume that the level of the composite signal supplied to the input terminal IN is DC, a staircase-like pseudo sine wave will be output to the left demodulation output terminal 0UTL.
Similarly, this and 18
A step-like pseudo sine wave having a phase difference of 0 degrees is obtained. In other words, if an arbitrary composite signal E1 is supplied to the input terminal IN, the left demodulation output terminal 0UT
The result of multiplying this composite signal @E1 and the pseudo sine wave is obtained for L, and on the other hand, the right side Il [lI output terminal 0L
The result of multiplying the composite signal jtEj by the pseudo sine wave for the right side is obtained in JTR.

As a result, the crosstalk components included in the left and right demodulated outputs can be completely removed, as proven by the above formula.

Thus, the FM stereo reconstruction a shown in this second embodiment
According to the ll@ route, a composite signal @E1 containing at least a stereo main channel signal and a stereo sub-channel signal is transferred to the subcarriers so that the shift ratio on the positive side and the negative side is +3 to -1. After the level is shifted alternately to the positive side and the negative side by half a cycle, each divided voltage output is shifted between the positive and negative side outputs and the potential corresponding to +1 at the shift ratio. The voltage is divided by resistor ladder circuits LAD and LAD2 that divide the voltage into multiple voltages symmetrically on the positive side and negative side with the potential corresponding to In synchronization with the subcarrier in signal E1,
Since the two analog multiplexers consisting of analog switches 817 to 820 and 821 to 824 are used to reciprocate and sequentially take out data in series, each of the divided voltage outputs of the resistor ladder circuits LADI and LAD2 has a sine If the composite signal E1 is set to have an instantaneous value at each of the 22-points obtained by dividing one cycle of the wave into 8 equal parts, the composite signal E1 can be multiplied accurately and without distortion by the staircase-shaped sine wave. As a result, the odd-order harmonic components contained in each demodulated output can be significantly reduced compared to the conventional multiplication of rectangular waves. In addition, the voltages applied to both ends of the resistance ladder circuit LAD1.1AD2 are +3 times the composite signal Ej to the positive side,
Since the levels are shifted by a factor of 11 to the negative side, the multiplicand signals used in each left-hand and right-hand multiplication operation are (1+2 sin ωt ), respectively.
, (1-2sln ωt) is included, and as proven by the above formula,
Crosstalk components are completely removed in each demodulated output.

Furthermore, in this embodiment, since the voltage applied to both ends of each resistor ladder circuit LAD is switched every half period of the subcarrier, the upper and lower halves of the pseudo sine wave, which is the multiplicand signal, are the same. As a result, the upper and lower half-waves of the multiplicand signal always have symmetrical waveforms. Therefore, it is possible to solve the conventional problem of even-order harmonics being included in each demodulated output due to the vertical asymmetry of the multiplicand signal. That is, the first
As in the embodiment, if the resistance ladder circuit LAD is constituted by a series of resistors "1 to "7, corresponding to one period of the subcarrier, each step output of the pseudo sine wave is generated by resistors r1 to r.
7 individually. Therefore, a pair of resistor groups located on both sides of resistor r4, that is, resistor "3" and resistor "5. Resistor r2 and resistor "6. Resistor "1" and resistor "7" have the same value. In contrast, according to the resistance ladder circuits LAD1 and LAD2 of the second embodiment shown in FIG. There is no need to prepare two resistors each having the same resistance value, and quality control in element selection becomes easier.

In both of these embodiments, the shift ratio of the level shift circuit is +3 to -1, but even if it is +1 to -3, it is not the same.

As is clear from the description of each embodiment above, according to the FM stereo demodulation circuit according to the present invention, it is possible to significantly reduce odd harmonics of subcarriers included in each left and right demodulated output, and In principle, crosstalk components contained in both inertia outputs can be completely removed,
Moreover, it has excellent features such as the configuration can be digitized and the cost can be reduced by integration technology.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an FM stereo tuning circuit using a conventional multiplier and a square wave switching signal, and FIG.
The waveform diagram of the switching signal used in the figure, Figure 3, is as follows:
A diagram showing the temperature control output components in the circuit of FIG. 2, FIG. 4 is a block diagram showing the basic aS of the circuit of the present invention, and FIG.
The staircase wave signal waveform diagram used in the circuit of the present invention, FIG. 6, is as follows:
The electrical circuit diagram showing the first embodiment of the present invention, No. 7all, is
625- Waveform diagram showing signal states in each part of FIG. 9 and FIG.
FIG. 8 is a diagram showing frequency components included in each demodulated output in the circuit of the invention, and FIG. 9 is an electric circuit diagram showing a second embodiment of the invention. OPl, OF2. OF2. OF2...Level shift circuit LAD, LADl, LAD2...Resistance ladder circuits 81 to 824...Each analog switch El constituting the analog multiplexer...Composite signal Patent applicant Nippon Musical Instruments Manufacturing Co., Ltd. 26-

Claims (1)

[Claims] (1) The main channel signal for stereo and the ■channel signal for stereo are at least a composite signal with a shift ratio of approximately 3:1. A resistor ladder circuit that shifts the level to both polarities and divides the voltage between the positive and negative outputs of this level-shifted output into multiple voltages using a resistor ladder circuit, and converts each divided voltage output of this resistor ladder circuit into a component signal. An FM stereo inertia control circuit characterized in that it performs reciprocating operation in synchronization with the subcarrier inside and sequentially extracts it as a demodulated output signal in series.