JPS5825720A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption, by providing first and second output transistors (TRs), which output levels (1) and (0) to the outside of a buffer circuit, and first and second load TRs for driving these output TRs and setting the threshold voltage of the first load TR to a value lower than that of the second load TR. CONSTITUTION:When a chip select signal CS is ''0'', TRs T13 and T14 are turned on, and gates of output TRs T9 and T10 become zero, and they are in the high impedance state together. When the signal CS is ''1'' and data is ''1'', a TR T6 is turned off, and a TR T7 is turned on, and therefore, the TR T9 is driven by a load TR T21 having a lower threshold and is turned on. When data is ''0'', the TR T7 is turned off, and therefore, the TR T10 is driven by a load TR T22 and is turned on. Since output TRs T9 and T10 are not made conductive simultaneously, the current consumption is small.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output cover and a filter circuit for outputting data in an integrated circuit to the outside of the integrated circuit.

Normally, in an integrated circuit, it is necessary to rapidly charge and discharge a large capacitor connected to the outside of the circuit, so the built-in transistor connected to the external output terminal for outputting data to the outside has a low driving capacity. Some large transistors are used. Therefore, the channel width of such a transistor is set to be very large.For example, when the channel length is 4-, the channel width is about 2000 μm. Therefore, the driving transistor that drives the transistor connected to this external output terminal also requires a fairly large transistor.

Due to the above-mentioned circumstances, the output cover and the output circuit for outputting the data in the integrated circuit to the outside of the integrated circuit, for example, are
Conventionally, the circuit configuration has been as shown in FIG. 1, for example.

In other words, in the figure, the data in the integrated circuit is input to the degressive input! llCDri)? The output of the inverter 1, which consists of a transistor T1 and an enhancement transistor T1, is input to an inverter I, which consists of a transistor T1 and an E-type transistor, and a D-type transistor. It is input to the gate of EfJ) transistor T, which constitutes buffer circuit B1 by T@ and LC type transistor T6. At the same time, the output of the inverter 21 is input to the D-made transistor T-, which constitutes a buffer circuit B with the 'Eli transistor T-dou and the D-type transistor T$. On the other hand, the above inverter! The snow output is f-) of the above transistor Tl*Tf
The output of the 77 circuit B1 is input to the transistor T circuit f-) of the 7 circuit circuit B consisting of E-type transistors T, T1, and the output of the 77 circuit B1 is input to
, are input to the above-mentioned transistor TIO. Further, between the output terminal of the inverter 11eIl and the ground, there is a K11l transistor T11 to which an inverted chip select signal j- is inputted to r-to, respectively.
e T 11 is provided, and the above-mentioned path, 77 circuit 1 is provided.
1. Between the B and Q output terminals and ground, there are inverted channels, respectively.
An E-type transistor T 18 e T14 to which the f-select signal C8 is inputted is provided. These transistors T11 to T7 are connected when the chip is not selected (Sil”
), the inverter l1yII becomes conductive at this time.
And the output of the P,F circuit B1#Bl becomes logic 10'', which causes the transistor T・ of the P,F circuit MBm
Since both eTl· become non-conductive, the output becomes a high impedance state. On the contrary, tsk! When selected (CB='Q), an output corresponding to the data "o", @i" logic is obtained from the P/F circuit B. At this time, the P/F circuit B
Since the channel width of the transistor TI*T1 constituting s is very large, its dirt capacitance is also very large. For example, if the dirt insulating film of a transistor is 81
0. The film thickness is 600X.

Channel length is 4 fira, channel width is 2000
If it is μm, the dart capacitance alone will have a capacitance value of about 4.6P. Therefore, the output 2 register T., T
In order to drive the transistor 1, a transistor 11*Bl is required, and a degradation lid transistor has conventionally been used as the load transistor Tl5T to increase the driving capability.
In order to increase the drive capability of ``a'', the channel width must be increased, and the current consumption when the chip is selected or when the chip is not selected becomes quite large. As the number of microcontrollers increases, for example in central processing units (CPUs), memories, etc., the current consumption also increases as the number of microcontrollers increases to 4.8 to 16.32.

Therefore, the output buffer circuit shown in FIG. 2 is a circuit designed to reduce the current consumption when the chip is not selected. This circuit eliminates the transistor T■ connected to the output terminal of the inverter I in Fig. 1, and the inverter I! , pa,
The circuit configuration is such that transistors Tll to T17, each of which receives a chip select signal CB (r-), are additionally connected between the filter circuit B1*"fi and a power supply VC (for example, 5V). These transistors The threshold voltage of Tli~Tl? is higher than that of the D-type load transistor TI#Tl,
0 to -IV, and is shown by the transistor symbol as shown in the figure.If the driving capability of one of these transistors Tl@eT is sufficiently large, the signal CS will be "1 level" (for example, the power supply Vj level), the output voltage waveform of the buffer circuit B1*Bl is determined by the load transistor 'rs*T's, for example, and has the same speed as the circuit shown in Figure 1.In addition, when the chip is in the non-selected state is the goo)tfov of these transistors 'rls-w'r1°, so the current consumption is reduced by the higher threshold voltage of the transistors Tll-rty compared to, for example, only the load transistors 'rs and 'r. For example, if the threshold voltages of these transistors T'si to 'I'ty can be controlled to Ov, then these transistors Tll''-'Tl? The current flowing through should be zero.

FIG. 3 shows an output circuit which is a further improvement on the circuit shown in FIG. 2 described above. That is, in place of the load transistor TI#TI described above, this circuit line is replaced by the transistor T II e T whose dark value voltage is Ov to -IV.
II is used as a load transistor of the circuit B1*Bl, and it is connected between the inverter 11 and the power supply V@! A transistor 'I'ss having the same dark value voltage as described above is provided to which the select signal C8 is applied to the dirt. In this way, when the tick is not selected, the tick select signal becomes 010'', Ω≧1'', and the dirt of the transistor "1@#T1@ becomes QV, so the current consumption can be reduced, and the switch , When f is selected, the output of the inverter Is becomes an inverted output, so one side of the transistor Tl1e and r-) is always @Om, so the current consumption can be reduced even when f is selected. It is possible. ゛However, the above-mentioned transistor T II @ aTII
It is very difficult to control the dark value voltage within the range of Ov to -IV, and the current consumption also changes drastically due to subtle fluctuations in the dark value voltage.

In other words, when the dark value voltage is Ov, the current is zero, but if it goes even slightly in the negative direction, the current increases extremely. This is because when the gate of the transistor is Ov, the transistor operates in the saturation region, so the current is proportional to the square of (dart voltage V, -threshold voltage vth). In this manner, in the above-described circuit, the transistor T1· is used to drive the large capacitance of the transistor TIeT1·.

It is necessary to increase the driving ability of T'xs. Therefore, it is necessary to increase the channel width of the transistor. However, since the channel width is made large, the dependence of current consumption on the threshold voltage becomes larger due to fluctuations in the threshold voltage. For this reason, in the past, there was a problem in that the dispersion in the current consumption between the wires and F was large, and the dark value voltage was very closely related to the yield.

The present invention has been made in view of the above circumstances, and is
The dark value voltage of the load transistor to drive the output transistor that outputs the 11# level to the outside of the circuit @
□ By using a circuit configuration that is set lower than the dark value voltage of the load transistor for driving the output transistor that outputs the In level, the dark value voltage dependency is reduced and the current consumption is stably reduced. The purpose of this invention is to provide an output buffer circuit that can realize integrated circuits with high yield.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.1 In the output buffer circuit shown in FIG. D is input with data generated within the integrated circuit.
A first inverter It consisting of a transistor T1 (ll) and a transistor T (III) is provided, and an extended tick select signal C8 is input to r-) between the first inverter I and the power supply vc, and the threshold value A transistor Tll with a voltage of O to -IV is provided. The output terminal of this first innovator I is connected to a D-type transistor T3 and Ii:
! l) Transistor Ta00-1 of the second inverter I consisting of transistor T4;
The gate of the transistor T of the first buffer circuit B1 consisting of Ta t Tm* and the EMji transistor
? pT1! are respectively connected to the gates of the transistors T■ of the second buffer circuit B3 consisting of the following. A transistor T'se similar to the transistor 'I'll described above is provided between the second inverter I and the power supply vc. Furthermore, these second inverters I, the output ends, the first . 2nd output cover, 7+- circuit between B1#ll output terminal and ground, respectively inverted tick select signal C8
Transistors T'xs to T14 whose gates are inputted are provided. Also, the second inverter above! Is the output terminal of 3 the transistor of the 1lzfy amplifier circuit B1? 'x
The transistor T of the dart and second pass circuit B of t
1 r-) respectively.

Further, the output terminal of the first buffer circuit B1 is connected to the r-to of the transistor T of the third buffer circuit Bs composed of the E-type transistor TI*T1.
The output terminal of the buffer circuit B is the third buffer circuit Bs.
f-) of the transistor T1.

That is, in this circuit, the transistor T II s of the dark value voltage Ov to -IV in the circuit shown in FIG.
Instead of TII, an Efjl load transistor T 11 *T 11 whose threshold voltage is equal to or higher than Ov group is used for the second buffer circuit 11 *Bl. These load transistors TsxeT*s are the third transistors.

It has the same threshold voltage as the output transistor T・sTl・ of the 7A circuit ms and is made in the same process, but the transistor T
The channel length of transistor Tll is longer than that of transistor Tll, so that the dark voltage of transistor T1 is smaller than the dark voltage of transistor T1m.

In other words, the dark value voltage of the load transistor Tll that drives the output transistor 〒9 of the third buffer 7 circuit Bs which outputs the 11m level to the outside of the main line, PA and 77 circuits is as follows.
A load transistor T that drives the output transistor Tl of the third buffer circuit ms that outputs the "0# level" to the outside.
It is characterized by being set lower than the dark value voltage of ll.

With this kind of circuit configuration, when the tick is not selected (cs-'
o'', and ♂11), the transistor circuit...I'
The eyes are conductive, the inverter It and the buffer circuit BleB
1 becomes @0'', and the load transistor T snow 1
#TII dirt becomes Ov, 3rd buffer circuit B,
Since the output transistor Tl5T1· becomes non-conductive, the current can be completely reduced to zero. At this time, the output becomes a high impedance state. On the other hand, when selecting a chip (C
B-'1', C3dO, the value corresponding to the @0''-1# data input to the first inverter IIK is the third one.
It is sent to the outside from the output end of the buffer circuit Bl. At this time, one of the load transistors becomes non-conductive due to the inverter 11*Il, and the current consumption of the load transistor 11sTll can also be reduced compared to the conventional transistor.

If the dark value of the load transistor is the same as that of the output transistor "l5T1", there will be a problem in circuit operation. In other words, there is no problem with the transistor T11eT1, but if the dirt of the transistor Tll is
The level becomes a1m, and the gate of transistor T- becomes @1
When it becomes Rubel and 9 o'clock, that is, when Chi and De are selected (C8="1
'', intoxication - First, from the output terminal of the third buffer circuit Bs, v
Only an output voltage of c-vms-V (v?W e v, respectively, is the dark value voltage of the transistor Ta1e) is output.

In other words, there is a drawback that the 11" level of the output of the Honda cover/fa circuit is not sufficient.

Therefore, in order to eliminate such defects, it is sufficient to lower the dark voltage of the transistor Tll, and as described above, according to the present invention, the short channel effect is used to reduce the channel length shorter than the channel length of the transistor T1m. By setting the dark value voltage of the transistor Tlt to the transistor 'I
It is lower than the dark value voltage of 'll. by this,
The output of the Honda Rikipad 77 circuit can be increased by the amount of the threshold voltage lowered by 11 levels, and the current consumption can be reduced compared to the conventional one. Furthermore, without controlling the threshold voltage by the transistor circuit, and without increasing any special provisions, the dark voltage of the transistor T snow 1 can be changed to the other transistor T.
,.

T　l@　e　T　can be lower than 1m.

3. Load transistor T! 3 mentioned above instead of 1.
The transistor T11 shown in the figure may also be used.

As explained above, according to the present invention, the output transistor that outputs the 6''''1'' level according to the data is driven to the outside of the output pad circuit that outputs the data in the integrated circuit to the outside of the integrated circuit. The circuit configuration is such that the dark value voltage of the load transistor is set lower than the dark value voltage of the load transistor for driving the output transistor that outputs @0 level according to the above data, so the threshold voltage dependence to stably reduce current consumption by reducing
It is possible to provide an output buffer circuit that can realize an integrated circuit with high yield.

[Brief explanation of the drawing]

FIGS. 1 to 3 each show a conventional cover. FIG. 4 is a block diagram of an output cover and a block diagram of an output circuit according to an embodiment of the present invention; FIG. T1 e Ts ・-p) transistor, T, ,T,. 'r, t 'r, e Tll a T14”・
Il! ) Transistor, Tss-T @@...Transistor with different threshold voltage, TllsTml"/Efi load transistor with different dark value voltage, T@sTl......X
type output transistor, 11*Il...inverter,
Bl ~ms...Parallel circuit, cs, T! 'Fi・
...Chip select signal, V, ...power supply.

Claims (3)

[Claims] (1) A first output transistor that outputs an 11'' level to the outside of the P/F circuit, a second output transistor that outputs a ``0'' level, a first load transistor that drives the first output transistor, and a second output transistor that outputs the ``0''level; a second load transistor for driving two output transistors, and the dark value voltage of the first load transistor is set lower than the dark value voltage of the second load transistor. circuit. (2) Above 1. 2. The output cover circuit according to claim 1, wherein the second load transistor is an enhancement transistor. (3) Above 1. The threshold voltage of the second load transistor is the same as that of the first load transistor. 2. The output buffer circuit according to claim 1, wherein the threshold voltage of the second output transistor is different.