JPH08148988A - Voltage level shift circuit - Google Patents

Abstract

PURPOSE: To obtain the circuit with high reliability in which a gate oxide film is not destroyed by connecting a load element, a one conduction type of a 1st MOS transistor(TR) and reverse conduction type of 2nd and 3rd MOS TRs in series between a power supply and ground in this order and introducing a logical output from a connecting point between the 1st and 2nd MOS TRs. CONSTITUTION: A resistive element R11 acting like a load element L11 , a P channel MOS TR P12 receiving a voltage VMP close to a voltage VPP/2 at its gate, an N channel MOS TR N12 whose gate receives a voltage VMN close to VPP/2 and an N channel MOS TR N11 whose gate receives an input signal IN1 are connected in series between a high voltage power supply terminal VPP and a GND. Then the inverse of output signal OUT11 is extracted from the connecting point between the MOS TRs P12 , N12 . Thus, a high voltage is controlled by the input signal IN11 deflected between the VDD and GND to obtain the inverse of output signal OUT11 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage level shift circuit, and more particularly to a high voltage level shift circuit necessary for controlling the writing of data to a non-volatile memory device by obtaining a high voltage with a logic signal of low amplitude. It is about.

[0002]

2. Description of the Related Art As shown in FIG. 14A, a nonvolatile memory device includes a memory cell array 81 and a row decoder (X decoder) for selecting a memory cell in the memory cell array 81 according to an address supplied from the outside. And a column decoder (Y decoder) 83, a sense amplifier 84 for reading the data stored in the selected memory cell, and a write circuit 85 for writing the data in the selected memory cell. Has been done.

A power supply voltage VDD (for example, 5V) and a high voltage VPP (for example, 12V) necessary for writing data are written in the X decoder 82, the Y decoder 83, and the writing circuit 85.
Is applied.

FIG. 14B is a circuit diagram of a memory cell forming the memory cell array 81. For example, when "1" is stored in the selected memory cell, VG = VPP, VD
= VPP, while storing "0" VG = VPP,
Let VD = 0V. In the non-selected memory cell, VG =
It is also necessary to set it to 0V.

As described above, when writing data in the non-volatile memory, it is necessary to control the high voltage applied to the memory cell by the address oscillating between VDD and GND (ground) and the write data, and VDD to GND. A high voltage level shift circuit is used to control the high voltage with a signal that swings between.

A conventional high voltage level shift circuit is disclosed in, for example, Japanese Unexamined Patent Publication No. 4-277920.
As shown in (a), a resistance element R31 functioning as a load element L31 and an input signal IN3 are applied to the gate between a high voltage power supply terminal VPP (hereinafter referred to as VPP) and a ground electrode GND (hereinafter referred to as GND). And a series circuit in which an N-channel type MOS transistor N31 is connected in series, VPP and G
Between ND, the gate has a resistance element R31 and an N-channel type MO.
A P-channel type MOS transistor P32 connected to the connection point K of the S transistor N31 and an input signal I at its gate.
N3 is composed of a series circuit in which an inversion signal IN3 inverted by an inverter I31 and an N-channel MOS transistor N32 to which an inversion signal IN3 is applied are connected in series, and a connection point between the P-channel MOS transistor P32 and the N-channel MOS transistor N32. The output signal OUT31 is taken out from.

Next, the operation will be described with reference to FIG. First, the input signal IN3 is "L"("L" is GN
In this case, it means the D level, and will be referred to as "L" hereinafter).
The channel-type MOS transistor N31 is turned off, and the potential at the connection point K is "HH"("HH") by the resistance element R31.
Means VPP level, and will be referred to as "HH" hereinafter).

Further, since the gate potential is "HH", the P-channel type MOS transistor P32 is turned off, and the inverted input inversion signal IN3 is "H"("H" means VDD level, hereinafter "H"). Therefore, the N-channel MOS transistor N32 is turned on, and the output signal OUT31 becomes "L".

On the other hand, when the input signal IN3 is "H", N
Since the channel type MOS transistor N31 is turned on,
(On-resistance of N-channel MOS transistor N31)
<< (resistance value of the resistance element R31), the connection point K becomes "L", and since the gate potential is "L", the P-channel MOS transistor P32 turns on,
Since the inverted input inversion signal IN3 is "L", N
The channel type MOS transistor N32 is turned off, and the output signal OUT31 becomes "HH".

As described above, according to the conventional high voltage level shift circuit shown in FIG. 8A, VDD to GND are used.
The high voltage is controlled by the input signal IN3 that oscillates between "L"
And the output signal OUT31 of "HH" can be obtained.

Further, as described above, since the resistance value of the resistance element R31 is sufficiently higher than the on resistance of the N-channel type MOS transistor N31, the output impedance at the connection point K is high, but a low output impedance is not required. , The output signal from the connection point K, and the P-channel type M
It is also possible to eliminate the OS transistor P32, the N-channel type MOS transistor N32 and the inverter I31.

However, when the connection point K is "HH", the high voltage VPP is applied to the N-channel MOS transistor N31 and to the resistance element R31 when it is "L", and the output signal OUT31 is "L". In the case of "HH", the P-channel MOS transistor P32
Since the high voltage VPP is applied to the OS transistor N32, the resistance element R31, the N-channel type MOS transistors N31 and N32 and the P-channel type MOS transistor P are provided.
32 must have a high withstand voltage structure that can withstand the high voltage VPP, and a large number of manufacturing steps must be added to make the resistance element and the MOS transistor a high withstand voltage structure, which complicates the manufacturing process and increases the manufacturing cost. Has the problem of becoming.

Further, Japanese Patent Application Laid-Open No. 4-277920 discloses another conventional high voltage level shift circuit. As shown in FIG. 9 (a), a P channel type MOS is provided between VPP and GND. A transistor P41 and an N-channel MOS transistor N having an input signal IN4 applied to its gate
41 connected in series, a P-channel type MOS transistor P42 between VPP and GND, and an N-channel type MOS transistor N to which the inverted signal IN4 obtained by inverting the input signal IN4 by the inverter I41 is applied to the gate.
And a series circuit in which 42 is connected in series, and a P-channel type MOS transistor P43 between VPP and GND, and a series circuit in which an N-channel type MOS transistor having an input signal IN4 applied to its gate is connected in series. There is.

The gates of the P-channel MOS transistors P41 and P43 are P-channel MOS transistors P.
42 and the N-channel MOS transistor N42, and the gate of the P-channel MOS transistor P42 is connected to the connection point M.
41 and an N-channel type MOS transistor N41, and a P-channel type MOS transistor P43.
The output inversion signal OUT41 is taken out from the connection point between the N-channel MOS transistor N43 and the N-channel MOS transistor N43.

Next, the operation will be described with reference to FIG. First, when the input signal IN4 is "L", the N-channel type MOS transistors N41 and N43 are turned off,
Since the inverted input inversion signal IN4 becomes "H", N
The channel type MOS transistor N42 is turned on and the connection point M is pulled down to "L", the P channel type MOS transistors P41 and P43 are turned on and the connection point L is "H".
The P-channel type MOS transistor P42 is pulled up to H "and turned off, and the output inversion signal OUT41 becomes" HH ".

On the other hand, when the input signal IN4 is "H", N
Since the channel type MOS transistors N41 and N43 turn on and the inverted input inversion signal IN4 becomes "L", the N channel type MOS transistor N42 turns off and the connection point L and the output inversion signal OUT41 pull down to "L". Then, the P-channel MOS transistor P42 is turned on, the connection point M is pulled up to "HH", and the P-channel MOS transistors P41 and P43 are turned off.

As described above, according to the conventional high voltage level shift circuit shown in FIG. 9A, the high voltage is controlled by the input signal IN4 swinging between VPP and GND, and "L" and "HH" are controlled. Output inversion signal OUT41 of
Further, a P-channel type MOS transistor P41, an N-channel type MOS transistor N41, a P-channel type MOS transistor
Transistor P42 and N channel type MOS transistor N42 and P channel type MOS transistor P43 and N
The channel type MOS transistor N43 is turned on complementarily,
Since it is off, it also has the advantage that no through current flows in the circuit and power consumption is extremely small.

Further, a P-channel type MOS transistor P4
Since it is necessary to pull down the potentials of the connection points L and M pulled up by 1 and P42 by the N channel type MOS transistors N41 and N42,
On Resistance of Transistor P41) >> (N-Channel MO
The on-resistance of the S-transistor N41) and the (on-resistance of the P-channel MOS transistor P42) >> (the on-resistance of the N-channel MOS transistor N42), so that the output impedance of the connection points L and M Is high, but when low output impedance is not required, output signals are taken out from the connection points L and M, and P
It is also possible to omit the channel type transistor P43 and the N channel type MOS transistor N43.

However, also in this conventional example, the connection point L is
And M are "HH", the high voltage VPP is applied between the drain and source of the N-channel type MOS transistors N41 and N42.
Is "L", the high voltage VPP is applied between the drain and source of the P-channel MOS transistors P41 and P42, and when the output inversion signal OUT41 is "HH", the drain of the N-channel MOS transistor N43. -When the high voltage VPP is between the source and "L", the high voltage VPP is applied between the drain and the source of the P-channel MOS transistor P43, so that the P-channel MOS transistors P41, P42 and P43 are connected to the N-channel. Type MO
S transistors N41, N42 and N43 are high voltage VPP
Must have a high withstand voltage structure that can withstand high voltage, and a large number of manufacturing steps must be added in order to make the MOS transistor a high withstand voltage structure, resulting in complicated manufacturing steps and high manufacturing costs. .

In order to solve the above-mentioned problem, a high voltage level shift circuit which can be constructed without using a MOS transistor having a high breakdown voltage structure is disclosed in, for example, Japanese Patent Laid-Open No. 62-62.
149218, and FIG.
As shown in (a), a P-channel MOS transistor P having an input signal IN5 applied to its gate between VPP and GND.
51, and P-channel type MOS transistors P52 and N having voltages VMP / 2 and VMN near VPP / 2 applied to their gates.
It is composed of a series circuit in which a channel type MOS transistor N52 and an N channel type MOS transistor N51 having an input signal IN5 applied to its gate are connected in series. The substrate electrode of the P channel type MOS transistor P52 is connected to VPP, and an N channel type The substrate electrode of the MOS transistor N52 is connected to GND, and the P-channel MOS transistor P52 and the N-channel MOS transistor N52 are connected.
The output inversion signal OUT51 is taken out from the connection point of.

Next, the operation will be described with reference to FIG. First, when the input signal IN5 is "L", P
The channel-type MOS transistor P51 turns on, the connection point N between the P-channel type MOS transistors P51 and P52 becomes "HH", and the N-channel type MOS transistor N51 turns off.

Further, since the connection point N is "HH",
If (VPP)> (VMN + | VTP |), the P-channel MOS transistor P52 is also turned on and the output inversion signal OU
T51 becomes "HH", and the connection point O between the N-channel MOS transistors N51 and N52 reaches (VMN-VTN).
It is pulled up and stabilized via the N-channel MOS transistor N52.

Here, VTP is a threshold voltage of the P-channel type MOS transistor P52, and the threshold voltage of the P-channel type MOS transistor is hereinafter referred to as VTP, and VTN
Is the threshold voltage of the N-channel MOS transistor N52, and the threshold voltage of the N-channel MOS transistor is hereinafter referred to as VTN.

On the other hand, when the input signal IN5 is "HH",
The N-channel MOS transistor N51 turns on and the connection point O becomes "L", and the P-channel MOS transistor P51 turns off. Further, since the connection point O is “L”, if (VMN)> (VTN), then N-channel type M
The OS transistor N52 also turns on, and the output inversion signal OUT
51 becomes "L", and the connection point N is pulled down to (VMP + | VTP |) through the P-channel MOS transistor P52 and stabilized.

Even when the input signal IN5 is "H" as shown by the broken line, (ON resistance of P-channel MOS transistor P51) >> (ON resistance of N-channel MOS transistor N51 + N-channel MOS transistor) N52), the same operation as when the input signal IN5 is “HH” is performed except that the P-channel MOS transistor P51 is always on. it is obvious.

Here, the output inversion signal OUT51 is "H".
In the case of H ", a voltage (VPP-VMN + VTN) is applied between the drain and source of the N-channel MOS transistor N52, and a voltage (VMN-VTN) is applied between the drain and source of the N-channel MOS transistor N52. So
By setting VMN to a voltage near VPP / 2, application of high voltage is avoided, and N-channel MOS
Even the breakdown voltage between the drain of the transistor N52 and the substrate is VPP
If it is above, N channel type MOS transistor N51
And N52 need not have a high breakdown voltage structure.

When the output inversion signal OUT51 is "L", a voltage (VMP + │VTP│) is applied between the drain and the source of the P-channel type MOS transistor P52 and between the drain and the source of the P-channel type MOS transistor P51. Since a voltage of (VPP-VPM- | VTM |) is applied to
By setting VMP to a voltage in the vicinity of VPP / 2, it is possible to avoid applying a high voltage, and if the drain breakdown voltage of the P-channel MOS transistor P52 is VPP or more, the P-channel MOS transistors P51 and P52 have a high breakdown voltage. It does not need to be structured.

An example of a circuit for generating VMP and VMN is shown in FIG. 13, and a resistor element R71 is provided between VPP and GND.
And R72 are connected in series, and VMP and VMN are resistive elements R
It is taken out from the connection point of 71 and R72, and the value is given by the following equation.

VMP = VMN = R71 / (R71 + R72) (Equation 1) In this example, VMP = VMN, but if the voltage is in the vicinity of VPP / 2, VMP ≠ VMN, the above-described effect is obtained. It is obvious that

As described above, according to the high voltage circuit shown in FIG. 10A, a high voltage is generated by the input signal IN5 oscillating between VDD and GND without using a MOS transistor having a high breakdown voltage structure. It can be controlled to function as a high voltage level shift circuit that can obtain the output inversion signal OUT51 of "L" and "HH".

Further, in Japanese Patent Laid-Open No. 62-149218, another high voltage level shift circuit is also proposed. As shown in FIG. 11 (a), a P-channel type MOS transistor P61 is provided between VPP and GND. , A P-channel type MOS transistor P62 and an N-channel type MOS transistor N62 to which the voltages VMP and VMN near VPP / 2 are applied to the gate, and an N-channel type MOS transistor N61 to which the input signal IN6 is applied to the gate are connected in series. Connected series circuit, P-channel type MOS transistor P63 between VPP and GND, and P-channel type MOS transistor P6 in which voltages VMP and VMN near VPP / 2 are applied to the gate.
4 and an N-channel type MOS transistor N64, and an N-channel type MOS transistor N63 to which the inverted signal IN6 obtained by inverting the input signal IN6 by the inverter I61 is applied to the gate is connected in series.

The gate of the P-channel type MOS transistor P61 is at the connection point of the P-channel type MOS transistor P64 and the N-channel type MOS transistor N64, and the gate of the P-channel type MOS transistor P63 is the P-channel type MOS transistor P62 and the N-channel type MOS transistor. It is connected to the connection point of the transistor N62 and the substrate electrodes of the P-channel type MOS transistors P61 and P64 are at VPP, and the N-channel type MOS transistors N62 and N62 are
64 substrate electrodes are connected to GND, and P-channel type M
A pair of complementary output signals OUT61 is taken out from the connection point between the OS transistor P62 and the N-channel MOS transistor N62 and the connection point between the P-channel MOS transistor P64 and the N-channel MOS transistor N64.

Next, the operation will be described with reference to FIG. First, when the input signal IN6 is "L", the N-channel MOS transistor N61 is turned off and inverted, and the input inversion signal IN6 becomes "H". Therefore, the N-channel MOS transistor N63 is turned on and the N-channel MO transistor N63 is turned on.
If the connection point S between the S transistors N63 and N64 is pulled down to "L" and (VMN)> (VTN), the N-channel MOS transistor N64 is also turned on and the output signal OU is output.
T61 becomes "L", and the connection point R between the P-channel MOS transistors P63 and P64 becomes (VMP + | VTP
Up to |) and is pulled down and stabilized via the P-channel MOS transistor P64.

Further, since the output signal OUT61 becomes "L", the P-channel type MOS transistor P61 is turned on, so that the P-channel type MOS transistors P61 and P6.
The connection point P of 2 is pulled up to "HH", and (VPP-
VMP)> | VTP |, the P-channel MOS transistor P62 is turned on and the output inversion signal OUT61 is also "H".
H ”, and the N-channel MOS transistor N
The connection point Q between 61 and N62 is pulled up and stabilized up to (VMN-VTN) via the N-channel MOS transistor N62.

On the other hand, when the input signal IN6 is "H", N
If the channel MOS transistor N61 is turned on and the connection point Q is pulled down to "L" and VMN> VTN, the N channel MOS transistor N62 is also turned on and the output inversion signal OUT61 becomes "L". Furthermore, the connection point P is (V
MP + | VTP |) is pulled down through the P-channel MOS transistor P62 and stabilized.

Further, since the inverted input inversion signal IN6 becomes "L", the N channel type MOS transistor N6
3 turns off, and the output signal OUT61 becomes "L", so P
Since the channel type MOS transistor P63 is turned on,
The connection point R is pulled up to "HH", and (VPP-VM
If P)> | VTP |, the P-channel MOS transistor P64 turns on and the output signal OUT61 also becomes "HH", the P-channel MOS transistor P61 turns off, and the connection point S reaches (VMN-VTN). , And is pulled up through the N-channel type MOS transistor N64 to be stable.

Here, similarly, a voltage of (VPP-VMN + VTN) is applied between the drains and sources of the N-channel MOS transistors N62 and N64, and a voltage (VMN-VTN) is applied between the drains-sources of the N-channel MOS transistors N61 and N63. VTN) is applied, so VMN is VPP /
By setting the voltage in the vicinity of 2, application of a high voltage is avoided, and the N-channel MOS transistor N
As long as the drain breakdown voltage of 62 and N64 is VPP or more, it is not necessary to make the N-channel type MOS transistors N61, N62, N63 and N64 into a high breakdown voltage structure.

Further, a P-channel type MOS transistor P6
2 and P64 drain-source (VMP + | VTP
The voltage of |) is the P-channel type MOS transistor P61.
And between the drain and source of P63 (VPP-VMP- |
Since the voltage VTP |) is applied, it is possible to avoid applying a high voltage by setting VMP to a voltage near PP / 2, and the drain breakdown voltage of the P-channel MOS transistors P62 and P64 must be VPP or more. For example, P-channel type MOS transistors P61, P62, P63 and P6
4 does not need to have a high breakdown voltage structure.

As described above, according to the high voltage level shift circuit shown in FIG. 11A, the high voltage MO structure is high.
It is possible to obtain a pair of complementary output signals OUT61 of "L" and "HH" by controlling the high voltage with the input signal IN6 swinging between VDD and GND without using the S transistor. Furthermore, a P-channel type MOS transistor P61
Since the N-channel type MOS transistor N61 and the P-channel type MOS transistor P63 and the N-channel type MOS transistor N63 are complementarily turned on and off, a through current does not flow and power consumption is extremely reduced. There is.

Further, US Pat. No. 5,243,236 also proposes a high voltage level shift circuit, which is shown in FIG. This embodiment is based on FIG.
It differs from the embodiment shown in (a) only in that the substrate electrodes of the P-channel type MOS transistors P62 and P64 are connected to the sources, and therefore the same reference numerals as those in FIG. The description is omitted.

In the embodiment shown in FIG. 12, since the substrate electrodes of the P-channel type MOS transistors P62 and P64 are connected to the sources, (voltage applied between drain and source) = (drain and substrate) Applied voltage)
And P-channel MOS transistors P62 and P
Even if the breakdown voltage between the drain of 64 and the substrate is VPP or less,
It has the advantage of working correctly.

Regarding other operations, the operation shown in FIG.
It is similar to the embodiment shown in (a), and the same reference numerals are given and the description thereof is omitted here. In FIG. 12, the substrate electrodes of the N-channel type MOS transistors N62 and N64 are GN.
Since it is connected to D, the drain breakdown voltage of the N-channel MOS transistors N62 and N64 needs to be VPP or higher.
It is also clear that by connecting the substrate electrodes of 62 and N64 to the source, it is possible to operate properly if the drain breakdown voltage is (VPP-VMN-VTN) or higher.

[0043]

In the conventional high voltage level shift circuit shown in FIG. 10A, when the input signal IN5 is "L", that is, the GND level, the P channel type M
Since the OS transistor P51 is turned on and both the drain and the source are at "HH", that is, VPP level, a high voltage VPP is applied to the gate oxide film of the P-channel type MOS transistor P51.

However, since the gate oxide film is becoming thinner along with the miniaturization of MOS transistors in recent years, a strong electric field of 10 MV / cm or more is applied to the gate oxide film, and the film quality of the gate oxide film is rapidly deteriorated. There is a problem that the gate oxide film is destroyed and the circuit operation becomes impossible.

Also in the conventional high voltage level shift circuit shown in FIG. 11A, when the output signal OUT61 is "L", both the drain and the source of the P-channel type MOS transistor P61 become VPP and the gate oxide film becomes VPP. Is applied and the output inversion signal OUT61 is "L", P
Both the drain and source of the channel type MOS transistor P63 become VPP, VPP is applied to the gate oxide film, the film quality of the gate oxide film is rapidly deteriorated as described above, and the gate oxide film is destroyed, so that the circuit cannot operate. There is a problem that it falls into.

Further, also in the conventional high voltage level shift circuit shown in FIG. 12, the gate oxide films of the P channel type MOS transistors P61 and P63 are formed similarly to the conventional high voltage level shift circuit shown in FIG. 11A. Since VPP is applied, there is a problem that the film quality of the gate oxide film is rapidly deteriorated and the gate oxide film is destroyed, which makes the circuit operation impossible.

In the conventional high voltage level shift circuit shown in FIG. 8A, the P channel type MOS transistor P is used.
Since the VPP is applied to the gate oxide film of P channel type MOS transistors P41, P42 and P43 in the conventional high voltage level shift circuit shown in FIG. It is also clear to have dots.

It is an object of the present invention to use a MOS transistor having a high withstand voltage structure and to have a high reliability in which the gate oxide film of the MOS transistor is deteriorated and destroyed so that the circuit cannot operate. It is to provide a voltage level shift circuit.

[0049]

SUMMARY OF THE INVENTION A voltage level shift circuit according to the present invention is a voltage level shift circuit which responds to a logic input of a predetermined amplitude level to generate a logic output having an amplitude VPP greater than said amplitude level. And a load element,
A first-conductivity-type first MOS transistor in which a voltage of approximately VPP / 2 level is applied to the gate, a second-conductivity-type second MOS transistor in which a voltage of approximately VPP / 2 level is applied to the gate, and a gate The third MOS transistor of the opposite conductivity type to which the logic input is applied is serially connected in this order between the power supply voltage VPP and the ground, and the first and second MO transistors are connected in series.
The logic output is derived from the connection point of the S transistor.

Further, the voltage level shift circuit according to the present invention is a voltage level shift circuit which generates a logic output having an amplitude VPP larger than the amplitude level in response to a logic input having a predetermined amplitude level. Type first MOS
A transistor and the second MOS transistor of one conductivity type having a gate to which a voltage of approximately VPP / 2 level is applied;
A reverse conductivity type third MOS transistor having a gate to which a voltage of approximately VPP / 2 level is applied, and a reverse conductivity type fourth MOS transistor having the gate to which the logic input is applied are the power supply voltage VPP in this order. And a fifth MOS transistor of one conductivity type, and a sixth MOS transistor of one conductivity type having a voltage of approximately VPP / 2 level applied to its gate.
, A reverse conductive type seventh MOS transistor whose gate is applied with a voltage of approximately VPP / 2 level, and a reverse conductive type eighth MOS transistor whose gate is applied with an inverted signal of the logic input. A MOS transistor is connected in series between the power supply voltage VPP and ground in this order, and the gate of the first MOS transistor is connected to the fifth and sixth M transistors.
The fifth MO is connected to the connection point of the OS transistor.
The gate of the S transistor is the first and second MOS
Connected to a connection point of the transistor,
Connection point of the MOS transistor and the sixth and seventh
Is characterized by deriving a pair of complementary logic outputs from the connection points of the MOS transistors.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION The operation of the present invention will be described. Basically, a load element, a MOS transistor of one conductivity type whose gate is biased to approximately 1/2 of the high voltage, and a high voltage of approximately 1
A reverse-conductivity-type MOS transistor whose gate is biased at / 2 and a reverse-conductivity-type MOS transistor in which a low-amplitude logic input is applied to the gate are connected in series in this order between the high voltage and the GND. The voltage applied to the gate film of the transistor is reduced.

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a circuit diagram showing a first embodiment of the present invention, in which a resistance element R11 functioning as a load element L11 is provided between VPP and GND, and a gate has a voltage VMP near VPP / 2. A P-channel MOS transistor P12 to which is applied, an N-channel MOS transistor N12 to which a voltage VMN near VPP / 2 is applied to the gate, and an N-channel MOS transistor N11 to which the input signal IN1 is applied to the gate are connected in series. It is composed of connected series circuits.

The substrate electrode of the P-channel MOS transistor P12 is at VPP, and the N-channel MOS transistor N is
The 12 substrate electrodes are respectively connected to GND, and the output inversion signal OUT11 is taken out from the connection point of the P-channel type MOS transistor P12 and the N-channel type MOS transistor N12.

Next, the operation will be described with reference to FIG. First, when the input signal IN1 is "L", the N-channel type MOS transistor N11 is turned off and the current path is cut off.
The potential at the connection point A of the transistor is pulled up to "HH" by the resistance element R11 and (VPP-VMP).
> | VTP |, P-channel MOS transistor P
12 is turned on and the output signal OUT11 also becomes “HH”,
The connection point B between the N-channel MOS transistors N11 and N12 is pulled up and stabilized up to (VMN-VTN) via the N-channel MOS transistor N12.

On the other hand, when the input signal IN1 is "H", N
The channel-type MOS transistor N11 turns on and the connection point B becomes "L". If VMN> VTN, the N-channel MOS transistor N12 also turns on and the output inversion signal OUT11 also becomes "L", and the connection point A becomes (VMP + | VTP
Up to |) and is pulled down and stabilized via the P-channel MOS transistor P12.

As described above, according to the first embodiment of the present invention shown in FIG. 1 (a), the high voltage is controlled by the input signal IN11 oscillating between VDD and GND, and the voltage becomes "L". "H
An output inverted signal OUT11 of H ″ can be obtained.

The resistance element R11 has the highest (VPP-VMP- |
The voltage of VTP |) is the P-channel MOS transistor P
12 drain to source maximum (VMP + | VTP |)
Is the maximum voltage (VMN-VTN) between the drain and source of the N-channel type MOS transistor N11.
Since the maximum voltage (VPP-VMN + VTN) is applied between the drain and the source of the channel type MOS transistor N12, by setting VMP and VMN to a voltage near VPP / 2, the drain and the source of the MOS transistor can be set. The high voltage VPP is prevented from being applied to the resistance element P11, the P-channel type MOS transistor P12, and the P-channel type MOS transistor P12.
It is not necessary to make the channel type MOS transistors N11 and N12 have a high breakdown voltage structure. Therefore, the problem that the manufacturing process becomes complicated and the manufacturing cost becomes high is solved.

Further, the gate oxide film of the P-channel type MOS transistor P12 has a maximum voltage (VPP-VMP), and the gate oxide film of the N-channel type MOS transistor N11 has a maximum voltage of VDD and an N-channel type MOS transistor. Since a voltage of maximum VMN is applied to the gate oxide film of N12, setting a voltage near VPP / 2 to VMP and VMN avoids applying a strong electric field to the gate oxide film of the MOS transistor. In addition, the gate oxide film is not deteriorated and the gate oxide film is destroyed, so that the circuit cannot be operated.

An example of a circuit for generating VMP and VMN is shown in FIG. 13, but since it has already been described, its description is omitted here. In this example, VMP = VMN, but VPP /
It is clear that if the voltage is in the vicinity of 2, the above-mentioned effect can be obtained even if VMP ≠ VMN.

FIG. 2A is a circuit diagram showing a second embodiment of the present invention, which is the P-channel MOS transistor P12 in the first embodiment of the present invention shown in FIG. 1A. The substrate electrode of P-channel type MOS transistor P
The source of 12 has an N-channel MOS transistor N1
The substrate electrode 2 is an N-channel MOS transistor N12
Are connected to each source.

Further, instead of the N-channel type MOS transistor N11 of FIG. 1A, an input signal IN1A is applied to the gate.
Channel MOS transistor N11A to which is applied
And a N-channel MOS transistor N11B having an input signal IN1B applied to its gate are connected in series, and an N-channel MOS transistor N11C having an input signal IN1C applied to its gate is connected in parallel. Is configured.

The other parts are the same as those in the first embodiment of the present invention described above, and the same reference numerals are given to omit the description here.

Next, the operation will be described with reference to FIG. Similar to the first embodiment of the present invention, either or both of N-channel MOS transistors N11A and N11B connected in series are turned off by applying "L" to the gate, and the gate of N-channel MOS transistor N11C is turned on. When "L" is applied to turn off and the current path is disconnected, the output inversion signal OUT12 becomes "HH" and N
“H” is applied to the gates of the channel type MOS transistors N11A and N11B to turn on or N channel type M
When "H" is applied to the gate of the OS transistor N11C to turn it on to form a current path, the output inversion signal OU
T12 becomes "L".

The operation of other parts is the same as that of the first embodiment according to the present invention described above, and the description thereof is omitted here.

As described above, according to the second embodiment of the present invention shown in FIG. 2A, in addition to the advantages described in the first embodiment of the present invention, the P-channel MOS transistor is provided. Since the substrate electrodes of the P12 and N-channel MOS transistor N12 are connected to the sources, respectively, the maximum voltage (VMP + | VTP |) between the drain of the P-channel MOS transistor P12 and the substrate is the N-channel MO transistor.
The maximum between the drain of the S transistor N12 and the substrate (V
(PP-VMN + VTN) voltage is applied and high voltage VPP is not applied, so the breakdown voltage between drain and substrate is VPP.
There is an advantage that it operates correctly even in the following cases.

Further, a high voltage (IN1) is applied to input signals IN1A, IN1B and IN1C which swing between VDD and GND.
A.IN1B + IN1C) has the advantage that an output inversion signal OUT12 controlled according to the logic represented by the negation of A.IN1B + IN1C) is obtained.

It is obvious that the high voltage can be controlled with an arbitrary logic by changing the configuration of the logic circuit regardless of the present embodiment.

FIG. 3 (a) is a circuit diagram showing a third embodiment of the present invention. In the first embodiment of the present invention shown in FIG. 1 (a), VMP is applied to the gate as the load element L11. The applied P-channel type MOS transistor P11 is connected and the gate is a P-channel type M transistor between VPP and GND.
A P-channel MOS transistor P13 connected to a connection point A between the OS transistors P11 and P12, and a P-channel MO transistor having a gate applied with a voltage VMP near VPP / 2
N-channel MOS transistor N1 with the voltage VMN near VPP / 2 applied to the gate of the S transistor P14
4 and an N-channel type MOS transistor N13 to which the input inversion signal IN1 obtained by inverting the input signal IN1 by the inverter I11 is applied to the gate are connected in series.

Further, the P-channel type MOS transistor P
The substrate electrode of 14 is the high-voltage power supply terminal VPP, and the substrate electrode of the N-channel MOS transistor N14 is the ground terminal GND.
Connected to a P-channel MOS transistor P14
The output signal OUT13 is taken out from the connection point between the N-channel type MOS transistor N14 and the N-channel type MOS transistor N14.

Next, the operation will be described with reference to FIG. However, P-channel type MOS transistor P11
Since a voltage VMP in the vicinity of VPP / 2 is applied to its gate to turn it on, it functions as a load element like a resistance element. Therefore, the P-channel MOS transistors P11 and P
12 and N channel type MOS transistors N11 and N
The operation of the first series circuit constituted by 12 is the same as that of the first embodiment of the present invention described above, so that the connection point A
The potential changes of B and B are shown in FIG. 3B, and the description here is omitted.

When the input signal IN1 is "L", the inverted input inverted signal IN1 becomes "H" and the N-channel type M
The OS transistor N13 is turned on to turn on the N-channel type MOS.
The connection point D between the transistors N13 and N14 is pulled down to "L". Further, if VMN> VTN, the N-channel type MOS transistor N14 is also turned on to output the output signal OUT1.
3 becomes "L" and the potential of the connection point A becomes "HH", the P-channel MOS transistor P13 is turned off, and the connection point C of the P-channel MOS transistors P13 and P14 is (VMP + | VTP |). Up to P-channel MO
Through the S transistor P14, it is pulled down and stabilized.

On the other hand, when the input signal IN1 is "H", the connection point A becomes (VMP + | VTP |), so that (VPP-VMP-
If | VTP |)> | VTP |, the P-channel MOS transistor P13 is turned on and the connection point C is pulled up to "HH". If (VPP-VMP)> | VTP | The transistor P14 also turns on, the output inversion signal OUT13 also becomes "HH", and the input signal IN1
The input inversion signal IN1 which has been inverted becomes "L", the N-channel MOS transistor N13 is turned off, and the connection point D between the N-channel MOS transistors N13 and N14 reaches (VMN-VTN) until the N-channel MOS transistor is reached. It is pulled up and stabilized via N14.

As described above, the P-channel type MOS
The highest (VPP-VMP- | VTP |) voltage is between the drain and source of the transistors P11 and P13, and the highest (VMP + | VTP |) voltage is between the drain and source of the P-channel MOS transistors P12 and P14. , The highest voltage (VMN-VTN) between the drain and the source of the N-channel type MOS transistors N11 and N13 is the drain of the N-channel type MOS transistors N12 and N14.
Since the maximum voltage (VPP-VMN + VTN) is applied between the sources, by setting VMP and VMN to voltages near VPP / 2, the drain of the MOS transistor
The application of high voltage VPP between the sources is avoided and P
Channel type MOS transistors P11, P12, P13
And P14 and N-channel type MOS transistor N11,
It is not necessary to provide N12, N13 and N14 with a high breakdown voltage structure.

Therefore, there is no problem that the manufacturing process becomes complicated and the manufacturing cost becomes high, and the highest voltage (VPP-VMP) is applied to the P-channel MOS transistors P11, P12 and P14. Type MOS transistor P13 has the highest gate oxide film (VPP-VMP
-| VTP |), and the voltage of the maximum VDD in the gate oxide films of the N-channel type MOS transistors N11 and N13 is N-channel type MOS transistors N12 and N14.
A voltage of maximum VMN is applied to the respective gate oxide films.

Therefore, by setting VMP and VMN to a voltage near VPP / 2, it is possible to avoid applying a strong electric field to the gate oxide film of the MOS transistor, which deteriorates the gate oxidation, resulting in destruction of the gate oxide film. This has an advantage that the circuit operation does not fall into an impossible state.

Further, since the P-channel type MOS transistor P13 and the N-channel type MOS transistor N13 are turned on and off in a complementary manner, power consumption does not increase even if the driving capability is set to a large value. It also has the advantage that it can be driven at high speed without increasing power consumption.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. In addition to the above-described second embodiment of the present invention, the P-channel type M of the third embodiment of the present invention described above is provided.
OS transistors P13 and P14 and N-channel type M
It is configured by connecting a second series circuit configured by the OS transistors N13 and N15. The substrate electrodes of the P-channel MOS transistors P12 and P14 are P-channel MOS transistors P, respectively.
12 and P14, the substrate electrodes of the N-channel MOS transistors N12 and N14 are connected to the sources of the N-channel MOS transistors N12 and N14, respectively, and the gate of the N-channel MOS transistor N13 is connected to the N-channel MOS transistor N12. N-channel type MOS transistors N11A, N11B and N11
It is connected to the connection point B of the logic circuit composed of C, and P
Channel type MOS transistor P14 and N channel type M
Output signal OUT1 from the connection point of the OS transistor N14
4 is taken out.

The other parts are the same as those in the second and third embodiments of the present invention described above, and the same reference numerals are given and the description thereof is omitted here.

Next, regarding the operation, since the signal is inverted by the series circuit composed of the P-channel type MOS transistors P13 and P14 and the N-channel type MOS transistors N13 and N14, the output signal OUT14 of FIG.
A signal obtained by inverting the output inversion signal OUT12 shown in (b), that is, a signal in which "HH" is replaced with "L" and "L" is replaced with "HH", and the operation of other parts is according to the present invention described above. Since it is the same as the second and third embodiments, the same reference numerals are given and description thereof is omitted here.

According to the fourth embodiment of the present invention shown in FIG. 4, application of the high voltage VPP between the drain and source of the MOS transistor is avoided as described above, and the MO
Since the S-transistor does not need to have a high breakdown voltage structure, the manufacturing process does not become complicated and the manufacturing cost does not increase, application of a strong electric field to the gate oxide film of the MOS transistor is avoided, and the gate oxide film deteriorates. However, the gate oxide film will not be destroyed and the circuit operation will not be impossible. Further, there is an advantage that a high voltage can be controlled by an arbitrary logic by an input signal oscillating between VDD and GND, and a large capacity load can be driven at high speed without an increase in power consumption.

Further, since the substrate electrodes of the P-channel type MOS transistors P12 and P14 and the substrate electrodes of the N-channel type MOS transistors N12 and N14 are connected to the sources, even if the breakdown voltage between the drain and the substrate is VPP or less, Operate. Further, the gate of the N-channel type MOS transistor N13 has the N-channel type MOS transistor N13.
12 and N channel type MOS transistors N11A, N1
Since it is connected between the logic circuits composed of 1B and N11C, input signals IN1A, IN1B and IN1
It also has an advantage that a circuit for inverting C and establishing a logic is unnecessary.

FIG. 5A is a circuit diagram showing a fifth embodiment of the present invention, in which a P channel type MO is provided between VPP and GND.
S-transistor P21 and P-channel MOS transistor P2 having a gate applied with a voltage VMP near VPP / 2.
2 and the voltage VMN near VPP / 2 applied to the gate N
A series circuit is provided in which a channel type MOS transistor N22 and an N channel type MOS transistor N21 whose gate receives the input signal IN2 are connected in series.

Further, a P channel type M is provided between VPP and GND.
OS transistor P23 and P-channel MOS transistor P having a gate applied with a voltage VMP near VPP / 2
24 and an N-channel MOS transistor N24 to which the voltage VMN near VPP / 2 is applied to the gate, and an N-channel MOS transistor N23 to which the input inversion signal IN2 obtained by inverting the input signal IN2 by the inverter I21 is applied to the gate. And a series circuit in which are connected in series.

The gate of the P channel type MOS transistor P21 has P channel type MOS transistors P23 and P2.
P-channel MOS transistor P at the connection point G with
The gate of 23 is a P-channel type MOS transistor P21
Is connected to the connection point E between P22 and P22, and the substrate electrodes of the P-channel MOS transistors P22 and P24 are VPP.
And N-channel type MOS transistors N22 and N24
Has a substrate electrode connected to GND, and has a P-channel MOS transistor P22 and an N-channel MOS transistor N.
22 connection point and P-channel MOS transistor P
A pair of complementary output signals OUT21 is taken out from a connection point between the N.sub.24 and the N channel type MOS transistor N24.

Next, the operation will be described with reference to FIG. First, when the input signal IN2 is "L", the N-channel MOS transistor N21 is turned off, and the inverted input inversion signal IN2 is "H", the N-channel MOS transistor N23 is turned on and the N-channel MOS transistor N23 is turned on. If the connection point H between the transistors N23 and N24 is pulled down to "L" and VMN> VTN, then an N-channel type MOS
The transistor N24 is also turned on, the output signal OUT21 becomes “L”, and the connection point G is (VMP + | VTP |) up to P.
It is pulled down and stabilized via the channel MOS transistor P24.

Further, (VPP-VMP- | VTP |)> | V
If TP |, the P-channel MOS transistor P21 is turned on, the connection point F is pulled up to "HH", and the P-channel MOS transistor P23 is turned off.
If (VPP-VMP)> | VTP |, P-channel type MOS
The transistor P22 turns on and the output inversion signal OUT21
Also becomes "HH", and the N-channel MOS transistor N
The connection point F between 21 and N22 is pulled up and stabilized up to (VMN-VTN) via the N-channel MOS transistor N22.

On the other hand, when the input signal IN2 is "H", N
The channel type MOS transistor N21 is turned on and the connection point F is pulled down to "L". If VMN> VTN, the N channel type MOS transistor N22 is also turned on and the output inversion signal OUT21 becomes "L", so that the connection point E is (VMP + ｜ VTP
Up to |), it is pulled down and stabilized via the P-channel MOS transistor P22, and the inverted input inversion signal IN2 becomes "L", and the N-channel MOS transistor N23 is turned off.

Further, (VPP-VMP- | VTP |)> | V
If TP |, the P-channel MOS transistor P23 is turned on, the connection point G is pulled up to "HH", and the P-channel MOS transistor P21 is turned off.
If (VPP-VMP)> | VTP |, P-channel type MOS
The transistor P24 is turned on and the output signal OUT21 also becomes "HH", and the connection point H is pulled up and stabilized via the N-channel MOS transistor N24 until (VMN-VTN).

As described above, according to the fifth embodiment of the present invention shown in FIG. 5 (a), the high voltage is controlled by the input signal IN2 oscillating between VDD and GND, and the voltage becomes "L". "H
A pair of complementary output signals OUT21 of H ″ can be obtained, and P-channel type MOS transistors P21 and P23 can be obtained.
Is the highest between the drain and source of (VPP-VMP- | VTP
The voltage of |) is the P-channel type MOS transistor P22.
And between the drain and source of P24 is the highest (VMP- | V
The voltage of TP |) is the N-channel MOS transistor N2
1 and the maximum between N23 drain-source (VMN-V
The voltage of (TN) is the N-channel MOS transistor N22
And between the drain and source of N24 is the highest (VPP-VMN
+ VTN) voltage is applied to each.

Therefore, by setting VMP and VMN to voltages near VPP / 2, it is possible to avoid applying a high voltage between the drain and source of the MOS transistor, and it is not necessary to provide a high breakdown voltage structure. The problem that the process is complicated and the manufacturing cost is high is solved.

Further, the gate oxide films of the P-channel type MOS transistors P21 and P23 have the highest (VPP-VMP
-| VTP |) is the highest voltage (VPP-V) on the gate oxide films of the P-channel MOS transistors P22 and P24.
MP) voltage is N-channel MOS transistor N21
The maximum VDD voltage is applied to the gate oxide films of N23 and N23, and the maximum VMN voltage is applied to the gate oxide films of the N-channel MOS transistors N22 and N24.

Therefore, by setting VMP and VMN to a voltage in the vicinity of VPP / 2, it is possible to prevent a strong electric field from being applied to the gate oxide film of the MOS transistor, which deteriorates the gate oxide film, resulting in destruction of the gate oxide film. The circuit operation does not fall into the impossible state. Furthermore, P-channel type MOS
Transistor P21 and N channel type MOS transistor N21 and P channel type MOS transistor P23 and N
The channel type MOS transistor N23 is turned on complementarily,
Since it is turned off, it also has an advantage that power consumption is extremely small.

FIG. 6A is a circuit diagram showing a sixth embodiment of the present invention. In the fifth embodiment of the present invention shown in FIG. 5A, a gate is connected between VPP and GND. A P-channel type MOS transistor P25 connected to the point G and a P-channel type M transistor having a gate applied with a voltage VMP near VPP / 2.
N-channel MOS transistor N in which the voltage VMN near VPP / 2 is applied to the OS transistor P26 and the gate
26 and an N-channel type MOS transistor N25 whose gate receives the input signal IN2 are connected in series to add a series circuit.

P-channel type MOS transistor P22,
The substrate electrodes of P24 and P26 are P channel type M
The output inversion signal OUT22 is taken from the connection point between the P-channel MOS transistor P26 and the N-channel MOS transistor N26, which is connected to the sources of the OS transistors P22, P24 and P25. The other parts are the same as those in the fifth embodiment of the present invention described above, and the same reference numerals are given and the description thereof is omitted here.

Next, the operation will be described with reference to FIG. The potential changes at the connection points E, F, G and H described in the fifth embodiment of the present invention are shown in FIG. 6B, and the description thereof is omitted here.

First, when the input voltage IN2 is "L", N
Since the channel type MOS transistor N25 is turned off and the connection point G is (VMP + | VTP |), (VPP-
If VMP- | VTP |)> | VTP |, P-channel type M
The OS transistor P25 is turned on to turn on the P-channel MOS
The connection point I between the transistors P25 and P26 is pulled up to "HH". If (VPP-VMP)> | VTP |, the P-channel type MOS transistor P26 is also turned on, the output inversion signal OUT22 also becomes "HH", and the connection point J between the N-channel type MOS transistors N25 and N26.
Up to (VMN-VTN) through the N-channel MOS transistor N26 and is stabilized.

On the other hand, when the input signal IN2 is "H", N
The channel type MOS transistor N25 is turned on and the connection point J is pulled down to "L". If VMN> VTN, the N channel type MOS transistor N26 is also turned on and the output inversion signal OUT22 is also set to "L". Is "H
H ", the P-channel MOS transistor P2
5 turns off and 6l, so the connection point I becomes (VMP + | VTP
Up to |) and is pulled down and stabilized via the P-channel MOS transistor P26.

As described above, according to the sixth embodiment of the present invention shown in FIG. 6 (a), the high voltage is controlled by the input signal IN2 oscillating between VDD and GND, and the voltage becomes "L". "H
An output inverted signal OUT22 of "H" can be obtained, and the maximum voltage (VPP-VMP- | VTP |) between the drain and source of the P-channel MOS transistor P25 is the drain-source of the P-channel MOS transistor P26. The highest voltage (VMP + | VTP |) between the N-channel type M
The highest voltage (VMN + VTN) is applied between the drain and source of the OS transistor N25, and the highest voltage (VPP-VMN) is applied between the drain and source of the N-channel MOS transistor N26.
+ VTN) voltage is applied to each.

By setting VMP and VMN to a voltage near VPP / 2, it is possible to avoid applying a high voltage VPP between the drain and source of the MOS transistor, and it is not necessary to provide a high breakdown voltage structure. The problem that the process is complicated and the manufacturing cost is high is also solved.

P-channel type MOS transistor P25,
Has the highest (VPP-VMP- | VTP |) voltage for the gate oxide film and the highest (VPP-VMP) voltage for the gate oxide film of the P-channel MOS transistor.
The voltage of maximum VDD is applied to the gate oxide film of the transistor N25, and the voltage of maximum VMN is applied to the gate oxide film of the N-channel type MOS transistor N26.

By setting VMP and VMN to a voltage near VPP / 2, it is possible to avoid applying a strong electric field to the gate oxide film of the MOS transistor, the gate oxide film is deteriorated, and the gate oxide film is destroyed, resulting in a circuit failure. It does not fall into an inoperable state.

Further, since the substrate electrodes of the P channel type MOS transistors P22 and P24 are connected to the sources, the P channel type MOS transistors P22 and P24 are connected.
The maximum voltage applied between the drain and the substrate is (VMP
Since it is suppressed to + | VTP |), there is an advantage that it operates properly even if the breakdown voltage between the drain and the substrate of the P-channel MOS transistors P22 and P24 is VPP or less.

Further, the P-channel type MOS transistor P
25 and the N-channel type MOS transistor N23 complementarily turn on and off, the power consumption does not increase even if the driving capability is set to a large value, so that it is possible to drive a large capacity load at high speed without increasing the power consumption. There are also advantages.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention. In the sixth embodiment of the present invention described above, N-channel type MOS transistors N22, N24 and N26 are used.
Of the substrate electrodes of N-channel MOS transistor N
22 and N26, and an N-channel MOS transistor N21A having an input signal IN2A applied to its gate instead of the N-channel MOS transistor N21 and an input signal IN2B applied to its gate N
The channel-type MOS transistor N21B is connected in series, and the input signal IN2C is applied to its gate.
A logic circuit formed by connecting channel-type MOS transistors N21C in parallel is connected.

Further, the N-channel type MOS transistor N
Instead of 23, an N-channel type MOS transistor N23A having an input signal IN2A having an inverted input signal IN2A applied to its gate and an N-channel type MOS transistor having an input inverted signal IN2B having an inverted input signal IN2B applied to its gate N23B is connected in parallel, and the input signal IN2C is inverted from the input signal IN2C at the gate.
N-channel MOS transistor N2 to which 2C is applied
3C are connected in series, and a logic circuit corresponding to the logic circuit composed of N-channel type MOS transistors N21A, N21B and N21C is connected.

The other parts are the same as those of the sixth embodiment of the present invention shown in FIG. 6A, and the description thereof is omitted here. Also, regarding the operation, the potentials at the connection points E to J are the same as those in the sixth embodiment of the present invention shown in FIG. 6B, and therefore the description thereof is omitted here, and the output inversion signal OUT2 is omitted.
3 is the same as the output inversion signal OUT12 of the second embodiment of the present invention shown in FIG.

In the seventh embodiment of the present invention shown in FIG. 7,
In addition to the advantages of the sixth embodiment of the present invention described above, N
Channel type MOS transistors N22, N24 and N2
Since 6 substrate electrodes are connected to each source, N
Channel type MOS transistors N22, N24 and N2
The maximum voltage applied between the drain of 6 and the substrate is (VPP
-VMN + VTN), which has the advantage that the N-channel MOS transistors N22, N24 and N26 operate correctly even if the breakdown voltage between the drain and the substrate is VPP or less.

Further, a high voltage (IN2A) is generated by the input signals IN2A, IN2B and IN2C which swing between VDD and GND.
The advantage is that the inverted signal OUT23 controlled according to the logic represented by the inversion of (IN2B + IN2C) is obtained.

Incidentally, regardless of the present embodiment, it is clear that the high voltage can be controlled by an arbitrary logic by changing the configuration of the logic circuit in various ways.

FIG. 15A is a circuit diagram showing an eighth embodiment of the present invention. In the fifth embodiment of the present invention described with reference to FIGS. 5A and 5B, the gate is a P channel. Type MOS
Connected to the connection point E of the transistors P21 and P22,
A P-channel MOS transistor P27 having a source connected to VPP, a gate connected to a connection point K of the P-channel MOS transistor P24 and an N-channel MOS transistor N24, and a source having a voltage of approximately VPP / 2 VPP A connection point OUT2 formed by a P-channel type MOS transistor P28 connected to / 2 and connecting the drains of the P-channel type MOS transistors P27 and P28.
Derives the output from 4.

The other parts are the same as those in the fifth embodiment of the present invention described above, and the same reference numerals are given and the description thereof is omitted here.

Next, the operation will be described with reference to FIG. It should be noted that FIG. 5 described in the fifth embodiment of the present invention
The potential change of OUT21 in (b) is replaced with K as it is, and each potential change of the inverting input IN2, connection points E, F, G, and H is shown in FIG. 15 (b), and the description thereof is omitted here.

First, when the input voltage IN2 is "L", since the connection point E is VPP, the P-channel MOS transistor P27 is turned off, and the connection point K is GND, so that the P-channel MOS transistor P28 is turned on. And then V
The potential of PP / 2 is output from OUT24.

On the other hand, when the input voltage IN2 is "H", since the connection point E is (VMP + │VTP│), the P-channel type M
Since the OS transistor P27 is turned on and the connection point K becomes VPP, the P-channel MOS transistor P28
Turns off and "HH" is output from OUT24.

In this embodiment, the high voltage is controlled by the input signal IN2 which swings between VDD and GND to control VPP / 2 and "HH".
Output signal OUT24 of P-channel type MOS transistors P27 and P28.
A voltage of (VPP-VPP / 2) or more is not applied between the sources and the gate oxide film, and even in other MOS transistors, as described in the fifth embodiment of the present invention, the drain- Since a high voltage is not applied between the sources and to the gate oxide film, it is not necessary to provide the MOS transistor with a high breakdown voltage structure, and the gate oxide film is not deteriorated and the circuit operation is not possible.

FIGS. 16A and 16B are circuit diagrams and timings showing a ninth embodiment of the present invention, and the third embodiment of the present invention described with reference to FIGS. 3A and 3B. In the standby state where VPP becomes equal to VDD, for example, VMP applied to the gates of the P-channel MOS transistors P12 and P14 is set to the GND level, and N
The VMN applied to the gates of the channel type MOS transistors N12 and N14 is set to the VDD level.

In this embodiment, when the input signal IN1 is "L", the connection point A becomes VDD and the P channel type M
Since the OS transistor P13 is turned off and the inverting input IN1 becomes "H", the connection point C becomes | VTP |, the connection point D becomes GND, and "L" is output from OUT15.

On the other hand, when the input signal IN1 is "H", the connection point A becomes | VTP | and VDD> 2 | VTP |
Since the P-channel MOS transistor P13 is turned on and the inverting input IN1 becomes "L", the connection point C becomes VDD, the connection point D becomes (VDD-VTN), and "H" is output from OUT15. .

In this embodiment, when the input signal IN1 is "L" and VDD> VTN, the N-channel type MOS transistors N13 and N14 are turned on and "L" is stably output from the OUT13. If IN1 is "H" and VDD> 2│VTP│, the P-channel MOS transistors P13 and P14 are turned on, and "H" is stably output from OUT13.

On the other hand, in the third embodiment of the present invention described with reference to FIGS. 3A and 3B, since VMN = VMP = VPP / 2, the input signal IN1 becomes VPP = VDD when VPP = VDD. When "L", VMN> VTN, that is, VDD> 2VTN, the N-channel MOS transistor N14 is turned on, OUT13 is stably output "L", and when the input signal IN1 is "H", the connection point A is VMP + | VTP |, so VDD>
(VMP + | VTP |) + | VTP | That is, VDD> 4 | VTP |
The P-channel MOS transistor P13 is turned on at O
“H” is stably output from the UT 13.

Therefore, according to the ninth embodiment of the present invention shown in FIGS. 16A and 16B, when VPP = VDD, for example, when the input signal IN1 is "H", VDD > 4
If it is not | VTP |, stable output cannot be obtained and VDD≤4 |
With VTP |, the level shift circuit that may cause circuit malfunction can obtain stable output with VDD> 2 | VTP |
Double voltage reduction can be realized.

In the third embodiment of the present invention shown in FIG. 3, VMP is set to the GND level and VMN is set to the VDD level in the state of VPP = VDD. Also in the first embodiment of the present invention shown in FIG. 2, the second embodiment of the present invention shown in FIG. 2 and the fourth embodiment of the present invention shown in FIG. 4, for example, VPP is VDD level. When VMP is set to the GND level and VMN is set to the VDD level, the ninth aspect of the present invention is achieved.
It is clear that the same effect as the embodiment of
The description here is omitted.

In order to set VMP to the GND level and VMN to the VDD level in the standby state where VPP becomes equal to VDD, for example, as shown in FIG. 20 (a), the VPP described in FIG. 13 is used. In addition to a circuit for generating a voltage in the vicinity of / 2, an N-channel type MOS transistor N72 is connected between the resistance element R71 and GND so that the gate of N72 becomes "L" in the standby state, and if VPP is a high voltage. In the meantime, the control signal C which becomes "H" is applied, and the resistance element R7
A P-channel type MOS transistor P71 is connected between the connection point of 1 and R72 and VMP, and N is connected between VMP and GND.
The channel type MOS transistor N71 is connected to P71
Consider a circuit configured by applying a signal obtained by inverting the control signal C by the inverter I71 to the gates of N1 and N71.

Next, the operation will be described with reference to FIG. In the standby state where VPP becomes equal to VDD, the control signal C becomes "L", so that the transistor N72 is turned off and the potential at the connection point of the resistance elements R71 and R72 is VPP = V.
Since it becomes DD, VMN also becomes VDD, and the inverted control signal C becomes "H", so that the transistor P71 turns off, the transistor N71 turns on, and VMP becomes GND.

On the other hand, when VPP is a high voltage, the control signal C becomes "H", so that the transistor N72 is turned on and R7 is turned on.
If 1 = R72, the potential at the connection point between the resistance elements R71 and R72 becomes VPP / 2, so VMN also becomes VPP / 2, and the inverted control signal becomes "L", so that the transistor P
71 is turned on, the transistor N71 is turned off, and VMP is also V
It becomes PP / 2.

FIG. 17A is a circuit diagram showing a tenth embodiment of the present invention. In the third embodiment of the present invention described with reference to FIGS. 3A and 3B, VMN is applied to the gate. A control signal S11 applied to the applied N-channel MOS transistor N15 and to the gate is "H" in the standby state where VPP is equal to VDD, and "L" when VPP is a high voltage. Channel type MOS transistor N
One end of a series circuit composed of 16 is connected to load elements L11 and P
It is connected to the connection point of the channel type MOS transistor P12, and the inverted input signal IN1 inverted by the inverter I11 is applied to the other end.

In this embodiment, the control signal S11 is "L" and the transistor N1 is in the high voltage VPP period.
Since 6 is off, it is the same as the third embodiment of the present invention described above, so the description thereof is omitted here, and the operation in the standby state where VPP is equal to VDD is also referred to FIG. 17B. While explaining.

Since the inverted input signal IN1 is "L" and VMN = VDD and S11 = VDD while the input signal IN1 is "H", the N-channel type MOS transistor N1.
5 and N16 turn on, load element L11 and P-channel type M
Since the connection point A of the OS transistor P12 is pulled down to GND, a P-channel type MOS with VDD> | VTP |
The transistor P13 is turned on, and "H" is stably output from OUT13.

During the period when the input signal IN1 is "L", the inverted input signal IN1 becomes "H" and the N-channel MOS
The connection point A is (VDD) via the transistors N15 and N16.
-VTN), but since it is further pulled up to VDD through the load element, it is shown in FIGS. 3 (a) and 3 (b).
The same operation as that of the third embodiment of the present invention described in
The description here is omitted.

As described above, according to the tenth embodiment of the present invention shown in FIGS. 17A and 17B, N
By adding channel type MOS transistors N15 and N16, VDD> | VTP | which is lower than VDD> 2 | VTP | in the ninth embodiment of the present invention shown in FIGS. 16 (a) and 16 (b). Therefore, when the input signal IN1 is "H", "H" can be stably output from OUT13.

In the first embodiment of the present invention shown in FIG. 1, the second embodiment of the present invention shown in FIG. 2 and the fourth embodiment of the present invention shown in FIG. , In an N-channel MOS transistor with VMN applied to its gate and in a standby state where, for example, VPP becomes equal to VDD, it becomes "H" and V
When PP is a high voltage, one end of a series circuit including an N-channel type MOS transistor to which a control signal of "L" is applied is connected to a connection point between the load element L11 and the P-channel type MOS transistor P12. However, even if the inverted input signal is applied to the other end,
It is obvious that the same effects as those of the embodiment are obtained, and the description thereof is omitted here.

18 (a) and 18 (b) show the eleventh aspect of the present invention.
5A is a circuit diagram and timing chart showing an embodiment of FIG.
And in the fifth embodiment of the invention described in (b),
For example, if VPP is in a standby state where it is equal to VDD, then P
The VMP applied to the gates of the channel type MOS transistors P22 and P24 is set to the GND level, and the VMN applied to the gates of the N channel type MOS transistors N22 and N24 is set to the VDD level.

In this embodiment, for example, in the standby state where VPP becomes equal to VDD, the input signal IN2 is "L".
In the case of N, the N-channel type MOS transistor N21 is turned off and the inverted input signal IN2 becomes "H", VDD> V
If it is TN, the N-channel MOS transistors N23 and N24 are turned on, “L” is stably output from OUT21, and the potential at the connection point G is pulled down via the P-channel MOS transistor P24, and | VTP | And VDD> 2 | VTP |, the P-channel type MOS transistors P21 and P22 are turned on, and the inverted OUT21
"H" is stably output from the output terminal, the connection point E becomes VDD, and the P-channel MOS transistor P23 is turned off.

On the other hand, when the input signal IN2 is "H", V
If DD> VTN, N-channel MOS transistor N
21 and N22 are turned on and "L" is stably output from the inverted OUT21, and the potential at the connection point E is pulled down via the P-channel MOS transistor P22 to become | VTP |, VDD> 2 | VTP | If so, the P-channel MOS transistors P23 and P24 are turned on, and O
"H" is stably output from UT21, and the connection point G is V
It becomes DD and the P-channel MOS transistor P21 is turned off.

In the fifth embodiment of the present invention shown in FIGS. 5A and 5B, since VMP = VMN = VPP / 2 is set, when VPP = VDD, the connection point E Or G
Since the pull-down potential of VMP + | VTP |
− | VTP |)> (VMP + | VTP |) That is, VDD> 4 | V
In the case of TP |, the P-channel type MOS transistor P21 or P23 is turned on, and OUT21 or inverted OU
Although "H" is stably output from T21, by setting VMP to GND level and VMN to VDD level during the period when VPP is equal to VDD as in the above-described embodiment,
If VDD> 2 | VTP |, OUT21 or inverted O
"H" is stably output from the UT 21, and a double voltage reduction can be realized.

In the sixth embodiment of the present invention shown in FIG. 6 and the first embodiment of the present invention shown in FIG. 1, for example, VMP is set to GN in the standby state where VPP is equal to VDD.
By setting DMN level and VMN level to VDD level,
It is obvious that a stable output can be obtained with VDD> 2 | VTP |, as in the present embodiment, and a description thereof will be omitted here.

FIGS. 19A and 19B show the twelfth embodiment of the present invention.
5A is a circuit diagram and timing chart showing an embodiment of FIG.
In the circuit diagram showing the fifth embodiment of the present invention shown in
An N-channel type MOS transistor N27 having VMN applied to its gate, and a control signal S21 which becomes "H" in a standby state where VPP is equal to VDD in the gate, and "L" when VPP is a high voltage. One end of a series circuit composed of the applied N-channel type MOS transistor N28 is connected to a connection point E of the N-channel type MOS transistors P21 and P22, and the inverted input signal IN2 is applied to the other end by an inverter I21 and its gate is connected. N with VMN applied
One end of a series circuit including a channel type MOS transistor N29 and an N channel type MOS transistor N30 having a gate applied with a control signal S21 has a P channel type M transistor.
It is connected to the connection point G of the OS transistors P23 and P24, and the input signal IN2 is applied to the other end.

In this embodiment, the control signal S21 is "L" and the P channel type MOS is in the high voltage VPP period.
Since the transistors N28 and N30 are turned off, they are similar to the fifth embodiment of the present invention described above. Therefore, the description thereof is omitted here, and the operation in the standby state where VPP is equal to VDD is shown in FIG. ) Will also be explained.

While the input signal IN2 is "L", the N-channel MOS transistor N21 is turned off and the inverted input signals IN2 and VMN are VDD, so VDD>
N-channel MOS transistors N23 and N14 at VTN
Turns on and OUT21 outputs “L” stably, V
MP is at GND level, so P-channel MOS
The connection point G is pulled down to | VTP | via the transistor P24, and the N-channel MOS transistor N
Pulled down to GND via 29 and N30.

Therefore, if VDD> VTP, the P-channel type MOS transistors P21 and P22 are turned on and the inverted OU is reached.
"H" is stably output from T21.

Similarly, if VDD> VTN and VDD> | VTP | while the input signal IN2 is "H", then OUT2
A stable “L” is output from 1 and a stable “H” is output from the inverted output OUT21.

As described above, in the present embodiment, for example, in the standby state where VPP becomes equal to VDD, VDD>
Stable output can be obtained even with a very low power supply voltage that satisfies VTN and VDD> | VTP |.

[0144]

As described above, according to the present invention,
Without using high breakdown voltage MOS transistor
Further, since the electric field applied to the gate oxide film of the MOS transistor is suppressed, the gate oxide film will not be deteriorated and the gate oxide film will be destroyed, so that the circuit cannot operate. The shift circuit can be realized.

[Brief description of drawings]

1A and 1B are a circuit diagram showing a first embodiment of the present invention and a diagram showing its operation.

2A and 2B are a circuit diagram showing a second embodiment of the present invention and a truth table showing its operation.

3A and 3B are a circuit diagram showing a third embodiment of the present invention and a diagram showing its operation.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

5A and 5B are a circuit diagram showing a fifth embodiment of the present invention and a diagram showing the operation thereof.

6A and 6B are a circuit diagram showing a sixth embodiment of the present invention and a diagram showing its operation.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention.

8A and 8B are a circuit diagram showing a first conventional example and a diagram showing its operation.

9A and 9B are a circuit diagram showing a second conventional example and a diagram showing the operation thereof.

10A and 10B are a circuit diagram showing a third conventional example and a diagram showing the operation thereof.

11A and 11B are a circuit diagram showing a fourth conventional example and a diagram showing its operation.

FIG. 12 is a circuit diagram showing a fifth conventional example.

FIG. 13 is a diagram showing an embodiment of a circuit for generating a voltage near VPP / 2.

14A and 14B are a system diagram showing a nonvolatile memory and a circuit diagram showing a memory cell.

15 (a) and 15 (b) are a circuit diagram showing an eighth embodiment of the present invention and a diagram showing its operation.

16 (a) and 16 (b) are a circuit diagram showing a ninth embodiment of the present invention and a diagram showing its operation.

17 (a) and 17 (b) are a circuit diagram showing a tenth embodiment of the present invention and a diagram showing its operation.

18 (a) and 18 (b) are a circuit diagram showing an eleventh embodiment of the present invention and a diagram showing its operation.

19 (a) and (b) are a circuit diagram showing a twelfth embodiment of the present invention and a diagram showing its operation.

20A and 20B are a circuit diagram showing a second example of a circuit for generating a voltage near VPP / 2 and a diagram showing its operation.

[Explanation of symbols]

VPP High-voltage power supply terminal GND Ground terminal IN1, IN1A, IN1B, IN1C, IN2, IN
2A, IN2B, IN2C input signals OUT11, OUT12, OUT13, OUT14, O
UT21, OUT22, OUT23 output signal L11 load element R11 resistance element P11, P12, P13, P14, P21 to P28 P
Channel type MOS transistors N11, N12, N11A, N11B, N11C, N1
3 to N16, N21 to N29, N21A, N21B, N
21C, N23A, N23B, N23C N-channel MOS transistor I11, I21 Inverter S11, S21, C Control signal

Claims (15)

[Claims] 1. A voltage level shift circuit for generating a logic output having an amplitude VPP larger than the amplitude level in response to a logic input having a predetermined amplitude level, the load level element comprising: a load element;
A first-conductivity-type first MOS transistor in which a voltage of approximately VPP / 2 level is applied to the gate, a second-conductivity-type second MOS transistor in which a voltage of approximately VPP / 2 level is applied to the gate, and a gate The third MOS transistor of the opposite conductivity type to which the logic input is applied is serially connected in this order between the power supply voltage VPP and the ground, and the first and second MO transistors are connected in series.
A voltage level shift circuit, wherein the logic output is derived from a connection point of S transistors. 2. A gate has the load element and the first MO.
The one conductivity type fourth MOS transistor connected to a connection point with the S transistor, and the gate having the substantially VPP / 2.
The fifth MOS of one conductivity type to which a level voltage is applied
A transistor, and a reverse conduction type sixth MOS transistor having a gate to which a voltage of approximately VPP / 2 level is applied;
A seventh MOS transistor of the reverse conductivity type, to the gate of which an inverted signal of the logic input is applied, is connected in series in this order between the power supply voltage VPP and the ground, and a connection point of the first and second MOS transistors. 2. The voltage level shift circuit according to claim 1, wherein the logic output is derived from a connection point of the fifth and sixth MOS transistors instead of deriving the logic output from. 3. The voltage level shift circuit according to claim 2, wherein the inverted signal of the logic input is a signal having the same amplitude as the logic input signal. 4. In place of the third MOS transistor, there is provided a logic circuit composed of a plurality of MOS transistors of the opposite conductivity type, to each gate of which a logic input of the predetermined amplitude is applied and which are connected in series or in parallel. The voltage level shift circuit according to claim 1 or 2, wherein. 5. A voltage level shift circuit for generating a logic output having an amplitude VPP larger than the amplitude level in response to a logic input having a predetermined amplitude level, the first conductivity type first MOS transistor, Almost V at the gate
The second MOS transistor of one conductivity type to which a voltage of PP / 2 level is applied, the third MOS transistor of the opposite conductivity type to which a voltage of approximately VPP / 2 level is applied to the gate, and the logic of the logic to the gate. The fourth MOS transistor of the opposite conductivity type to which an input is applied is connected in series in this order between the power supply voltage VPP and the ground, and the fifth MOS transistor of the one conductivity type and the gate of approximately VPP / 2 level. The sixth MOS transistor of one conductivity type to which a voltage is applied, the seventh MOS transistor of reverse conductivity type to which a voltage of approximately VPP / 2 level is applied to the gate, and the inverted signal of the logic input to the gate. Is connected in series between the power supply voltage VPP and ground in this order, and the gate of the first MOS transistor is connected to the fifth and sixth MOS transistors. Is connected to a connection point of the MOS transistor, a gate of said fifth MOS transistor is connected to a connection point of said first and second MOS transistors, said second
And the connection point of the third MOS transistor and the sixth
And a pair of complementary logic outputs from the connection points of the seventh and seventh MOS transistors, respectively. 6. A logic circuit comprising a plurality of reverse-conductivity-type MOS transistors connected in series or in parallel with each other, instead of the fourth MOS transistor, to which a logic input having the predetermined amplitude is applied to each gate. The voltage level shift circuit according to claim 5, further comprising: 7. A second MOS transistor, instead of the eighth MOS transistor, comprising: a plurality of MOS transistors of the reverse conductivity type, to which respective inverted signals of the logic input are applied to respective gates and which are connected in series or in parallel with each other. 7. The voltage level shift circuit according to claim 5, further comprising the logic circuit of. 8. A ninth M of the one conductivity type having a gate connected to a connection point of the fifth and sixth MOS transistors.
An OS transistor, the tenth MOS transistor of one conductivity type having a voltage of approximately VPP / 2 level applied to its gate, and the eleventh MOS transistor of the opposite conductivity type having a voltage of approximately VPP / 2 level applied to its gate. The MOS transistor and the twelfth MOS transistor of the reverse conductivity type in which the inverted signal of the logic input is applied to the gate are the power supply voltage V in this order.
7. The logic output is connected in series between PP and ground, and the logic output is derived from a connection point of the tenth and eleventh transistors instead of the pair of complementary logic outputs.
The described voltage level shift circuit. 9. A gate is connected to a connection point of the first and second MOS transistors, and a source is the power supply voltage VPP.
The thirteenth MOS transistor of one conductivity type connected to the first conductivity type, and the one conductivity type in which a gate is connected to a connection point of the sixth and seventh MOS transistors and a voltage of approximately VPP / 2 level is applied to the source. 14th MOS transistor, and instead of the pair of complementary logic outputs having an amplitude VPP larger than the predetermined amplitude level, the 13th M
From the connection point connecting the drain of the OS transistor and the drain of the fourteenth MOS transistor, VPP is approximately V
8. The voltage level shift circuit according to claim 5, wherein a logic output oscillating between PP / 2 is derived. 10. The potential applied to the gate of the first MOS transistor is set to the low level of the predetermined amplitude when the VPP is at a potential equal to or near the high level of the predetermined amplitude level. 5. The voltage level shift circuit according to claim 1, wherein the voltage level shift circuit is set and the potential applied to the gate of the second MOS transistor is set to the high level of the predetermined amplitude level. 11. One end of a series circuit composed of the eighth MOS transistor having a gate to which the voltage of substantially VPP / 2 level is applied and the ninth MOS transistor having a gate to which a control signal is applied, Load element and the first M
11. The voltage level shift circuit according to claim 10, wherein the voltage level shift circuit is connected to a connection point with an OS transistor, and an inverted signal of the logic input is applied to the other end. 12. When the VPP is at a potential equal to or near a high level of a predetermined amplitude level,
12. The voltage level shift circuit according to claim 11, wherein the potential applied to the gate of the eighth MOS transistor is set to the high level of the predetermined amplitude level. 13. When the VPP is at a potential equal to or near a high level of a predetermined amplitude level,
The potential applied to the gates of the second and sixth MOS transistors is set to the low level of the predetermined amplitude, and the potential applied to the gates of the third and seventh MOS transistors is set to the predetermined amplitude level. The voltage level shift circuit according to claim 5, wherein the voltage level shift circuit is set to a high level. 14. A fifteenth MOS transistor of one conductivity type having a gate to which the voltage of substantially VPP / 2 level is applied, and a first MOS transistor of one conductivity type having a control signal applied to a gate.
One end of the series circuit composed of 6 MOS transistors
The first MOS transistor is connected to a connection point of the second MOS transistor, the inverted signal of the logic input is applied to the other end, and the gate is applied with the voltage of substantially VPP / 2 level. One end of a series circuit composed of a seventeenth conductivity type MOS transistor and the eighteenth MOS transistor of one conductivity type having a control signal applied to its gate is connected to the fifth MOS transistor and the sixth MOS transistor.
The voltage level shift circuit according to any one of claims 5 to 9 and 13, wherein the voltage level shift circuit is connected to a connection point of a transistor and the logic input is applied to the other end. 15. When the VPP is at a potential equal to or near the high level of the predetermined amplitude level, the potential applied to the gates of the fifteenth and seventeenth MOS transistors is set to the predetermined amplitude level. 15. The voltage level shift circuit according to claim 14, wherein the voltage level shift circuit is set to a high level.