JPS5824964B2 - noise reduction warmer - Google Patents

Description

Detailed Description of the Invention The present invention compresses an input signal logarithmically according to its input level (dB) and records it on a tape, reproduces this signal, and compresses the playback level (dB) logarithmically. By expanding the recording signal to a wide range, it is possible to widen the range of the recorded signal, and in particular, with regard to the noise reduction circuit used when measuring the reduction of noise accompanying recording and playback, it is particularly useful to utilize simple switching means. This is so that the noise reduction function cannot be performed.

To explain the noise reduction circuit according to the present invention, the embodiment shown in FIG. 1 configures an encoder circuit and a decoder circuit by switching switches S1 and S2, thereby configuring a noise reduction circuit as a whole. This is the case.

1 is a signal input terminal, and the input signal from this is supplied to the logarithmic compression circuit 3 through the amplifier 2 (its input terminal is designated as 2a), and its output (the output terminal is designated as D2) is supplied to the switch S2. It is supplied to the encoder contact e2 and also to the decoder contact d1 of the switch S1.

Also, the output of the amplifier 2 is sent to the encoder contact e1 of the switch S1.
and the decoder contact d2 of switch S2
is supplied to

The signals obtained at the contacts d1 and el are supplied to the negative feedback terminal 2c of the amplifier 2 (the terminal whose polarity is opposite to that of the input terminal 1) through the switching contact Sa of the switch S1.

The signals obtained at contacts d2 and e2 are supplied to output terminal 4 through switching contact sb of switch S2.

When the base of the first stage transistor of the amplifier 2 is set as the input terminal 2a, its emitter can be set as the terminal 2c.

7 is a resistor. The logarithmic compression circuit 3 has a variable impedance means 5 and an amplifier 6 that performs a linear amplification operation within a certain level range, and the output of the variable impedance means 5 is passed through the amplifier 6 to the variable impedance means 5. The signal is supplied to the control terminal G of.

Further, a control terminal G of the variable impedance means 5 is grounded through a switch 8 and a DC power supply 9.

The polarity and voltage of the power supply 9 in this case are chosen depending on the configuration of the means 5, or the control terminal G may be grounded through the switch 8.

The variable impedance means 5 that can be used in the present invention will be explained with reference to FIG.

FIG. 2 is a basic configuration diagram of a transistor that can be used in this means 5, and FIG. 3 is a sectional view taken along the line 1-1 in FIG.
In this example, the basic idea is introduced into a MOS type FET.

For convenience of explanation, an explanation will be added starting from FIG. 3. Since this sectional view shows that the structure of a normal MOS-FET is almost the same, detailed explanation will be omitted.

12 is an N-type (or P-type) semiconductor substrate.

P-type (or N-type) impurities are diffused from the upper surface 12a of the base 12 at predetermined positions and at predetermined distances, respectively, to form a source diffusion region 13 and a drain diffusion region 14.
(in the following description, they will be referred to as a source region and a drain region, respectively) are formed.

However, in the formation of regions by diffusion in this example, the diffusion area is different for each region as shown in the figure, and the drain region 14 is made smaller, but this is because the electrode extraction position is outside the channel, as shown in FIG. This is because the selection was made in accordance with the following.

Further, the impurity concentration of the drain region 14 facing the channel is made to be equal to or lower than that of the drain region of the lead-out portion of the electrodes D1 p D2.

Note that 15 is an insulating layer such as SiO2, and 16 is an insulating layer such as SiO2 that is selected to have a predetermined thickness and becomes a gate oxide film, as is well known.On the upper surface of this insulating layer 16 is a gate electrode G.
A conductive layer 17 such as A1 is deposited, and a conductive layer 18 is similarly deposited over the entire upper surface of the source region 13 to form a source electrode S.

Then, the electrodes D1. D2 is taken out.

In this case, in order to make it easier to take out the electrodes D1 and D2,
In this example, they are taken out from positions outside the channel formed between the source and drain.

In this figure, the left drain electrode is connected to the first drain electrode D.
1. Let the one on the right side be the second drain electrode D2.

In order to facilitate understanding of FIG. 2, the source and drain regions 13.14 are shown as dotted lines, the conductive layers 17.18 are shown as solid lines, and the window holes i9a and 19b formed to take out the electrode layer 1M D2 are shown as dotted lines. are indicated by dashed lines.

The symbols of the FET configured as shown in FIG. 2 are determined as shown in FIG.

When this FET is used as a variable impedance element, the source electrode S is grounded.

Note that 10 is a back gate terminal.

When connected in this way, by varying the control voltage VQ of the control electrode G, the gain g of the output signal changes linearly, the amount of attenuation is increased, and the distortion rate is improved.

Next, I will explain the similarities. Therefore, first consider an equivalent circuit of an FET as shown in FIG.

The lateral resistance groups 2N21a, 21b, . . . ) are resistances multiplied by 8 in the y direction of the channel width of the drain region 14, and constitute a kind of diffused resistance.

And the vertical resistance group 22 (22a, 22b...
・) is the channel conductance of each part.

The resistance value of the resistor group 21 is dR1, the conductance value of the resistor group 22 is dG, the current flowing through the resistor 21c is ID(y), the voltage across it is VD(y), and the resistor 22b is
If the current flowing through is dI D (y), these equations are as follows.

I D (y)-d VD (y)
=”(1) dID (y) = VD (y) ・d
G...''' (2) Here, .

However, R is the channel resistance, and β is the proportionality constant of the FET.

Next, dividing equation (1) by dy, substituting equation (3) into equation (5) gives the following equation, and further differentiating equation (6) with respect to y yields.

On the other hand, dividing equation (2) by dy yields, so this (8
) by substituting the equation into equation (7) and transposing the term, the following differential equation is obtained.

Therefore, the general solution to the differential equation expressed by equation (9) can be found as shown in the following equation.

Now, if we consider the mapping with VD(0) = V, , VDtW) = V2, if we insert the boundary condition VD(2W) = V1 and eliminate the constants C1 and C2, we get (10)
The formula is as follows.

From this equation (11), it can be seen that the voltage gain g (g-v2/v) is a curve 20 that represents the reciprocal of cos h, that is, the attenuation (bB).

As a result, the cos h curve 2 that changes with the control voltage VC
3 has (1) relatively good linearity, so the attenuation characteristics are good, (2) the amount of attenuation is extremely large, about -30 dB when vG is 15V, and (3) VG is close to vth. Since there is no sudden change in attenuation even at a relatively low control voltage, the distortion factor is also improved.

It is shown that.

As explained above, in addition to the usual MO8 type configuration, this FET has two drain electrodes, that is, the first and second drain electrodes D1 and D2 are taken out from both ends of the drain region 14 in the channel width y direction. It is composed of

Therefore, the signal gain g is cos
Since the characteristic is proportional to the reciprocal of h, it is possible to provide a damping characteristic with good linearity, and the amount of attenuation is comparable to that of the conventional M
It has the great feature of increasing the number of transistors compared to OS-FETs and improving the distortion rate.

Of course, since the structure of PET is simple, it has the practical benefit of being able to provide it at a low price.

The first drain D1 of such FET 5 is connected to the output terminal 2b of the amplifier 2, and the second drain D2 is connected to the contact e2 of the above-mentioned switch S2 and the contact d1 of the switch S.
and the control electrode G is connected to the input side of the amplifier 6.
It is connected to the output side of the

3 is in a circuit like this, switch 8 is off, and S
The operation when l and S2 are in the switching states shown by solid lines, that is, when they are used as encoder circuits, will be described.

The signal supplied to the terminal 1 is amplified by the amplifier 2 and obtained at the terminal 2b, and this signal is further transmitted to the logarithmic characteristic compression circuit 3.
Therefore, the output terminal 4 receives a signal in which the input signal is compressed according to the characteristic curve 23 shown in FIG. will be obtained.

That is, the input signal is compressed logarithmically with respect to the signal level (dB).

When the output terminal 4 is connected to the input side of the magnetic recording/reproducing apparatus, the compressed signal as described above is recorded on the tape.

In this state, a negative feedback signal is supplied to the input side of the amplifier 2 through the resistor 7.

Next, with switch 8 in the off state as described above, switch S
The operation when 1 and S2 are in the switching state shown by dotted lines, that is, when they are used as decoder circuits, will be explained.

In this case, the W end of the magnetic recording/reproducing apparatus as described above is connected to the input terminal 1, and the output terminal 4 is connected to a speaker via an amplifier as required.

In the switching states of the switches S1 and S2 shown by dotted lines,
The output from the logarithmic characteristic compression circuit 3 will be supplied to the negative feedback terminal 2c of the amplifier 2, and the output of the amplifier 2 will be obtained at the output terminal 4.

In this state, the logarithmic compression circuit 3 is inserted into the amplifier 2 as a negative feedback system. Therefore, when the signal level supplied to the input terminal 1 is low, the level of the signal passing through this circuit 3 is Since it is relatively large with respect to the input signal, a large negative feedback is generated to the amplifier 2, so that the output signal is suppressed to a low level.

Next, when the level of the input signal is high, the level of the signal passing through this circuit 3 is relatively small compared to the input signal, so that the amount of negative feedback to the amplifier 2 is equal to the magnitude of the input signal mentioned above. It becomes relatively small, and therefore the amplifier of the amplifier 2 becomes large.

That is, since the amount of feedback passing through this circuit 3 is logarithmic, the output of the amplifier 2 is expanded logarithmically, and this signal is obtained at the output terminal 4.

Next, when the switch 8 is turned on with the switches S1 and S2 in the state shown by the solid lines, that is, in the encoder state, a constant DC voltage is applied to the control electrode G of the variable impedance means 5.

Or the control electrode G is grounded.

In this case, the gain g of the variable impedance means 5 is fixed to a constant value, so the above-mentioned encoder operation disappears, that is, the amplifier becomes an amplifier with a constant gain G.

In addition, the input terminal and output terminal of the variable impedance means 5 (
In this example, a similar state can be obtained even if the first and second drain terminals D1 and D2) are short-circuited, but if there is a positive gain between these terminals D1 and D2, If it is a means, it will cause a loss, which is not preferable.

However, according to the configuration according to the present invention described above, there is no loss because the gain g of the variable impedance means 5 is only kept constant.

It should be noted that each of the above-mentioned switches S1. Although S2 and S8 are both mechanically displayed, they can both be configured with electronic switching.

In the example of FIG. 1, an encoder circuit and a decoder circuit are configured by switching switches S1 and S2, but it is also possible to configure only an encoder circuit as shown in FIG. 7.

Therefore, the same reference numerals are given to the parts of this circuit corresponding to those in FIG. 1, and the explanation thereof will be omitted.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an example of a noise reduction circuit according to the present invention, FIG. 2 is a partial plan view showing an example of a field effect transistor that can be used in the circuit of the present invention, and FIG. 3 is an I
-1 line sectional view, FIG. 4 is its symbol diagram, FIG. 5 is its circuit, FIG. 6 is its characteristic curve diagram, and FIG. 7 is a connection diagram showing another embodiment. 1 is a signal input terminal, 2 is an amplifier, 3 is a logarithmic compression circuit, 5
numeral 4 denotes a variable impedance means constituting this circuit, 4 an output terminal, and 8 a switch.

Claims (1)

[Claims] 1. A logarithmic compression circuit having a variable impedance means, the output of which is fed back to a control terminal as a control signal so that the gain of the signal passing through the variable impedance means is varied in a logarithmic curve with respect to changes in the control signal. 1. A noise reduction circuit comprising: an on/off switch for noise reduction operation connected between the control terminal and a constant DC power supply including a DC voltage of zero.