JPS582454B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor container, and is particularly suitable for application to semiconductor devices in ultra-high frequency bands.

As is generally known, the structure of a semiconductor device having a semiconductor container that houses a semiconductor element used in an ultra-high frequency band has a significant influence on the electrical characteristics of the semiconductor device. The configuration of the parts involved in electrically connecting the electrodes of the semiconductor container is extremely important.

Examples include parasitic reactance components such as stray capacitance between different electrodes of a semiconductor container and inductance of a bonding wire that electrically connects the semiconductor element and the semiconductor container.

In other words, when designing a semiconductor container on which a semiconductor element is placed and used in an ultra-high frequency band, particular attention should be paid to the selection and geometrical arrangement of the materials constituting the semiconductor container.

Specifically, it has a low dielectric constant as a constituent material for semiconductor containers.
Use materials with low dielectric loss, use materials with as low resistance as possible for thin metal wires and metal tapes that electrically connect semiconductor elements and semiconductor containers, and keep their lengths short. The goal is to shield different types of electrodes in some way.

Currently, the most recommended container configuration is one in which air with a low dielectric constant is interposed between different types of electrodes other than the grounding part, or the distance between the electrodes is kept as far as possible, and the different types of electrodes are shielded with metal.

However, as mentioned above, the distance between the electrodes of the semiconductor element and the electrodes of the container must be kept as short as possible, so the structure of the container becomes complex in order to reduce the values of electrostatic stray capacitance and inductance, and therefore extremely advanced manufacturing technology is required. required.

For example, as shown in FIGS. 1 and 2, there is a conventional method in which air is interposed between different types of electrodes to reduce the electrostatic stray capacitance between them.

G is a gap interposed between the different types of electrodes.

This gap G is formed between the surrounding surface of the convex portion 1a of the metal stud 1 and the inner circumferential surface of the insulating envelope 9 surrounding the convex portion 1a.
The capacitance values between the electrode layers 5, 6, and 7.8 are reduced.

That is, in this example, the semiconductor element 2 is a so-called bipolar transistor whose collector electrode is led out from the back surface of the chip, and the metallized layer 4 on the mounting surface of the semiconductor element 2 is electrically connected to the collector.

Therefore, it is attached to the heat dissipation stud 1 via the insulating layer 3.

The collector is connected to one of the metallized layers formed on the upper surface of the insulating envelope 9, for example 6, by a bonding wire 10a.
Other electrodes of the semiconductor element 2, such as the base, are connected to the Hong Kong wire 1.
The emitter is connected to the metallized layers 5 and 7 through a bonding line 10c, and the emitter is connected to the metallized layer 8 through a bonding line 10c.

Therefore, the metallized layers 5 and 7 formed on the insulating envelope 9 become base electrodes, the metallized layer 6 becomes a collector electrode, and the metallized layer 8 becomes an emitter electrode.

The insulating substrate 3 and the insulating envelope 9 are, for example, soldered to the stud 1 via metallized layers 4' and 11, respectively.

During this brazing work, the insulating substrate 3 and the insulating envelope 9 tend to move, for example, the insulating envelope 9 moves to the left and is fixed with its inner surface in contact with the outside of the protrusion 1a of the stud 1. If this happens, there will be no gap G between the emitter electrode 8 and the metallized layer 4 connected to the collector, and the electrostatic stray capacitance between this gap will increase.

In other words, if the permittivity of air is ε-1 and the permittivity of the material of the insulating envelope 9 is ε=4 to 5, then since the gap G is eliminated, the gap between the opposing electrodes 8 and 4 in this example is The capacitance is increased by 4 to 5 times.

Further, even if only the insulating substrate 3 moves and collides with the inner circumferential surface of the insulating envelope 9, an increase in capacitance is observed in the same way.

However, if the brazing work proceeds with the peripheral edge of the insulating substrate 3 abutting the inner surface of the insulating envelope 9, the melted brazing material will creep up between the insulating substrate 3 and the insulating envelope 9 due to capillary action. Accidents such as electrically shorting the mekrise layer 4 formed on the top surface to the metal stud 1 are also likely to occur.

For this purpose, as shown in FIGS. 3 and 4, a recess 12 is formed in the stud 1, an insulating substrate 3 is mounted on the bottom of the recess 12, the insulating substrate 3 is positioned, and the insulating substrate 3 and the insulating envelope 9 are connected to each other. A method has been considered in which a part of the metal stud 1 is interposed between the two and the dielectric constant between the two is kept low.

However, with the structure shown in Fig. 3, it is necessary to have extremely advanced mechanical manufacturing techniques to provide stepwise recesses over extremely short distances. (Materials with a large coefficient of expansion have a large coefficient of expansion).
As a result, a significant strain is applied to the insulating substrate 3 mounted on the stud 1, causing a crack.

Furthermore, if a convex portion 13a is provided on the insulating substrate 3 as shown in FIG.
When performing this process, since the protrusion 13a becomes an obstruction, it becomes impossible to use mass production techniques such as screen printing, and manual techniques have to be resorted to, which is not economical.

For example, the convex portion 13a of the insulating substrate 3 and the concave portion 13b of the stud 1
If it is reversed, the problems explained in FIG. 3 will occur, and no matter where the uneven portion is provided, impedance fluctuations will not be avoided and the characteristics of the semiconductor device will be impaired.

In addition, the structure as shown in FIG.
There is a risk of electrical short-circuiting between the metallized layer 4 and the metallized layer 4, and even if they are electrically insulated, the distance between them becomes extremely short, increasing stray capacitance.

Furthermore, the structure as shown in FIG. 4 has the risk of significantly impairing the heat sink effect since holes are likely to be formed in the uneven portions 13a and 13b during brazing.

The purpose of the present invention is to eliminate these various drawbacks, and to obtain an economical semiconductor container that can be mass-produced.

In this invention, as shown in FIGS. 1 and 2, conductive studs are disposed within the area surrounded by the insulator outer envelope as shown in FIGS. 3 and 4, and In a semiconductor device having a semiconductor container in which an insulating substrate 3 is mounted in a recess surrounded by a conductor of a stud and a semiconductor element 2 is held on this base, the area of the semiconductor element holding surface of the base is The cross-sectional area of the lower scud is selected to be smaller than that of the bottom surface of the recess, so that the facing gap with the outer circumference of the recess of the scud surrounding the base becomes larger toward the semiconductor element holding surface.

FIG. 5 shows an example of this, and parts corresponding to those in FIGS. 1 to 4 are given the same reference numerals and redundant explanation will be omitted. A case where substrate 3 is used is shown.

That is, the insulating substrate 3 has a cross-sectional area on the bottom side of the concave portion of the lower scud that is larger than the area of the semiconductor element mounting surface on which the metallized layer 4 is attached, and in this example, it is formed in a stepped shape as shown in FIG. , the area of the bottom surface is larger than that of the semiconductor element mounting surface, and the larger area of the lower part positions the metal stud 1 in the recess 12, and the upper part is the side surface of the insulating substrate 3 and the inner surface of the metal stud 1 surrounding it. The gap between the two is made larger.

With this structure, even if the position of the insulating substrate 3 moves a little during brazing and comes into contact with the inner surface of the metal stud 1, the stepped portion formed on the insulating substrate 3 allows the metallized layer 4 to be directly attached to the stud 1. Since the inner surface is not touched or approached, the capacitance between the mekrise layer 4 and the stud can be minimized, and the position can be controlled by the lower part of the insulating substrate 3.

Moreover, since a gap is formed around the mekrise layer 4 by the stepped portion of the insulating substrate 3, it is possible to prevent the brazing material from creeping up, and there is no risk of short-circuiting of the strip line.

The figure shows a case where a cover 14 is provided to airtightly seal the mounting portion of the semiconductor element 2.
The lead wires 15a and 15b made of, for example, Covar are attached to the metallized layer formed above, and the semiconductor element 2
For example, the collector is connected to the stud 1 by a wire, and the collector electrode is led out through the stud 1.

Furthermore, as another embodiment of the base, for example, as shown in FIG. The width of the gap created on the inner peripheral surface with the stud 1 is made to gradually increase as it goes upward, and the position is regulated at the bottom of the lower part, and the brazing material is prevented from creeping up in the large part of the upper gap. At the same time, the larger area of the lower part prevents the metallized layer 4 and the stud 1 from coming close to each other, thereby preventing the electrostatic capacitance between them from increasing. It is also possible to configure the impedance of the line to be maintained at a predetermined value.

Further, by forming the tapered surface in this way, when the insulating substrate 3 is pressure-molded, it becomes easier to come out of the mold, so that there is an advantage that the manufacturing yield of the insulating substrate 3 can be improved and the reliability can also be improved.

Alternatively, as shown in FIG. 8, the insulating substrate 3 may be formed into a barrel shape, and its position may be regulated by a protrusion at the center.

As explained above, according to the present invention, the shape of the base that holds the semiconductor element 2 is made so that the lower cross-sectional area is larger than the area of the semiconductor element mounting surface, so that positional regulation is performed in a large part of this cross-sectional area. However, since the area of the mounting surface around the semiconductor element mounting surface is small, the side edges of the semiconductor mounting surface do not come close to the surrounding studs 1 or the insulating envelope 9. The electrostatic charge between the metallized layer 4 formed on the element mounting surface and the electrode formed on the stud 1 or the upper surface of the insulating envelope 9 can be kept to a small value, making it particularly suitable for ultra-high frequency semiconductor devices. It is something.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of a conventional semiconductor container for high frequency, FIG. 2 is a sectional view thereof, FIGS. 3 and 4 are sectional views showing other examples of the conventional example, and FIG. 5 is a sectional view of the present invention. FIG. 6 is a sectional view showing an embodiment of the invention; FIG. 6 is a perspective view showing an example of the main part of the invention;
FIGS. 7 and 8 are sectional views showing other embodiments of the present invention. 1: Metal stud, 2: Semiconductor element, 3,16 two bases,
9: Insulating envelope.

Claims (1)

[Claims] 1. In a semiconductor device in which an insulating base is mounted in a recess surrounded by a conductor and a semiconductor element is mounted on the base, the area of the semiconductor element mounting surface of the insulating base is equal to the cross section below this. A semiconductor device characterized in that it is formed smaller than its area.