JPS58225730A - Synchronous oscillation type automatic frequency controller - Google Patents

Abstract

PURPOSE:To complete synchronous oscillation AFC operation at a high speed even when the number of input signals (number of hits) is small, by providing a control system which operates so that the one-round DC gain of a syncrhonous oscillation AFC device is equal to the PRF of the input signals. CONSTITUTION:A control error is generated at the output 106 of a zero-order holding part 4 by the 1st input signal and the system carries on control until the 2nd input signal 101 arrives, so the control error to the 2nd input signal 101 is reduced, so that an output 104 has a stepwise difference owing to the control error when the 2nd input signal 101 arrives. A timing signal generating circuit 15 is so set by the output 111 of a detecting and amplifying circuit 14 to extract both sides of the step of the output 104 of a zero-order holding circuit 4. A one- round gain adjusting circuit 12 outputs a control voltage which has such a direction and a level that the one-round DC gain is equal to the input signal PRF.

Description

[Detailed Description of the Invention] The present invention relates to a synchronous oscillation automatic frequency control device that can perform synchronous oscillation automatic frequency control operation at high speed even when the input is a pulse modulated wave and the number of input signals (number of hits) is very small. It was designed to be carried out in the following manner.

Conventionally, there has been a device of this type as shown in FIG.

In FIG. 1(a), (1) represents a pulse-modulated input signal (101) with a carrier frequency fin and a reference oscillation frequency f of a voltage controlled oscillator (hereinafter referred to as vCO) (8).

CW ratio output 102) and outputs (103) using the difference fs between the two frequencies as a carrier wave.
mixer, (2) is the IF ratio output 1 of the first mixer (2)
(3) is a sampling circuit that samples the output (10 predetermined portions) of the frequency discrimination circuit (3); (4) is a sampling circuit that samples the sampled error signal (LOS) to the next pulse. (6) is a zero-order hold circuit that holds the modulated wave until it arrives;
6) is an arithmetic processing unit consisting of a zero-order hold circuit (4) and a -order integration circuit (5), and (7) is a -order integration circuit (5).
The amplifier circuit (8) amplifies the output (107) of the amplifier circuit (7), the oscillation frequency of which is controlled by the output (1041) of the VCO1 (9).
2) a fixed oscillator whose frequency is equal to the null point of α4 is the output (102) of the fixed oscillator (9) and vco
The second mixer outputs the frequency of the sum of the outputs (102) of (s), OD is the fixed oscillator (9) and the second mixer 00
This is an input frequency reproducing section consisting of:

Next, the operation will be explained. The input signal of this synchronous oscillation automatic frequency control bag ml (hereinafter referred to as synchronous oscillation AFC) is a pulse modulated wave. Figure 1(b) shows the frequency discrimination characteristics of the frequency discriminator (2).
The null point of 2) is f8.

Carrier frequency fin of input signal (lOl) and VCO (8)
The reference oscillation frequency fO is mixed by the first Miki Lee (1), and a pulse modulated wave having a carrier frequency fin-fo l=fm is generated at its output (103).

At the output of the frequency discrimination circuit (2) (10), a video pulse waveform having an amplitude corresponding to the deviation of fm from f8 is obtained, which is shown in FIG. 2 (bl), (cl), and (dl).

Generally, the pulse width used in a pulse generator or the like is several microseconds or less, and it is impossible to complete AFC within this time.

Frequency discrimination circuit (2) by sampling circuit (3)
The output (loa) of the sampling circuit (3) is sampled at a predetermined position (for example, 100 ns from the pulse rise) as shown in Figure 1 (blXctXdt
), the size of which is indicated by the arrow in the frequency discrimination circuit (2
) becomes an impulse train corresponding to the amplitude of the output (103). The zero-order hold circuit (4) holds this sampling signal until the next input signal arrives. The output (log) of the zero-order hold circuit (4) is shown in FIG. 2 (bl) (c2) (dz). -order integral circuit (5)
Accordingly, the output (lOa) of the zero-order hold circuit (4) is subjected to negative-order integration. The output (107) is 1Figure 2 (b
3XcaXd3). The output of the -order integration circuit (5) (
107) is amplified to a predetermined value by the amplifier circuit (7) and controls the VCO (8). vcou is l fin-f
o The oscillation frequency fO so that l=fm approaches f8
change. On the other hand, in the input signal reproducing section 0, the fixed oscillator (9) is oscillating at fs, and the output (102) of the VCO (8) is mixed by the second mixer α1, and its output (11G) is Frequency fs+fo=fo
A continuous wave called ut is obtained. Figure 2 (b4) (c4) (
d4) shows a change in the output (tto) of the second mixer αQ approaching the input frequency fin.

In addition, Fig. 2 shows a pulse-modulated input signal (Fig. 2(a)
)) as well as the output waveforms of each part in the following eight cases. According to the sample value control theory, the DC gain of the AFC open loop transfer function is 2 2 of the period T of the input signal.
2 When the relationship is (A)T〉−(B)T−1 (C)T×K, K K AFC performs different control actions. In other words, in the case of (A),
Control is completed exponentially (Fig. 2 (bl)-(b4)
)), (B), the control is completed at the time of arrival of the input signal of the second annotation (Fig. 2 (clHc4)), (C)
In this case, the control is completed by causing damping ((dl) to (d4) in FIG. 2).

In the case of conventional synchronous oscillation AFC, the input signal period T and AF
When the open circuit DC gain of C is (A) and (C) above, AFC
A large number of signals (number of hits) are required to complete the operation, and if a large number of signals (number of hits) cannot be obtained, AF
There was a drawback that the C operation was not completed.

This invention was made to eliminate the drawbacks of the conventional synchronous oscillation AFC device as described above.
An electrically variable gain amplifier is provided in the control loop of
It has a one-round DC gain adjustment part that changes the gain of the amplification part according to the repetition frequency (hereinafter referred to as PRF) of the input signal, and operates so that the one-round DC gain of the AFC system is always equal to the PRF of the input signal. As a result, the control operation is faster than conventional ones, and AF is possible even with a small number of input signals (number of hits).
It is an object of the present invention to provide a synchronous oscillation AFC device that can complete C operation.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 8, @ is a one-turn gain adjustment circuit which is a feature of the present invention. Ql is a variable gain amplifier circuit whose gain can be changed by the output of the loop gain adjustment circuit (6);
04 is a detection amplifier circuit that detects the arrival of the input signal, and 04 is a round-trip gain adjustment unit (6) that obtains information from the detection amplifier circuit (to).
This is a timing signal generation circuit that generates a timing signal for. Further, FIG. 4 shows a specific configuration of the open circuit gain adjustment circuit. In FIG. 4, Q → is the first gate circuit that gates the zero-order hold circuit output (106) according to the first gate signal (112), and Q7) is the first gate circuit that gates the zero-order hold circuit output (106) according to the second gate signal Ua). (g) is a first polarity determination circuit that determines the polarity of the output of the first gate circuit (11) and holds the result until the next input signal arrives; is a second polarity determination circuit that determines the polarity of the output (115) of the second gate circuit 07) and holds the result until the next input signal arrives; Output (us)
and the second polarity determination circuit (the first multiplier circuit, Ql, which multiplies the output (117) of 1), the zero-order hold circuit output (1
06) An absolute value circuit that outputs the absolute value of (A), a second multiplication circuit that calculates the product of the output (US) of the first multiplication circuit (E) and the output (US) of the absolute value circuit Q]); @ is an amplifier circuit that amplifies the output (120) of the second multiplier circuit (2), (c)
- is a control direction identification circuit that identifies the control direction of the circular DC gain. In addition, the outputs (116X117) of the first polarity determination circuit (G), the second polarity determination circuit α, and the first multiplication circuit (E)
(118) is a positive, negative, or 0 [■] unit voltage.

In Fig. 8, the −circuit gain adjustment unit Q and the detection amplifier circuit α
Other than the addition of a timing signal generation circuit (to) and a variable gain amplification circuit (to), the functions of this invention are as follows.
This is the same as the conventional synchronous oscillation AFC method shown in the figure.

The operation of the synchronous oscillation AFC according to the present invention will be explained with reference to FIGS. 8 and 4, focusing on the function of the open loop gain adjustment section. 8th
In the synchronous oscillation AFC method shown in the figure, the -circuit gain adjustment section (2
)'s output (122) is fixed at a certain voltage and used as a reference, the circular DC gain KO is a constant, and when it is smaller than the PRF of the pulse-modulated input signal (101),
The output (no) of the system exponentially approaches the carrier frequency of the input compensation sphere, and conversely, when KO is larger than the PRF of the input signal q (1ol), the output (no) of the system will carry the input signal while damping it. Asymptotic to the frequency.

First, in the control system of the synchronous oscillation AFC method of the present invention,
PRF of input sphere lo l)
The signals of each part are shown in FIG. 15 and FIG. 6, respectively, when the value is smaller and when it is larger. In Figures 5 and 6, (al is the input signal (101), (b) is the output (106) of the zero-order hold circuit (4), and (c) is the detection amplifier circuit [
The outputs (m) and (d) of Xun are the first gate signal (112),
(e) is the second gate signal (113), (f) is the output (114) of the first gate circuit αQ, (gl is the output (115) of the second gate circuit αη, (b) is the polarity determination circuit (g) Output (us), (1) is the second polarity determination circuit 1.11
output (117), (j) is the output (11B) of the first multiplication circuit (1), (k) is the output (120) of the second multiplication circuit
).

A control error occurs in the output (106) of the zero-order hold section (4) due to the input signal of the first note, and the system continues to be controlled until the second input compensation ball (101) arrives. Therefore, the control error is smaller with respect to the second input signal (101), and therefore a control error (10 steps) occurs at the time of arrival of the second input signal (101).

The timing signal generation circuit (a) extracts both sides of the step of the output (104) of the zero-order hold circuit (4) from the output (m) of the detection amplifier circuit α, as shown in Figure 5 (dl (e)). is set to

As can be seen from FIG. 4, a control voltage having a direction and magnitude such that the open loop DC gain becomes equal to the input signal PRF is generated at the output of the open loop gain adjustment circuit.

- When the circular DC gain becomes equal to the input signal PRF, the responses shown in (cl) to (c) of FIG. 2 are obtained, and the AFC operation can be completed at high speed.

As described above, according to the present invention, by providing a control system that operates to make the PRF of the input signal equal to the PRF of the input signal using the loop DC gain of the synchronous oscillation AFC device, the synchronous oscillation A
The FC method performs control operations at high speed.

Therefore, even when the number of input signals (number of hits) is small, the synchronous oscillation ANC operation can be completed at high speed.

[Brief explanation of drawings]

FIG. 1 shows a conventional synchronous oscillation AFC device, (al is its block diagram, (b) is an explanatory diagram showing the characteristics of the frequency discrimination circuit, and FIG. 2 is an explanation showing the control operation of the conventional synchronous oscillation ANC device. 8 is a block diagram showing a synchronous oscillation kFC device in an embodiment of the present invention, FIG. 4 is a block diagram showing details of the open loop gain adjustment circuit in FIG. 8, and FIGS. The figure is an explanatory diagram for explaining the function of the -circuit gain adjustment section. In the figure, (1)...first mixer, (2)...frequency discrimination circuit, (3)...sampling circuit, ( 4)...Zero-order hold circuit, (5)...--order integration circuit, (6)...
...Arithmetic circuit, (7)...Amplification circuit, (8)
...voltage controlled oscillator, (9)...fixed oscillator,
α0...Second mixer, α→...Variable gain amplifier circuit, (6)...-Return gain adjustment circuit, (To)...Detection amplifier circuit, 04)...Timing signal generation circuit, (To )...first gate circuit, 0...second gate circuit,
αη...First polarity judgment circuit, (To)...Second polarity judgment circuit, αAnne/First multiplication circuit, (A)...Absolute value circuit, η...-Second multiplication circuit, To) ...Amplification circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno

Claims (1)

[Claims] A first mixer that receives a pulse-modulated input signal as an LO large input of the output of an RF large input voltage controlled oscillator, a frequency discrimination circuit that discriminates the IF ratio output frequency of this mixer, and a predetermined part of the output of this frequency discrimination circuit. A sampling circuit that samples the signal, a zero-order hold circuit that holds the signal sampled by this sampling circuit until the next input signal arrives, and an oscillation frequency of the voltage-controlled oscillator that integrates the output of this zero-order hold circuit. a fixed oscillator that oscillates at a frequency equivalent to the null point of the frequency discrimination circuit;
In an automatic frequency control device having a second mixer which inputs the output of the fixed oscillator as a large RF input and receives the output of the voltage controlled oscillator as a large LO input, the automatic frequency control device includes a variable gain amplifier circuit whose gain can be electrically controlled; A loop gain adjustment that uses the output signal of the hold circuit to determine the magnitude of the loop DC gain with respect to the repetition frequency of the input signal, and controls the loop DC gain so that the loop DC gain always matches the repetition frequency of the input signal. 1. A synchronous oscillation automatic frequency control device comprising: a synchronous oscillation automatic frequency control device;