SU1354429A1 - Discriminator of clock unit - Google Patents

Abstract

The invention relates to telecommunications and increases noise immunity. The device contains M input processing units 1, M-channel sampling and storage unit (BVZ) 2, M-channel delay unit 5, M-channel recording pulse generator. (FIZ) 6. The additional M-channel BVZ 3 and FIZ 7, as well as block 4 subtraction, are newly introduced. Each of the M blocks 1 contains a resonant switched-al 8, a linear detector 9 and BVZ 10. 1 Cp f-ly, 2 ill. from 00 ate; o

Description

The invention relates to telecommunications and can be used in clock synchronization devices of synchronous radio communication systems with discrete frequency-manipulated signals.

The purpose of the invention. - increase noise immunity.

FIG. 1 shows the structural electrical circuit of the discriminator of the clock synchronization device in FIG. 2 - time diagrams of signals, explaining the operation of the discriminator.

The discriminator of the clock synchronization device contains M input processing units 1, M-channel sampling and storage unit 2, additional M-channel sampling and storage unit 3, subtraction unit 4, M-channel delay unit 5, M-channel driver 6 pulses recording, optional M-channel driver 7 write pulses.

Each of the M processing units 1 of the input signal contains a resonant switched amplifier 8, a linear detector 9, and a sampling and storage unit 10.

The discriminator device clock synchronization works as follows.

Consider the operation of the discriminator of the clock synchronization device for servants (in which the processing units 1 are conventionally called the first processing unit and the second processing unit).

The input discrete frequency-manipulated (DFM) signal (Fig. 2a), the frequency elements of which for the case have the values of the frequencies f

and f, enters (FIG. 1) to the information inputs M of the processing units 1 (for the case, to the information inputs of the first and second processing units) and respectively to the information inputs of the resonant switched amplifiers 8. At the same time, from the corresponding outputs of the clock synchronization device (not shown ), a component of which is the proposed discriminator of the clock synchronization device, to the Record and Vibration Silence Inputs of the Processing Blocks 1 are fed from T1 transmitting signals (Fig. 2k), which go to the control inputs dyes correspond

a resonant switched amplifier 8 and a sampling and storage unit 10. As a result, in the resonant switched amplifiers 8, tuned to the cases f and f, respectively, the input signal is processed at the time interval t, - &, where t, is the estimate of the time corresponding to the change of the frequency elements of the PMF signal, iT / 2, T - the average duration of the frequency element. Interval,. duration

5 2d is equal to the interval between two adjacent pulses of the control signal arriving at the control input of the resonant switched amplifiers 8 and performing the damping of oscillations

0 in them.

The signals from the outputs of the resonant switched amplifiers 8 are detected in the linear detectors 9 of the first and second processing units, which are built for the case, respectively, at frequencies f, and f. (Fig. 2m, for the first processing unit, Fig. 2o, for the second processing unit) and then come to the input of the sampling unit 10

Q and memorization, in which at the end of the processing time interval, but before damping the oscillations in the resonant switched amplifiers 8, the signal is sampled and memorized.

The signals from the outputs of the sampling and memorizing units 10 (Fig. 2n, for the first processing unit, Fig. 2n, for the second processing unit) are sent to the corresponding information inputs of the M-channel sampling and storage unit 2 and the additional M-channel sampling and memorization unit 3 which are controlled by the signals generated as follows.

The decision device (not shown), which receives the input DFM signal, with a delay equal to the duration of the frequency element of the input DFM signal, generates signals (fig. 2g and g - corresponding to the first and second processing units), determining which frequency element of the input PMM signal enters the discriminator device clock synchronization. These signals are sent to the corresponding information inputs of an additional M-channel driver 7 and 5

0

five

0

five

recording pulses and information inputs of the M-channel delay unit 5 (delaying for a time equal to the duration of the frequency element of the input DFM signal), the output signals of which follow through the M-channel driver 6 write pulses to the control inputs of the M-channel unit 2 samples and memorization (figs. and and - corresponding to the first and second processing units).

The signals from the outputs of the additional M-channel 1 of the driver 7 write pulses (Fig. 2e and W, corresponding to the first and second processing units) are received at the corresponding control paths of the additional M-channel unit 3 sampling and recall. At the same time, the clock input of the M-channel delay unit 5 and the combined clock inputs of the M-channel driver 6 write pulses and the additional M-channel driver 7 write pulses are followed by a sequence of clock pulses (FIG. 26 and c) from the corresponding first and second clock inputs of the discriminator clock synchronization devices that are connected to the corresponding outputs of the specified clock synchronization device.

The output signals of the M-channel sampling and storage unit 2 and the additional M-channel sampling and storage unit 3 (Fig. 2-p and c) are sent to the subtraction unit 4, the output signal of which (Fig. 2t) determines the time error between the moments of change (boundaries) of the frequency elements of the input signal and the middle processing interval.

F o rmula of the invention

Claims (2)

1. The discriminator of the clock synchronization device, which contains series-connected M-channel delay unit, write pulse shaper and sample and memory unit, as well as M input signal processing units, whose outputs are connected to the corresponding information inputs of the M-channel sample and memory unit, the control inputs of which are connected to the corresponding M-channel outputs write pulse generator, the combined information inputs, the combined inputs Recording and the combined inputs Muting damping M input signal processing units are respectively the information input, Recording input and the Oscillator oscillation damping, information and clock inputs of the delay unit and clock input M-channel the write pulse driver are the inputs of the frequency element of the input signal and the first and second clock inputs of the discriminator, respectively, which are different In order to increase noise immunity, additional M-channel shapers of the recording pulses are entered in the sample and memory unit, as well as a subtraction unit, while the information inputs and output of the additional sample and memory unit are connected respectively to the outputs of the corresponding M input signal processing units and the first input of the subtraction unit, the second input of which is connected to the output of the main M-channel block of sampling and storage, the information inputs of the additional MC The anal pulse shaper of the recording pulses are combined with the corresponding information inputs of the main M-channel delay unit, and the clock input of the additional M-channel shaper of recording pulses is combined with the clock input of the main M-channel shaper of recording pulses, the output of the subtractor being the output of the discriminator. 2. A discriminator according to claim 1, characterized in that each of the M input signal processing units is configured as a series-connected resonant switched amplifier, a linear detector and a sample and memory unit, the information and control inputs of the resonant switched amplifier and control input and the output of the block of sampling and memorization is respectively the information input, the input Oscillation damping, the Recording input and the output of the processing block the input | Nogo signal. I 1 . d aOoftiftsujj ti, I: o c: Ci. tj K J L SC1