JPS58225708A - Current mirror circuit - Google Patents

Current mirror circuit

Info

Publication number
JPS58225708A
JPS58225708A JP57108740A JP10874082A JPS58225708A JP S58225708 A JPS58225708 A JP S58225708A JP 57108740 A JP57108740 A JP 57108740A JP 10874082 A JP10874082 A JP 10874082A JP S58225708 A JPS58225708 A JP S58225708A
Authority
JP
Japan
Prior art keywords
current
transistor
collector
emitter
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57108740A
Other languages
Japanese (ja)
Other versions
JPH0452644B2 (en
Inventor
Koji Uno
廣司 宇野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57108740A priority Critical patent/JPS58225708A/en
Publication of JPS58225708A publication Critical patent/JPS58225708A/en
Publication of JPH0452644B2 publication Critical patent/JPH0452644B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To improve the precision of a mirror circuit by adding a by-pass route wherein the collector current of the clamping transistor (TR) of an IC-implemented current mirror circuit is controlled. CONSTITUTION:A TRT4 is grounded directly at its emitter and connected at its collector to the emitter of a TRT1 to form the by-pass route 1. The base of the TRT4 is connected to the collector of the TRT1 and its base current is adjusted by a TRT5 and a resistance R4 connected between its collector and the ground. The collector and base of the TRT5 are short-circuited and it is used as a diode. The collector of the TRT4 is connected to the emitter (point P1) of the TRT1 to use some percentage of a current flowing to the point P1 as the collector current IC4 of the TRT4. The remainder is the emitter current of the TRT1, i.e. its collector current IC1 and base current IB1, but as the emitter current of the TRT1 is reduced, the IB1 is reduced.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、集積回路化されたカーレントミラー回路に関
し、特にそのラテラル構造で電流増幅率の小さいベース
電流供給用兼りランプ用のPNP トランジスタがミラ
ー電流の対称性に与える影響を除去しようとするもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an integrated current mirror circuit, and in particular, the present invention relates to an integrated current mirror circuit, and in particular, a PNP transistor for base current supply and lamp, which has a lateral structure and has a small current amplification factor, is used for supplying a base current and for a lamp. The aim is to eliminate the influence on the symmetry of

従来技術と問題点 第1図に示すカーレントミラー回路は、ベースを共通に
した一対のトランジスタT2.T3の一方T2に定電流
■1が流れるとき、抵抗R2に発生する電圧に等しい電
圧が抵抗R3に発生するように他方T3から負荷りに電
流が流れ、R2=R3なら負荷りに流れ込む電流I2の
値が■1と等しくなることを利用して構成されるもので
あるが、これをIC化するとPNP トランジスタT1
の電流増幅率βが問題となる。トランジスタT+はトラ
ンジスタT2.T”3にベース電流を流させ、かつトラ
ンジスタT2が飽和しないようにそのコレクタ電圧をク
ランプするものであるが、が覧るトランジスタT1があ
ると、そのベース電流が定電流源11に流入するので、
これがミラー電流■2の予定値I五からのずれを招く。
Prior Art and Problems The current mirror circuit shown in FIG. 1 consists of a pair of transistors T2. When a constant current 1 flows through one T2 of T3, a current flows from the other T3 to the load so that a voltage equal to the voltage generated across the resistor R2 is generated across the resistor R3, and if R2=R3, the current I2 flows into the load. It is constructed by taking advantage of the fact that the value of is equal to 1, but when this is made into an IC, a PNP transistor T1
The current amplification factor β becomes a problem. Transistor T+ is transistor T2. It allows the base current to flow through T"3 and clamps its collector voltage so that the transistor T2 does not saturate. However, if there is a transistor T1, the base current flows into the constant current source 11. ,
This causes a deviation of the mirror current (2) from the planned value I5.

これらを更に詳しく説明するに、トランジスタTI、T
2.・・・・・・のベース電流を’Bl、l112.・
・・・・・、コレクタ電流をIce、  Ic2.・・
・・・・、エミッタ電流を15.、I)l、2.・・・
・・・とすると、IC技術によりPNP l−ランジス
タT2.T3に同等の特性を持たせることば可能である
から、R2=R・3なら図示結線では 1112 鴇IB3 r  IF5 ’= IF3 +
 IC2’= IC3となる。従って 12 = IC3= IF5  Ina = Ic2=
 IF5 1112= I + −I旧       
    ・ ・・■の関係が成り立つので、IBlが充
分に小さければ12=I lとなり流れ出し電流■1を
流れ込み電流I2に変換できる。ところが、IC技術に
おけるPNP )ランジスタは一般にラテラル型であっ
て電流増幅率βが小さく、従ってベース電流が大きくな
る。PNP )ランジスタT1はトランジスタT2.T
3のベース電流■B2.1B、を供給する目的(この限
りでは抵抗でもよい)の他に、トランジスタT2が飽和
しないようにそのコレクタ電位をクランプする役割を果
たす。つまり、電源E1から抵抗R2による電圧降下だ
け下ったトランジスタT2のエミッタ電位に対し、その
コレクタ電位を更に2 VBEだけ低い値にクランプし
て飽和しないようにする。2 VBgはトランジスタT
 + 。
To explain these in more detail, the transistors TI, T
2. The base current of . . . is 'Bl, l112.・
..., the collector current is Ice, Ic2.・・・
..., the emitter current is 15. ,I)l,2. ...
..., PNP l-transistor T2. Since it is possible to give T3 the same characteristics, if R2=R・3, the connection shown in the diagram is 1112 IB3 r IF5 '= IF3 +
IC2'=IC3. Therefore 12 = IC3= IF5 Ina = Ic2=
IF5 1112= I + -I old
... Since the relationship ■ holds true, if IBl is sufficiently small, 12=I l, and the outflow current ■1 can be converted into the inflow current I2. However, PNP transistors in IC technology are generally of the lateral type and have a small current amplification factor β, resulting in a large base current. ) transistor T1 is connected to transistor T2.PNP). T
In addition to the purpose of supplying the base current 2.1B of transistor T2 (a resistor may be used as far as this goes), it also serves to clamp the collector potential of the transistor T2 so that it does not become saturated. That is, with respect to the emitter potential of the transistor T2, which is lowered by the voltage drop caused by the resistor R2 from the power source E1, the collector potential is further clamped to a value lower by 2 VBE to prevent saturation. 2 VBg is transistor T
+.

T2のベース、エミッタ間電圧の和である。かかる目的
で使用されるトランジスタT+が引込むエミッタ電流I
。1は、抵抗R1に流れる電流とトランジスタT2.T
3のベース電流1112.+113の和であるから、β
小ではベース電流l111が大となり0式のIBIが無
視できなくなる。しかもβには製造バラツキがあるので
、負荷りに流れる電流■2はIRいによる誤差を含むば
かりてな(、ロット毎にバラツキが変る欠点がある。
This is the sum of the voltage between the base and emitter of T2. The emitter current I drawn by the transistor T+ used for this purpose
. 1 is the current flowing through the resistor R1 and the transistor T2. T
3 base current 1112. Since it is the sum of +113, β
If it is small, the base current l111 becomes large and the IBI of formula 0 cannot be ignored. Moreover, since there are manufacturing variations in β, the current (2) flowing through the load only includes errors due to IR resistance (it has the disadvantage that the variations vary from lot to lot).

発明の目的 本発明は、クランプ用トランジスタのベース電流を小さ
くできるバイパス回路を追加し、クランプ機能を損なわ
せることなく上述した欠点を解決しようとするものであ
る。
OBJECTS OF THE INVENTION The present invention aims to solve the above-mentioned drawbacks without impairing the clamping function by adding a bypass circuit that can reduce the base current of the clamping transistor.

発明の構成 本発明は、ベースが共通に接続された特性の等しい一対
のトランジスタの一方に定電流源を接続して定電流を流
すことで他方に接続された負荷に該定電流とほぼ等しい
ミラー電流を流す回路構成を有し、且つ該一対のトラン
ジスタのベース電流を流す素子に、該定電流源側のトラ
ンジスタを非飽和に保持する第1のトランジスタを用い
た、集積回路化されたカーレントミラー回路において、
該第1のトランジスタが引込む電流の一部をバイパスす
る第2のトランジスタと、該第1のトランジスタのコレ
クタ、エミッタ間に流れる電流から該第2のトランジス
タにバイパスする電流値を決定するダイオード接続され
た第3のトランジスタまたはダイオードとを備え、該第
1のトランジスタのベース電流を減少して前記ミラー電
流の値を前記定電流値に接近させるようにしてなること
を特徴とするが、以下図示の実施例を参照しながらこれ
を詳細に説明する。
Structure of the Invention The present invention is characterized in that a constant current source is connected to one of a pair of transistors having the same characteristics and whose bases are connected in common, and a constant current is caused to flow therethrough. A current integrated circuit that has a circuit configuration that allows current to flow, and uses a first transistor that holds the transistor on the constant current source side in non-saturation as an element that flows the base current of the pair of transistors. In the mirror circuit,
a second transistor that bypasses a portion of the current drawn by the first transistor; and a diode-connected transistor that determines a current value to be bypassed to the second transistor from the current flowing between the collector and emitter of the first transistor. and a third transistor or diode, the base current of the first transistor is reduced so that the value of the mirror current approaches the constant current value. This will be explained in detail with reference to examples.

第2図は本発明の一実施例で、第1図の回路にNPN 
l−ランジスタT4.T5および抵抗R4からなるバイ
パス回路を付加したものである。トランジスタT4はそ
のエミッタを直接接地し、且っコレクタをトランジスタ
TIのエミッタに接続してバイパスルートを形成する。
FIG. 2 shows an embodiment of the present invention, in which the circuit of FIG.
l-transistor T4. A bypass circuit consisting of T5 and resistor R4 is added. Transistor T4 has its emitter directly grounded and its collector connected to the emitter of transistor TI to form a bypass route.

このトランジスタT4のベースはトランジスタT1のコ
レクタに接続され、該コレクタとアース間に直列接続さ
れたトランジスタT5および抵抗R4によってそのベー
ス電流が調整される。トランジスタT5はコレクタ、ベ
ース間が短絡され、ダイオードとして用いられる。トラ
ンジスタT4のコレクタがトランジスタT1のエミッタ
(P+点)に接続されることにより、P1点に流れ込む
電流の何割ががトランジスタT4のコレクタ電流I。4
となる。残りはトランジスタT1のエミッタ電流従って
同コレクタ電流I。1とベース電流11,1になるが、
TIのエミッタ電流を小さくできれば1111も小さく
なる。
The base of transistor T4 is connected to the collector of transistor T1, and its base current is adjusted by transistor T5 and resistor R4, which are connected in series between the collector and ground. The collector and base of the transistor T5 are short-circuited and used as a diode. Since the collector of the transistor T4 is connected to the emitter (point P+) of the transistor T1, a percentage of the current flowing into the point P1 is the collector current I of the transistor T4. 4
becomes. The remainder is the emitter current and therefore the collector current I of the transistor T1. 1 and the base current becomes 11,1, but
If the emitter current of TI can be reduced, 1111 can also be reduced.

トランジスタT+のエミッタ電流を小さくするためには
lC4を大きくすればよく、その比(Ic4/IC1で
代表する)は下式により定められる。
In order to reduce the emitter current of transistor T+, it is sufficient to increase lC4, and the ratio (represented by Ic4/IC1) is determined by the following formula.

ここでv=rはボルツマン定数に1電気素量q、絶対温
度Tで表わされる定数(V、、、 −k T / Q 
) テ、T−300°にでおよそ26mVである。
Here, v=r is a constant (V, , -k T / Q
) Te, approximately 26 mV at T-300°.

上述した電流比は抵抗R4の値により任意に設定できる
ので、例えばIc4 / ic、 = 9に設定すれば
コレクタ電流Ic1は第1図のl/10になる。
The above-mentioned current ratio can be arbitrarily set by the value of the resistor R4. For example, if Ic4/ic is set to 9, the collector current Ic1 becomes 1/10 in FIG.

従って、l−ランジスタT1の電流増幅率βが同じでも
そのベース電流IB1を1/10に低減できる。
Therefore, even if the current amplification factor β of the l-transistor T1 is the same, its base current IB1 can be reduced to 1/10.

第2図の回路でトランジスタT4のエミッタとアース間
に抵抗Ra(第3図参照)を挿入してもよく、この場合
電流比1c4/ io、は抵抗比R4/Roにより設定
できる。しかし第2図のように抵抗RI+がなくてもよ
く、この場合はトランジスタT4.T5のVnEはそれ
ぞれエミッタ電流に比例するという特徴を利用している
In the circuit of FIG. 2, a resistor Ra (see FIG. 3) may be inserted between the emitter of the transistor T4 and the ground, and in this case, the current ratio 1c4/io can be set by the resistance ratio R4/Ro. However, as shown in FIG. 2, the resistor RI+ may be omitted; in this case, the transistor T4. The characteristic that VnE of T5 is proportional to the emitter current is utilized.

第3図は本発明の他の実施例で、第2図に対し次の3点
を変形したものである。第1はPNPiランジスタT1
に同様のPNP )ランジスタT1′をダーリントン接
続して総合的な電流増幅率を増大させ、これにより定電
流fil+に流れ込むベース電流i n、 rを第2図
の’IlHに比し更に低減した点である。第2は前述し
たように抵抗R5を追加して電流比1c4/Iclの設
定の自由度を増した点、そして第3はトランジスタT3
にパラレルに同種のトランジスタT3’、T3.・・・
・・・を接続して負荷りに流れる電流I2をI−の複数
倍に増幅するようにした点である。これらの変更点は全
て同時に採用する必要はない。抵抗R4,R5を共に省
略し、トランジスタT 4’、 T aをそれぞれ複数
個パラレルに接続する或いはそれらのエミッタ面積を変
えてもよい。また回路全体のトランジスタのタイプ(P
NP、NPN)を入れ換えてもよい。       )
発明の効果 以上述べたように本発明によれば、IC化されたカーレ
ントミラー回路のクランプ用トランジスタのコレクタ電
流を、コントロールされたバイパスルートを付加するこ
とにより低減し、これにより該トランジスタのベース電
流を微小にすることができるのでミラー電流の精度を向
上できる利点がある。
FIG. 3 shows another embodiment of the present invention, which is modified from FIG. 2 in the following three points. The first is PNPi transistor T1
A similar PNP) transistor T1' is connected to Darlington to increase the overall current amplification factor, thereby further reducing the base current in, r flowing into the constant current fil+ compared to 'IlH in Fig. 2. It is. The second is that the resistor R5 is added as described above to increase the degree of freedom in setting the current ratio 1c4/Icl, and the third is the transistor T3.
The same type of transistors T3', T3. ...
... is connected to amplify the current I2 flowing through the load to multiple times I-. All of these changes need not be adopted at the same time. Both resistors R4 and R5 may be omitted, and a plurality of transistors T4' and Ta may be connected in parallel, or their emitter areas may be changed. Also, the type of transistor in the entire circuit (P
NP, NPN) may be replaced. )
Effects of the Invention As described above, according to the present invention, the collector current of the clamping transistor of a current mirror circuit integrated into an IC is reduced by adding a controlled bypass route, and thereby the base of the transistor is reduced. Since the current can be made very small, there is an advantage that the precision of the mirror current can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のカーレントミラー回路の一例を示す回路
図、第2図および第3図は本発明の異なる実施例を示す
回路図である。 図中、TIはクランプ用の第1のトランジスタ、T2.
T3は一対のトランジスタ、T4はバイパス用の第2の
トランジスタ、T5はダイオード接続された第3のトラ
ンジスタ、I+は定電流源、Lは負荷である。 出願人 富士通株式会社 代理人弁理士  青  柳    稔 3 第1図 F( 第2図 1:+
FIG. 1 is a circuit diagram showing an example of a conventional current mirror circuit, and FIGS. 2 and 3 are circuit diagrams showing different embodiments of the present invention. In the figure, TI is the first transistor for clamping, T2.
T3 is a pair of transistors, T4 is a second transistor for bypass, T5 is a diode-connected third transistor, I+ is a constant current source, and L is a load. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi 3 Figure 1 F (Figure 2 1: +

Claims (2)

【特許請求の範囲】[Claims] (1)ベースが共通に接続された特性の等しい一対のト
ランジスタの一方に定電流源を接続して定電流を流すこ
とで他方に接続された負荷に該定電流とほぼ等しいミラ
ー電流を流す回路構成を有し、且つ該一対のトランジス
タのベース電流を流す素子に、該定電流源側のトランジ
スタを非飽和に保持する第1のトランジスタを用いた、
集積回路化されたカーレントミラー回路において、該第
1のトランジスタが引込む電流の一部をバイパスする第
2のトランジスタと、該第1のトランジスタのコレクタ
、エミッタ間に流れる電流から該第2のトランジスタに
バイパスする電流値を決定するダイオード接続された第
3のトランジスタまたはダイオードとを備え、該第1の
トランジスタのベース電流を減少して前記ミラー電流の
値を前記定電流値に接近させるようにしてなることを特
徴とするカーレントミラー回路。
(1) A circuit that connects a constant current source to one of a pair of transistors with the same characteristics and whose bases are connected in common and causes a constant current to flow, thereby causing a mirror current approximately equal to the constant current to flow through the load connected to the other. a first transistor that maintains the transistor on the constant current source side in a non-saturated state is used as an element that has a configuration and causes the base current of the pair of transistors to flow;
In an integrated current mirror circuit, a second transistor bypasses a part of the current drawn by the first transistor, and a current flowing between the collector and emitter of the first transistor is extracted from the second transistor. and a diode-connected third transistor or diode that determines a current value to be bypassed to reduce the base current of the first transistor to bring the value of the mirror current close to the constant current value. A current mirror circuit characterized by:
(2)第1のトランジスタがダーリントン接続された複
合トランジスタであることを特徴とする特許請求の範囲
第1項記載のカーレントミラー回路。
(2) The current mirror circuit according to claim 1, wherein the first transistor is a Darlington-connected composite transistor.
JP57108740A 1982-06-24 1982-06-24 Current mirror circuit Granted JPS58225708A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57108740A JPS58225708A (en) 1982-06-24 1982-06-24 Current mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57108740A JPS58225708A (en) 1982-06-24 1982-06-24 Current mirror circuit

Publications (2)

Publication Number Publication Date
JPS58225708A true JPS58225708A (en) 1983-12-27
JPH0452644B2 JPH0452644B2 (en) 1992-08-24

Family

ID=14492315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57108740A Granted JPS58225708A (en) 1982-06-24 1982-06-24 Current mirror circuit

Country Status (1)

Country Link
JP (1) JPS58225708A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144906A (en) * 1984-12-19 1986-07-02 Nec Corp Current mirror circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137456A (en) * 1974-04-11 1975-10-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137456A (en) * 1974-04-11 1975-10-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144906A (en) * 1984-12-19 1986-07-02 Nec Corp Current mirror circuit

Also Published As

Publication number Publication date
JPH0452644B2 (en) 1992-08-24

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