JPS58225670A - N-channel mos integrated circuit and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates generally to semiconductor integrated circuits, and more particularly to an advanced integrated circuit having a single self-aligned thick film doped region.

No. 3,751,722, filed by the present applicant, discloses a MOB-type semicircular structure of an n-channel structure in which a p-doped surface region is self-aligned beneath an extended region of thick oxide. A conductive semiconductor ladder circuit is disclosed.

In the upper surface of the p-type substrate there is a doped surface region, preferably formed by implantation of ion implants; as in the case of adjacent source and drain regions of two unrelated MOFEs; Extending and contacting the n-shaped regions of two adjacent unrelated MOB devices.

In particular, it has been found that this structure substantially eliminates the parasitic field inversion and feedthrough mechanisms of high speed, high density n-channel MO8 integrated circuits when forced to use opposite substrate biases. . In recent years, this structure has also been used with the same characteristics in 0M0B n-well integrated circuits.

Since the beginning of 1972, this structure tX-n channel MO, which has been described as being identical to +OOPLAMO8 structure.
Widely used in 8-gauge circuits.

00PLAMO8 is a registered four stick of Standard Migro System Company. However, in recent years significant advances have been made in MOB processing technology in the direction of size reduction. Thus increasing the density of n-channel orchard circuits per g2+. Whereas in the early 1970s the linewidth, or width of the active channel area, was standard in the range g2 of 101 Gron. Many n-channel integrated circuits manufactured today have line widths of 1 to 4 tgrons.

In the structure disclosed in the aforementioned U.S. Pat. No. 3,751,722, the boron impurity in the doped surface region is
During the formation of a region of thick oxide expanse that grows overlyingly as it is heated, the MO8
It can be laterally diffused into the active channel region of the device. In integrated circuits where the width of the active channel is on the order of 10 tgrons, this lateral diffusion of boron tX
It has virtually no influence on the operation of MOS devices. In such a circuit, this diffusion &1 is typically of the order of magnitude. However, if the channel width is only 2 to 3 tons, then the MOB collection wI (b) is even smaller than 62 tons.
In the channel, lateral boron diffusion toward the edge of the active channel smaller than 0.5 microns can increase the concentration of boron doping in a critical portion of the active channel region. Thus, in the latter case, a much larger proportion of the total channel experiences an increase in boron doping concentration. This results in degradation of transistor performance. This is because the ends of the channel where this occurs suffer from reduced mobility due to increased impurity dispersion (thus lower gain), increased threshold voltage, and parasitic coupling between the Dracy channel and the source-channel. This is because they experience an increase in capacity. These effects tend to degrade the performance of integrated circuits in terms of their speed performance.

Recognizing the undesirable effect of lateral diffusion of creepage into the active channel region of a narrow channel MOS device, this lateral diffusion is eliminated or reduced. And also some attempts have been made to reduce the parasitic junction capacitance that occurs between the heavily doped n+ drain or source or the diffused intermediate indirect MftR region and the p-type thick extended surface doping region. There is.

Two such attempts are described next. One of them & 1K Wang, Nis Sara, Double Middle Hunter, Pitcher 1 Tsutaji, Beyoung's Direct Motor 1 Isolation for VLSI (Moat 18o
1at1on)'.

This was announced at the 1981 International Electronic Devices Research Conference in the District of Columbia.

The other one is K Kurosawa, T Shibata, -Ichi.
□ ('Bird's beak-shaped free 9-field 9-eightray technology for VL8I devices' by Iizuka L.
This was announced at the 1981 International Electronic Devices Research Conference in the District of Columbia.

However, these prior attempts have not eliminated or reduced the lateral diffusion of the boron-field doping region in the active channel region of the MO8 device, and at the same time also exploited the advantages of the OOPLAMO8 structure, especially the surface area associated with this structure. There has been no evidence of success in maintaining a high degree of flatness.

It is an object of the present invention to provide an MO8 integrated circuit with a narrow active channel region, such that parasitic region inversion is eliminated by providing a doped surface region.

Another object of the invention is the narrow channel MO81'i'11T
It is an object of the present invention to provide an MO8 bomber circuit in a form that is said to be amenable to effective high speed operation in 52.

Yet another objective of the present invention is that the lateral diffusion of field-doped surface regions into the active channel region of MO8 devices is sufficiently reduced.

Or to provide an MO8 integrated circuit that can be removed.

For these purposes, the MO8 integrated circuit of the present invention includes an active channel region between the source and drain regions. A doped surface flFils that is self-aligned with the overlying thick oxide region is selectively formed outside or coincident with the active channel region. In the method for creating this structure, sloped silicon dioxide sidewalls are used as a mask for implantation during the implantation of impurities into the base forming the doped surface region. This is a method of isolating the doped surface region by a desired distance from the active channel region.

To achieve the above and other purposes described below.

The present invention is defined in the claims and added to the chemically deposited silicon dioxide with a thickness of 30
00X to 6000X) is deposited on the surface of the wafer. As seen in FIG. 2b, the thickness of the deposited silicon dioxide layer 26 is also greater where it extends over the upper corners of the silicon mononitride-silicon dioxide dielectric 22-24.

After that, as shown in FIG. 20, m: layer 2 of silicon oxide y.
6 is directional 52 reactive ion etching (dira
This process is described in the paper entitled ``Hot Electron Gate Current Removal in Lightly Doped Drain-Source Structures''.

This was announced by Ogura et al. in December 1981 at the International Electronic Devices Research Group.

Direction i two reacting ions nine etching (dlrect
The ional RIE step removes all of the deposited silicon dioxide layer 26 on the planar or silicon nitride-silicon dioxide dielectric side of the structure. Layer 2 of silylon dioxide at the outer edge of the body layer
Comparatively, the same thick part of 6 is in the form of an inclined side wall 28.
It remains after the internal ion etching stage. This side extends downwardly and outwardly from the upper surface of the a2a&z dielectric layer 22.24 to the surface of the substrate.

A thin layer 8o of silicon dioxide is then grown bi-thermally on the surface 4 of the t/II conductor substrate 10. Thereafter, as shown by arrow 82 in this structure tX, the 20Key and 200Key
It is subjected to the implantation of ions with energies between 1 and 2. The portion of the implantation process will vary depending on the required surface concentration of boron. The relatively thick portions of the dielectric layer 22, 24 and the sloped silicon dioxide sidewall 28 serve as implants and masks. This allows the boron ions to pass radix only through the relatively thin portions of the sidewalls and through the thin silicon dioxide layer 30. This forms a p-type 1 Nidogged surface region as shown in FIG. 2d.

Then, as shown in FIG. 2e, all exposed areas of chemically vapor deposited or thermally grown silicon dioxide are located over the selected areas of the silicon substrate 10. One etch is removed leaving selectively etched silicon nitride-silicon dioxide layers 22-24. At this stage in the fabrication of the MO8 semiconductor integrated circuit structure, a p-type doped surface region 84 formed by selectively masked boron ion implantation is applied to the peripheral edge of the dielectric layer 22=24. in the upper surface of the substrate, except around. surface area 3
4 is controlled by a distance W from the layer 22.24. This distance is a function of the sloped sidewalls 28 of the silicon monoxide and is typically on the order of 0.3 to 1.5 microns.

The thick oxide region 86 is then selectively thermally removed using the dielectric layer as an oxidation barrier, as shown in Figure 2f.
Two are made to grow. Thereby.

As pointed out in U.S. Pat. No. 3,751,722, the operation of a thick oxide region 86 and a p-doped surface region 84 that is self-aligned with the upper surface of the substrate A mesa 88 is formed in the substrate. Diffusion (drive-in) time and temperature.

A particular combination of subsequent oxidation times and temperatures can be selected by the process engineer to achieve the primary structure. The structure may be close to the active mesa, away from it, or extend a little into the active mesa, as the p-shaded region 84 in the final structure was designed by the Guess engineers. The selection of these process parameters is within the ability of a process engineer of ordinary skill in the art.

However, these parameters are described herein below with reference to the accompanying drawings.
The present invention relates to a method for manufacturing integrated circuit structures.

FIG. 1 is a cross-sectional view of a MOEI semiconductor integrated circuit field effect transistor (FET). This transistor is 19
5: OS Field Effect Transistors and Integrated Circuits by Tutschman, published by John Wiley & Son, 1973, and US Pat. No. 3,751,722. ing. Since Figure 1 is in the width direction of the channel -
The n+ source and drain regions of FE'I' are not shown.

The structure of the FET shown in Figure 1 is typically 5 to 1.
It includes a substrate 10 of p-type silicon with a resistivity of 00 ohms and an orientation of (100). Typical thermally to a thickness of 4000A to 1200OA 5: overlying a thick oxide region 12 being grown and self-aligned with a doped surface region 14 of a pf impurity, e.g. . The dogged region 14 is adjacent to the n0 dogged region of the functional ytIJMO8 device and also the 5 1 mesa (such as &1.16).
masaβ)l.

The mesa 16 is formed on the substrate by the method of localized thermal growth of an oxide layer into the substrate. This prevents the formation of parasitic field inversions in the substrate between adjacent MO8 devices, as described in Figure 1 MO8F) i!
T is also doped polycrystalline silicon gate electrode 18
Contains. The structure is then typically capped by a dielectric layer 20, typically a phosphorus-doped silicon dioxide layer.

Figure 1 5 = Ordinary integrated surface road structure of the shape shown
In i, the p-type doped surface region 14
As can be seen in the cross-sectional view of Figure 1, boron impurities from
2. In the edge of the active channel region between the source and drain regions 5 = facing, and laterally (2) along the sidewall of the mesa 16. In the edge of the active channel region 1 = facing This elementary diffusion was not very important in the past when the active channel of an n-channel FLET of this configuration was on the order of 10 microns.

However, in more recent years, when the channel of such devices is typically in the range of 1 to 4 ton, the diffusion of boron impurities into the narrow active channel is
It has been discovered that this has a significant adverse effect on the gain, threshold voltage, and parasitics of O8 devices.

The integrated circuit MO8 device of the present invention, shown in FIGS. 2g-3 and 40, retains the advantages of using parasitic region inversion doggy surface areas as in prior art configurations. are doing.

At the same time, the innermost extension of the dogged surface region one step away from the active channel region.

The selective and controlled positioning maintains the convenience of limiting and preventing diffusion of surface layer encroaching impurities into the active channel region.

It is then produced by selectively creating 52 patterns.

This dielectric layer is 500' thick on top of a thin (200A-100OA) layer 24 of silicon nitride (81,N,) or silicon oxide (810,) as shown in FIG. 2a.
It consists of a silicon nitride layer 22 ranging from A to 2oooi. As is known in the art, a layer of material such as silicon dioxide is used as an etch mask to enable selective etching of the threatened silicon. This dovetail is removed after the etching of the nitride film is completed.

It's not obvious.

A p-doped region 84 such as obtained by this method
Improvements to minimize the spread, or diffusion, in the spear direction can be understood by comparing the structure shown in Figure 2f with the cross section of Figure M1.

Figure 1 shows an MO that is normally made by staying in the middle direction of the channel.
SFET, in which, as already mentioned, the doped region 14 is well diffused laterally within the active channel area at the edge location.

Figure 2f (: The structure shown has been completed along similar usual lines according to a similar process (:) to that described in the above-mentioned patent and the above-mentioned or Tutschmann publication. That is, the silicon nitride layer 22tX is etched using hot sulfuric acid, for example.

The thin I- layer of silicon dioxide is thereby exposed and removed. The layer of silio dioxide is also chemically removed. The structure is cleaned and a new thin layer of silicon dioxide is grown to serve as the gate insulator. The wafer is then subjected to a high temperature annealing and a thin layer of polycrystalline silicon (t1 not shown in the drawing) is deposited over the entire surface of the wafer. The IJV17 layer is selectively etched away by known procedures to leave a polysilicon gate region such as 40. The polysilicon gate region 40 is used as an implant mask in conjunction with a thick oxide layer to mask the effect of the n-type impurity implant to selectively form the drain, source and n+ connection regions. Ru.

A layer 42 of heavily phosphorous doped silicon dioxide is deposited pyrolytically 52 over the entire surface of the wafer. (Second
(Figure 9) The wafer is then heated to a high temperature in a dry nitrogen atmosphere. At this point in the process, the tXn+ source and drain regions 44, 46 and n+ silicon interconnections (not shown in Figure C2) typically exhibit junction depths on the order of 1/4 to 1 micron.

Since Figure 2g is shown in the mid-channel direction,
Source and drain flIiI regions 44 and 46 are not visible t1 in this figure. However, Figures 2a-29 are shown in Figures 1-2. In the cross-sectional view of FIG. 3, which is shown in the longitudinal direction of the channel, there is a plane t, which is 90'
'zThis area is shown. As shown in FIG. 3, openings are selectively made in a layer 42 of IJ doped silicon dioxide. A metal, such as aluminum, is then deposited and selectively etched IFJl to create gold-contacts 48 to the source and drain regions 44, 46 and doped polysilicon gate electrode 40. The p-type I grooved surface region 34, seen along the length of the channel as in FIG. 3, extends far enough to contact the source and drain regions as in the aforementioned patent.

At the same time, it ends at a point isolated from the active channel region as seen in the direction into the channel as shown in FIG. 2g.

4a-40 illustrate several intermediate steps in the fabrication of an integrated circuit MOB device according to another process of the present invention. In this process.

As shown in FIG. 4a, a dielectric layer consisting of a layer 22 of silicon nitride overlying a thin silicon dioxide dove 24 as in the previous embodiment is applied to the surface of the silicon radical 10. selectively created on top. In still other cases, the dielectric layer is simply silicon nitride. The silicon nitride-silicon oxide dielectric layer is then replaced with a thick C4O layer of silicon dioxide (not shown).
ooi~12oooIB- is used as an oxidation barrier for selective FFJl bithermal growth. This layer is then etched away leaving a mesa-like structure 50 forming a silicon nitride dielectric layer thereon. In yet other cases, instead of growing a thick layer of silicon dioxide and etching it away, the surface of the silicon radix is selectively etched to a depth where the structure is as shown in Figure i4a. This is accomplished by being removed. For example, a certain depth is 2ooo
f~6ooo, &, this is isotropic chemical medium etch (18otropic chemical e
toh) using for example hydrofluoric acid and nitric acid and using a patterned layer of silicon nitride as a mask.

A thicker layer of silicon dioxide is then chemically deposited over the structure. In a manner similar to that in the first embodiment, the structure was then subjected to bidirectional ion etching to remove the chemically deposited silicon dioxide 1- that covered the flat portions of the structure. exposed to processing. This leaves the sidewalls 28 of agglomerated silicon dioxide at the edge of the mesa, such as mesa 50 remaining at this stage of the processing sequence, as shown in FIG. 4b.

A layer of silicon dioxide is then thermally grown onto the exposed (flat) portion of the silicon substrate.

A boron implant is then made through the thin oxide layer into the area of silicon beneath the thick oxide. During this implantation step, a thicker dielectric layer 22,24 and a sloped sidewall 2
8 acts as an injection barrier. and the implanted p-type encroachment region 8 created as a result of this implantation step.
4 from the active mesa. The structure obtained by this manufacturing sequence is shown in Figure 4b.

The next thickest silicon oxide film 52 is 4,000 people.
-Selectively grown (or regrown) to a thickness of 12000X
The result is as shown in FIG. 40, the top surface of the silicon mesa 52 is slightly higher as in FIG. 2f, whereas the top surface of the silicon mesa in the active channel area is > except that they reach the same height.
2f It is very similar to the structure shown in FIG. But ji
The properties of the structure in figure tG4o are similar to the property 1 of the structure in figure 2f. And both structures have the advantage of allowing the process engineer to adjust the position of the edge of the doped surface region relative to the edge of the active mesa. The structure of FIG. 40 can then be completed as a complete integrated circuit through the use of the same or similar techniques as employed to complete the fabrication of the first embodiment.

Thus, a semiconductor integrated circuit according to the present invention is provided with a doped surface region that prevents the formation of parasitic inversion regions as taught by the above-mentioned U.S. Pat. It is evaluated that the materials are separated within a range that allows them to be separated or close to each other.

Thus, the important advantages obtained by the structure taught in said patent are maintained, and in addition, the use of integrated circuits in which the channel [1] is significantly reduced is now facilitated.

Although the invention has been described in terms of several embodiments, it will be understood that modifications and changes may be made thereto without necessarily departing from the spirit and scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is based on the prior art. 1 is a cross-sectional view of a semiconductor integrated circuit taken in the direction of the channel at an intermediate stage of its manufacture; FIG. Figures 2a to 2g illustrate each stage of manufacturing the present invention. 1 is a cross-sectional view illustrating an example of a semiconductor integrated circuit. FIG. 3 is a sectional view of the semiconductor integrated circuit in the length direction of the channel indicated by the arrow 8-8g in FIG. 2g. Figures 4a-40 are at various stages of manufacture according to a second embodiment of the invention. FIG. 1 is a cross-sectional view of a semiconductor integrated circuit. lO...Substrate I2...Thick oxide region 14...Surface region 16...Mesa 18...Gate electrode 20...Dielectric layer 22...Nitride layer 24...Silicon dioxide Layer 26...Silicon dioxide layer 28...Side walls 80...Thin silicon dioxide layer 82...Boron ion implantation arrow 84...P-type l-doped surface region 86...Thick oxide Object area 88... Mesa 40... Boxi ζ! Congut gi region 42...Phosphorous doped silicon dioxide layer 44...N+ drain region 46...N+ source region 4 days...Gold-contact 50...Mesa 52...Thick silicon acid (t[ FIG, 2f FIG, 2g FIG, 4a FIG, 4b

Claims (1)

[Claims] 1) A. Substrate of first conductivity type. Source and drain regions of opposite conductivity type formed on the upper surface of the substrate.
C. An active channel region between the source and drain regions. B. A thick oxide region selectively covering a portion of the substrate adjacent to the active channel region. E. Underneath the thick oxide region. two doped surface layers of said first conductivity type in self-alignment therewith;
MOBp structure for semiconductor circuits, characterized in that the doped surface layer seen in section I: in the channel width direction lies in the actual vifFll outside or in close proximity to the active channel region. 2) An integration according to claim 1, characterized in that the doped surface layer is in contact with at least one of the source and drain regions as seen in a cross-section in the channel length direction. circuit. 3) The first conductivity type is p-type, and the doped surface layer is formed by selectively implanting boron ions into the upper surface of the substrate. An integrated circuit structure according to claim 2. 4) Claim I!, characterized in that the width of the active channel is less than 4 t/lC7! The integrated circuit structure according to item 2. 5) The dogged surface layer is isolated from or one step closer to the outer edge of the active gate region, as seen in the direction of the channel. Described dye deposit circuit structure. 6) The dogged surface layer extends to the outer edge of the active channel region, as seen in the direction of the channel, but does not extend to the inner part of the active channel region. Centralized circuit structure as described in Section 3. 7) forming a patterned dielectric layer over a selected portion of a major surface of a silicon substrate of a first conductivity type, with a slope extending downwardly from said dielectric layer to the major surface of said substrate; forming dogged sidewalls of the first conductivity type and a MOS device on a major surface of the substrate, using the dielectric layer as a mask along a relatively thick portion of the sloped sidewalls; selectively forming a width of the dielectric having dimensions of the width of an active channel region and an inner edge of the doped layer terminating away from or close to the outer width limit of the active channel region; implanting ions of the first conductivity type such that the ions enter the substrate through only the relatively thin outer portions of the sloped sidewalls.
8. Method of manufacturing integrated circuits. 8) The step of forming a sloped sidewall. depositing a layer of silicon dioxide over the patterned dielectric layer and the upper surface of the substrate, followed by selective removal of portions of the deposited oxide layer to leave the sloped sidewalls; 8. A method as claimed in claim 7, comprising the steps of: 9. The method of claim 8, wherein said selective removal of said deposited oxide layer includes a step of unidirectionally reactive ion-etching. 10) said implantation step (previously depositing a thin layer of silicon oxide over the remaining portion of said major surface of said silicon substrate extending from the lower edge of said sloped sidewall); 9. The method of claim 8, further comprising the step of thermally growing. 11) As seen in the channel width direction. Thick oxide overlying in self-alignment with said doped layer - in preselected parameters and conditions - to be confined to end at or close to a preselected distance from the edge of the channel region. 11. The method of claim 10, further comprising the step of thermally growing a material layer. 12) Formation of the sloped sidewalls forms an active mesa region and the mesa and the substrate 7. The method of claim 7, further comprising the step of depositing a 1 meter thick layer of oxide and subjecting the substrate to an etching process that selectively removes portions of the thick oxide layer. Method described. 13) Prior to the step of implantation, the method further comprises the step of: thermally growing a thin layer of silicon oxide extending from the lower end of the sloped sidewall. the method of. 14) The lateral diffusion of the dogged layer, as seen in the mid-channel direction, is preselected to be restricted to terminating at a preselected distance or close to the seam of the active channel region. 14. The method of claim 13, further comprising the step of thermally growing a thick oxide layer self-aligned and overlying the doped layer under the same parameters and conditions. 15) Forming a mesa on the surface of a substrate of a first conductivity type with a dielectric layer formed on the upper surface of said mesa, the thickness extending downward from said dielectric layer to the surface of said substrate. forming oxide sidewalls of varying thickness and using the dielectric layer as a mask along relatively thick portions of the sidewalls to coat the surface of the substrate with oxides of the initial conductivity type;
- and + a width of said dielectric layer having dimensions of the width of an active channel region of a MOB device and an inner side of said doped layer terminating away from or close to the outer width limit of said active channel region; selectively implanting ions of the first conductivity type such that the ions pass only through a relatively thin portion of the sloped sidewall into the substrate for shading. 1 characterized by consisting of stages
A method of manufacturing a S08 integrated circuit structure. 16) the step of forming the sidewalls deposits a thick layer of oxide over the mesa and the substrate and subjects the substrate to an etching process that selectively removes portions of the thick oxide; 16. The method of claim 15, comprising the step of exposing. 17) The method of claim 15, further comprising the step of thermally growing a thin layer of silicon oxide extending from the lower end of the sidewall prior to the step of implanting. 1B) As seen in the channel direction 52. Under preselected parameters and conditions, the doped layer is constrained to end in the vicinity of the active channel region or at a preselected distance from its total area. 18. The method of claim 17, further comprising the step of thermally growing a thick oxide layer overlying the deposited layer in self-alignment with the deposited layer.