JPS58225654A - Holder combined with connecting semiconductor - Google Patents
Holder combined with connecting semiconductorInfo
- Publication number
- JPS58225654A JPS58225654A JP10742682A JP10742682A JPS58225654A JP S58225654 A JPS58225654 A JP S58225654A JP 10742682 A JP10742682 A JP 10742682A JP 10742682 A JP10742682 A JP 10742682A JP S58225654 A JPS58225654 A JP S58225654A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- connection
- recess
- current
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体接続保持具に関する。[Detailed description of the invention] The present invention relates to a semiconductor connection holder.
従来、半導体を保護すると同時に接続配線を容易に接続
するため、半導体接続保持具が使用されている。Conventionally, semiconductor connection holders have been used to protect semiconductors and at the same time to easily connect connection wiring.
第１図は従来の半導体接続保持具の一例の分解斜視図で
ある。FIG. 1 is an exploded perspective view of an example of a conventional semiconductor connection holder.
半導体接続保持共は上段２、中段３、下段４の３層構成
であシ、中段３の面上には、はぼ放射状に通電電極５が
配置されている。また、通’［電極５の中段３の外周囲
における配置に対応して、図における下段４の裏面側に
は、接続電極６が備わっている。上記３層は素材の種類
に応じて焼結あるいは接着尋が選択されて組立てられる
。その後、中段３０通電電極と下段４裏面側の接続電極
６とは、各段の外周の側部へめっき等の手段により導体
７を設ける。しかる後、上段２．中段３．下段４を貼合
わせる。The semiconductor connection and holding device has a three-layer structure including an upper layer 2, a middle layer 3, and a lower layer 4. On the surface of the middle layer 3, current-carrying electrodes 5 are arranged radially. In addition, a connection electrode 6 is provided on the back surface side of the lower stage 4 in the figure in correspondence with the arrangement of the middle electrode 5 on the outer periphery of the middle stage 3. The above three layers are assembled by selecting sintering or bonding depending on the type of material. Thereafter, conductors 7 are provided on the sides of the outer periphery of the middle stage 30 current-carrying electrodes and the connection electrodes 6 on the back side of the lower stage 4 by means of plating or the like. After that, the upper row 2. Middle row 3. Attach the bottom row 4.
第２図は従来の半導体チップの一例の斜視図、。FIG. 2 is a perspective view of an example of a conventional semiconductor chip.
第３図（ａ） 、 （ｂ）は半導体チップを実装した半
導体接続保持共の刹視図及びＡ−Ａ’断面図である。FIGS. 3(a) and 3(b) are a perspective view and a cross-sectional view taken along the line AA' of a semiconductor connection holding device with a semiconductor chip mounted thereon.
半導体チップ９には電極１０が設けられている。The semiconductor chip 9 is provided with an electrode 10 .
この半導体チップ９を半導体接続保持具１の凹部にろう
拐１１に結句ける。そして、保持具の通電電極５と半導
体チップの電極１０とを導線８で接続する。This semiconductor chip 9 is placed in the recess of the semiconductor connection holder 1 with a solder 11. Then, the conductive wire 8 connects the current-carrying electrode 5 of the holder and the electrode 10 of the semiconductor chip.
半導体接続保持具１への半導体チップ９の実装は、チッ
プろう付は工程と、導線８の接続工程の２工程に分けら
れる。そして、導線８の接続工程は電極数が多ければ多
い程作業工数が増加するので、非常に時間がかかるとい
う欠点を生ずる。また、導線８の接続のために通電電極
５の占有ｌｆｉ積もある程度の大きさが必要であシ、半
導体接続保持具１は電極数が増えれば増える程大きくな
シ、全体が大きくなってしまうという欠点があった。The mounting of the semiconductor chip 9 on the semiconductor connection holder 1 is divided into two steps: a chip brazing step and a conducting wire 8 connection step. Furthermore, the process of connecting the conductive wires 8 has the disadvantage that it takes a very long time, since the more electrodes there are, the more the number of work steps will be required. Furthermore, the lfi product occupied by the current-carrying electrode 5 must be of a certain size in order to connect the conducting wire 8, and the semiconductor connection holder 1 becomes larger as the number of electrodes increases, resulting in an increase in the overall size. There was a drawback.
本発明は上記欠点を除去し、半導体チップの固着並びに
電極間接続に要する工数を低減し、かつ外形寸法の小型
化をはかった半導体接続保持を提供するものである。The present invention eliminates the above-mentioned drawbacks, reduces the number of man-hours required for fixing semiconductor chips and connecting electrodes, and provides a method for holding semiconductor connections that reduces external dimensions.
本発明の半導体接続保持具は、絶縁基板に半導体チップ
を収容できる大きさに形成された凹部と、搭載される半
導体チップの電極の位置に対応して前記凹部底面に設け
られた通電電極と、前記凹部周囲の前記絶縁基板面に前
記通電電極と同数だけ設けられた導電接続部と、前記通
１！電極と前記導電接続部とを一対一対応で接続する導
体配線と前記通電電極から前記絶縁基板を貫通して四部
形成面と反対側の面に達する貫通孔とを含んで構成され
る。The semiconductor connection holder of the present invention includes: a recess formed in an insulating substrate to a size capable of accommodating a semiconductor chip; and a current-carrying electrode provided on the bottom surface of the recess corresponding to the position of the electrode of the semiconductor chip to be mounted. Conductive connecting portions provided on the insulating substrate surface around the concave portion in the same number as the current-carrying electrodes, and the through 1! It is configured to include a conductor wiring that connects the electrode and the conductive connection part in a one-to-one correspondence, and a through hole that penetrates the insulating substrate from the current-carrying electrode and reaches the surface opposite to the four-part forming surface.
本発明の実施例について図面を用いて説明する。Embodiments of the present invention will be described with reference to the drawings.
第４図ｆａ）〜（Ｃ）は本発明の一実施例の上面斜視図
。FIGS. 4fa) to 4(C) are top perspective views of an embodiment of the present invention.
下面斜視図及びＢ −Ｂ ’断面図である。They are a bottom perspective view and a B-B' sectional view.
絶縁基板２１は正方形または矩形でほぼ平行な二面を有
し、その−面に半導体チップ９を収容できる四部２２を
有す。凹部２２の底面には半導体チップ９の電極１０に
対応する通電電極２３が設けられる。凹部２２の周囲の
基板表面に導電接続部２４を半導体チップの電極１０の
数と同数だけ対応した位置に設け、導体２５で通電電極
２２と導電接続部２４とを接続する。通電電極２２から
基板２１を貫通して反対面に出る貫通孔２６を設ける。The insulating substrate 21 is square or rectangular and has two substantially parallel faces, and has four parts 22 on the negative face of which can accommodate the semiconductor chip 9. A current-carrying electrode 23 corresponding to the electrode 10 of the semiconductor chip 9 is provided on the bottom surface of the recess 22 . Conductive connecting portions 24 are provided on the substrate surface around the recess 22 at positions corresponding to the same number of electrodes 10 of the semiconductor chip, and the conductive electrodes 22 and the conductive connecting portions 24 are connected by conductors 25. A through hole 26 is provided from the current-carrying electrode 22 through the substrate 21 and emerging from the opposite surface.
・（このような構造にすると、第２図に示す半導体
チップ９の電極１０の存在する面を凹部２２の底面に向
けて挿入することによシ半導体チップ９の電極１０と通
電電極２３とが接触するので、貫通孔２６からろう材２
７を流し込めば直ちに接続、固着することができる。ろ
う材２７の流し込みは電極数に関係なく、一度に行うこ
とができるので従来の導線による接続と異なシ、電極数
が増えたら接続工数が増えるということはない。また、
ろう材２７の注入によシミ極間接続と半導体チップの固
着とを同時に行うから、従来のように二工程を要してい
たものが一工程で行うことができる。
(With such a structure, the electrodes 10 of the semiconductor chip 9 and the current-carrying electrodes 23 can be connected to each other by inserting the semiconductor chip 9 shown in FIG. Since they contact each other, the brazing material 2 is removed from the through hole 26.
If you pour 7, you can connect and fix it immediately. The pouring of the brazing material 27 can be performed at once regardless of the number of electrodes, so unlike the conventional connection using conductive wires, the number of connection steps does not increase as the number of electrodes increases. Also,
Since the connection between the stain electrodes and the fixing of the semiconductor chip are simultaneously performed by injecting the brazing material 27, what used to require two steps can be accomplished in one step.
更にまた、導線による接続を行なわないから、通電電極
２３並びに半導体チップの電極１０を小さくでき、小型
化がはかれる。Furthermore, since no connection is made using conductive wires, the current-carrying electrode 23 and the electrode 10 of the semiconductor chip can be made smaller, resulting in miniaturization.
以上詳細に説明したように、本発明によれば、半導体チ
ップの固着並びに電極間接続に要する工数を低減し、か
つ外形寸法を小型化した半導体接続保持具が得られるの
でその効果は大きい。As described in detail above, according to the present invention, it is possible to obtain a semiconductor connection holder that reduces the number of man-hours required for fixing a semiconductor chip and connecting electrodes, and has a smaller external size, so the effects are significant.
第１図は従来の半導体接続保持具の一例の分解５−
斜視図、第２図は従来の半導体チップの一例の斜視図、
第３図（ａ） 、 （ｂ）は半導体チップを実装した半
導体接続保持具の斜視図及び断面図、第４図（ａ）〜（
Ｃ）は本発明の一実施例の上面斜視図、下面斜視図及び
断面図である。
１・・・・・・半導体接続保持具、２・・・・・・上段
、３・・・・・・中段、４・・・・・・下段、５・・・
・・・通電電極、６・・・・・・接続電極、７・・・・
・・導体、８・・・・・・導線、９・・・・・・半導体
チップ、１０・・・・・・電極、１１・・・・・・ろう
材、２０・・・・・・半導体接続保持具、２１・・・・
・・絶縁基板、２２・・・・・・凹部、２３・・・・・
・通電電極、２４・・・・・・導電接続部、２５・・・
・・・導体、２６・・・・・・貫通孔、２７・・・・・
・ろう材。
６−
￥１酉
（し）
ｙｚ侶 警３ツ
（ａ）
（′）γ
第４圀
５７．９．−１
昭和 年 月 １」
特許庁長官 殿
１、事件の表示 昭和５７年 特許 願第１０７４
２６号２、発明の名称 半導体接続保持具
３、補正をする者
事件との関係 出 願 人東京都港区芝五
丁目３３番１号
（４２３） 日本電気株式会社
代表者 関本忠弘
４、代理人
〒１０８ 東京都港区芝Ｉｊ丁目３７番８号 住友三
田ビル５、補正の対槃
明細書の発明の詳細な説明の欄
６、補正の内容
（１）第２軛第１３行乃至第１４行
「体７を設ける。しかる後、上段２、中段３、下段４を
貼合わせる。」とあるのを「体７を設ける。」と補正す
る。
（２）第２頁第２０行
「にろう材１１に結句ける。・・・・・・」とあるのを
「にろう材１１によって貼付ける。・・・・・・」と補
正する。
（３）第３頁第８行乃至第１１行
［た、導線８の接続のために通電電極５の占有面積もあ
る程度の大きさが必要であり、半導体接続保持具１は電
極数が増えれば増える根太とあるのを［た、通電電極５
には導線８の接続を得るための余地が必要であるため、
半導体 ２−
接続保持共１は電極数の増加に伴い必然的に大形化し、
本来の高密度実装化傾向に反するという欠点がめった。
」と補正する。
（４）第４頁第１５行
「・・・・・・通電電極２２と」とめるのを「・・・・
・・通電電極２３と」と補正する。
（５） 第４貞第１６行
［・・・・・・通電電極２２から」とあるのを「・・・
・・・通電電極２３から」と補正する。
（６）第４貞第１６行
「基板２１・・・・・・」とおるのを「絶縁基板２１・
・・・・・」と補正する。
（７）第５頁第１１行
「・・・・・・接続を行なわないから、」とあるのを「
・・・・・・接続のための余地を必要としないから、」
と補正する。
一 ３−FIG. 1 is an exploded perspective view of an example of a conventional semiconductor connection holder, and FIG. 2 is a perspective view of an example of a conventional semiconductor chip.
FIGS. 3(a) and 3(b) are a perspective view and a sectional view of a semiconductor connection holder mounted with a semiconductor chip, and FIGS. 4(a) to (
C) is a top perspective view, a bottom perspective view, and a sectional view of an embodiment of the present invention. 1... Semiconductor connection holder, 2... Upper tier, 3... Middle tier, 4... Lower tier, 5...
... Current-carrying electrode, 6 ... Connection electrode, 7 ...
... Conductor, 8 ... Conductor wire, 9 ... Semiconductor chip, 10 ... Electrode, 11 ... Brazing material, 20 ... Semiconductor Connection holder, 21...
...Insulating substrate, 22...Concavity, 23...
- Current-carrying electrode, 24... Conductive connection part, 25...
...Conductor, 26...Through hole, 27...
- Waxing material. 6- ¥1 rooster (shi) yz monk 3 pieces (a)
(') γ 4th area 57.9. -1 Month 1, 1980” Commissioner of the Patent Office 1, Indication of the case 1981 Patent Application No. 1074
No. 26 No. 2, Title of the invention: Semiconductor connection holder 3, Relationship to the amended person's case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent Sumitomo Mita Building 5, 37-8 Shiba Ij-chome, Minato-ku, Tokyo 108, Detailed explanation of the invention column 6 of the amended specification, Contents of the amendment (1) Second yoke, lines 13 to 14 The phrase "The body 7 is provided. After that, the upper tier 2, the middle tier 3, and the lower tier 4 are pasted together." is corrected to ``The body 7 is provided.'' (2) In the 20th line of the second page, the phrase "It is attached to the soldering material 11....." is corrected to "It is pasted using the soldering material 11." (3) Page 3, lines 8 to 11 [Also, the area occupied by the current-carrying electrode 5 is required to be a certain size in order to connect the conductive wire 8, and the semiconductor connection holder 1 is As the joists increase, the current-carrying electrode 5
requires room for the connection of conductor 8,
Semiconductor 2 - Connection and maintenance 1 inevitably becomes larger as the number of electrodes increases,
The drawback was that it went against the original trend toward high-density packaging. ” he corrected. (4) On page 4, line 15, replace “... with current-carrying electrode 22” with “...
. . and the current-carrying electrode 23." (5) The 16th line of the 4th line [...from the current-carrying electrode 22] has been changed to ``...
. . . from the current-carrying electrode 23." (6) The 4th line, 16th line “Substrate 21...” should be changed to “Insulating substrate 21.
"..." I corrected myself. (7) Page 5, line 11, ``...Because no connection is made,'' was replaced with ``
...because it doesn't require any room for connection.''
and correct it. 1 3-
Claims (1)
た凹部と、搭載される半導体チップの電極の位置に対応
して前記凹部底面に設けられた通電電極と、前記凹部周
囲の前記絶縁基板面に前記通電電極と同数だけ設けられ
た導電接続部と、前記通電電極と前記導電接続部とを一
対一対応で接続する導体配線と前記通電電極から前記絶
縁基板を貫通して四部形成面と反対側の面に達する貫通
孔とを含むことを特徴とする半導体接続保持具。A recess formed in an insulating substrate to a size that can accommodate a semiconductor chip, a current-carrying electrode provided on the bottom surface of the recess corresponding to the position of the electrode of the semiconductor chip to be mounted, and a conductive electrode provided on the surface of the insulating substrate around the recess. A conductive connection part provided in the same number as the current-carrying electrodes, a conductor wiring that connects the current-carrying electrode and the conductive connection part in a one-to-one correspondence, and a side opposite to the four-part forming surface passing through the insulating substrate from the current-carrying electrode. A semiconductor connection holder comprising a through hole reaching the surface of the semiconductor connection holder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10742682A JPS58225654A (en) | 1982-06-22 | 1982-06-22 | Holder combined with connecting semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10742682A JPS58225654A (en) | 1982-06-22 | 1982-06-22 | Holder combined with connecting semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58225654A true JPS58225654A (en) | 1983-12-27 |
Family
ID=14458839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10742682A Pending JPS58225654A (en) | 1982-06-22 | 1982-06-22 | Holder combined with connecting semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58225654A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5099392A (en) * | 1990-04-02 | 1992-03-24 | Hewlett-Packard Company | Tape-automated bonding frame adapter system |
| US5825084A (en) * | 1996-08-22 | 1998-10-20 | Express Packaging Systems, Inc. | Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices |
-
1982
- 1982-06-22 JP JP10742682A patent/JPS58225654A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5099392A (en) * | 1990-04-02 | 1992-03-24 | Hewlett-Packard Company | Tape-automated bonding frame adapter system |
| US5825084A (en) * | 1996-08-22 | 1998-10-20 | Express Packaging Systems, Inc. | Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices |
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