JP2003086734A - Chip stack structure of csp - Google Patents
Chip stack structure of cspInfo
- Publication number
- JP2003086734A JP2003086734A JP2001276246A JP2001276246A JP2003086734A JP 2003086734 A JP2003086734 A JP 2003086734A JP 2001276246 A JP2001276246 A JP 2001276246A JP 2001276246 A JP2001276246 A JP 2001276246A JP 2003086734 A JP2003086734 A JP 2003086734A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- csp
- stack structure
- spot facing
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数のチップが実
装されたＣＳＰのチップスタック構造に属する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CSP chip stack structure in which a plurality of chips are mounted.
【０００２】[0002]
【従来の技術】従来、プリント回路基板への半導体装置
の高密度化に伴い、半導体装置の小型化も進んでおり、
チップサイズにまで小型化された半導体装置が開発され
ている。この小型化された半導体装置はＣｈｉｐ Ｓｉ
ｚｅ Ｐａｃｋａｇｅ（以下、ＣＳＰと称す）と呼ばれ
ている。2. Description of the Related Art Conventionally, as the density of semiconductor devices on printed circuit boards has increased, miniaturization of semiconductor devices has also been advanced.
Semiconductor devices downsized to the chip size have been developed. This miniaturized semiconductor device is Chip Si
It is called ze Package (hereinafter referred to as CSP).
【０００３】図２は、従来技術におけるＣＳＰのチップ
スタック構造の一例を示す図である。FIG. 2 is a diagram showing an example of a conventional CSP chip stack structure.
【０００４】ＣＳＰ内部のチップを重ねて実装（スタッ
ク実装）する際に、主に図２に示すように、下側に形状
の大きなチップ１０２を配置し、その上にそれよりも形
状が小さなチップ１０１を載せワイヤーボンディング１
０３等でインターポーザ１０４と呼ばれる基板に接続さ
れる。When the chips inside the CSP are stacked and mounted (stack mounting), as shown in FIG. 2, a large chip 102 is arranged on the lower side, and a smaller chip is formed on the chip 102. Mount 101 and wire bonding 1
03 and the like are connected to a substrate called an interposer 104.
【０００５】特開平１１−２０４７２０号公報には、表
面に所望の回路が形成されたウエハーの裏面に熱圧着シ
ートを貼り付け、ダイシングすることにより形成された
半導体チップに関して、配線層が形成され、且つ、裏面
に貫通孔を通して配線層と電気的に接続された実装用外
部端子を有する絶縁性基板に、回路形成面を上にして搭
載され、半導体チップの回路形成面上に、表面に回路形
成されたウエハーの裏面に熱圧着シートを貼り付け、ダ
イシングすることにより形成された半導体チップが搭載
され、２つの半導体チップと配線層の電極部とがワイヤ
ーを用いて接続され、２つの半導体チップ及びワイヤー
が樹脂封止される技術が公開されている。In Japanese Unexamined Patent Publication No. 11-204720, a wiring layer is formed on a semiconductor chip formed by attaching a thermocompression bonding sheet to the back surface of a wafer having a desired circuit formed on the front surface and dicing it. Also, the circuit forming surface is mounted on an insulating substrate having a mounting external terminal electrically connected to the wiring layer through the through hole on the back surface, and the circuit is formed on the surface on the circuit forming surface of the semiconductor chip. A semiconductor chip formed by pasting a thermocompression-bonding sheet on the back surface of the formed wafer and dicing is mounted, the two semiconductor chips and the electrode portion of the wiring layer are connected by a wire, and the two semiconductor chips and A technique for resin-sealing a wire has been disclosed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来技
術には以下に掲げる問題点があった。However, the prior art has the following problems.
【０００７】このような場合、チップを重ねるためにＣ
ＳＰ全体の厚みが厚くなる問題が発生した。また、ＣＳ
Ｐの厚みを薄くしようとした時に、ウエハーの厚み自体
を薄くする手段が用いられるが、８インチ程度の直径が
ある薄いウエハーの取り扱いを考慮する必要がある。ス
タック時の厚みを薄くする手段として具体的には、ＬＳ
Ｉチップの厚みを薄くする手段が採用され、従来は３５
０μｍ程度あった厚みが最近では１００μｍ以下になろ
うとしている。このような条件において、８インチ程度
の直径がある薄いウエハーの取り扱いが非常に難しくな
るという問題点があった。In such a case, in order to stack the chips, C
There was a problem that the thickness of the entire SP became thick. Also, CS
When attempting to reduce the thickness of P, a means for reducing the thickness of the wafer itself is used, but it is necessary to consider handling a thin wafer having a diameter of about 8 inches. Specifically, as a means for reducing the thickness at the time of stacking, LS
Means to reduce the thickness of the I-chip are adopted
Recently, the thickness of about 0 μm is about to be 100 μm or less. Under such a condition, there is a problem that it becomes very difficult to handle a thin wafer having a diameter of about 8 inches.
【０００８】本発明は斯かる問題点を鑑みてなされたも
のであり、その目的とするところは、ＣＳＰ内部のチッ
プについて、一方のチップの裏面から座グリを設け、他
のチップを座グリの凹部の内側に配置することで、ＣＳ
Ｐの強度を損ねることなく、ウエハーの強度を維持しな
がらチップをスタック実装した後の厚みを抑えることの
できるＣＳＰのチップスタック構造に関する技術を提供
する点にある。The present invention has been made in view of the above problems, and an object of the present invention is to provide a chip inside a CSP with a spot facing from the back surface of one chip and a spot facing the other chip. By arranging inside the recess, CS
It is an object of the present invention to provide a technique relating to a CSP chip stack structure capable of suppressing the thickness of chips after stacking them while maintaining the strength of a wafer without deteriorating the strength of P.
【０００９】[0009]
【課題を解決するための手段】請求項１記載の本発明の
要旨は、複数のチップが実装されたＣＳＰのチップスタ
ック構造であって、前記ＣＳＰに実装される第１のチッ
プと、底面側から座グリ部が設けられた第２のチップと
を備え、前記第１のチップは、前記第２のチップに設け
られた座グリ部の凹部の内側に配置されることを特徴と
するＣＳＰのチップスタック構造に存する。請求項２記
載の本発明の要旨は、前記第１のチップの天面は、前記
座グリ部の凹部における天井部を鉛直方向に下方から支
えることを特徴とする請求項１に記載のＣＳＰのチップ
スタック構造に存する。請求項３記載の本発明の要旨
は、前記第１のチップの天面は、直接、又は、緩衝材な
どを介して、前記座グリ部の凹部における天井部を鉛直
方向に下方から支えることを特徴とする請求項１又は２
に記載のＣＳＰのチップスタック構造に存する。請求項
４記載の本発明の要旨は、複数のチップが実装されたＣ
ＳＰのチップスタック構造の構成方法であって、前記Ｃ
ＳＰ内部の第１のチップ及び第２のチップを重ねる際
に、前記第１のチップをインターポーザ上に異方性導電
フィルムなどを用いて接続を行う第１の工程と、前記第
１のチップの上から、底面側に座グリ部を設けた第２の
チップを、前記第１のチップを前記座グリ部の凹部で覆
うように配置する第２の工程と、前記第２のチップと前
記インターポーザとの接続を、ワイヤーボンディングを
用いて行う第３の工程とを備えることを特徴とするＣＳ
Ｐのチップスタック構造の構成方法に存する。請求項５
記載の本発明の要旨は、前記第２の工程は、前記座グリ
部の凹部における天井部を、前記第１のチップの天面
で、鉛直方向に下方から支える工程を含むことを特徴と
する請求項４に記載のＣＳＰのチップスタック構造の構
成方法に存する。請求項６記載の本発明の要旨は、請求
項１乃至３のいずれかに記載のＣＳＰのチップスタック
構造を有することを特徴とする半導体装置に存する。The gist of the present invention according to claim 1 is a chip stack structure of a CSP in which a plurality of chips are mounted, the first chip mounted in the CSP, and a bottom surface side. And a second chip provided with a counterbore part, wherein the first chip is arranged inside a recess of the counterbore part provided in the second chip. It exists in the chip stack structure. The gist of the present invention according to claim 2 is that the top surface of the first chip supports the ceiling portion of the recess of the spot facing portion from below in the vertical direction. It exists in the chip stack structure. The gist of the present invention according to claim 3 is that the top surface of the first chip supports the ceiling portion of the recess of the spot facing portion from below in the vertical direction directly or via a cushioning material. Claim 1 or 2 characterized
The chip stack structure of the CSP described in 1. The gist of the present invention as set forth in claim 4 is a C in which a plurality of chips are mounted.
A method of constructing a chip stack structure of an SP, comprising:
A first step of connecting the first chip and the second chip inside the SP on the interposer using an anisotropic conductive film or the like when stacking the first chip and the second chip; and A second step of arranging a second chip having a spot facing portion on the bottom surface side from above so as to cover the first chip with a recess of the spot facing portion; the second chip and the interposer; And a third step of connecting with the wire using wire bonding.
It exists in the method of constructing the P chip stack structure. Claim 5
The gist of the present invention described is characterized in that the second step includes a step of vertically supporting the ceiling portion of the recess of the spot facing portion from below from the top surface of the first chip. A method of configuring a chip stack structure of a CSP according to claim 4 exists. A sixth aspect of the present invention resides in a semiconductor device having the CSP chip stack structure according to any one of the first to third aspects.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１１】図１は、本実施の形態に係るＣＳＰのチッ
プスタック構造の概略を示す図である。FIG. 1 is a diagram showing an outline of a chip stack structure of a CSP according to this embodiment.
【００１２】図１に示すように、本実施の形態に係るＣ
ＳＰのチップスタック構造におけるＣＳＰ１Ａは、チッ
プ（第１のチップ）１と座グリ部１２が設けられたチッ
プ（第２のチップ）２とワイヤーボンディング３とイン
ターポーザ４とで概略構成され、チップ１は座グリ部１
２の内部に配置される。As shown in FIG. 1, C according to the present embodiment.
The CSP 1A in the chip stack structure of the SP is roughly configured by a chip (first chip) 1, a chip (second chip) 2 provided with a spot facing portion 12, a wire bonding 3 and an interposer 4, and the chip 1 is Counterbore part 1
It is placed inside 2.
【００１３】ＣＳＰ１Ａの実装面積の削減を考慮した場
合ＣＳＰ１Ａ内部に複数（２個）のチップを重ねて実装
（スタック実装）する。これらのチップを重ねて配置す
る際に、チップを重ねても厚み方向が増大しないよう
に、図１の如く一方のチップ２の底面側１０から座グリ
部１２を設けて、他方のチップ１を座グリ部１２の凹部
の内側に配置する。Considering the reduction of the mounting area of the CSP 1A, a plurality of (two) chips are stacked and mounted (stack mounting) inside the CSP 1A. When stacking these chips, a counterbore portion 12 is provided from the bottom surface side 10 of one chip 2 as shown in FIG. 1 so that the thickness direction does not increase even if the chips are stacked, and the other chip 1 is attached. It is arranged inside the concave portion of the spot facing portion 12.
【００１４】また、チップ１の天面１５は、チップ２に
設けられた座グリ部１２の凹部における天井部２７を鉛
直方向に下方から支える構造となっている。図中に、ワ
イヤーボンディング３とインターポーザ４とを示す。The top surface 15 of the chip 1 has a structure in which the ceiling portion 27 in the recess of the spot facing portion 12 provided on the chip 2 is vertically supported from below. The wire bonding 3 and the interposer 4 are shown in the figure.
【００１５】次に、図１のＣＳＰ１Ａを配置する動作を
説明する。Next, the operation of arranging the CSP 1A of FIG. 1 will be described.
【００１６】ＣＳＰ１Ａを構成する際に、強度を損なわ
ずＣＳＰ１Ａの実装面積を削減するために複数のチップ
（本実施の形態においてはチップ１及びチップ２）を重
ねて配置する。When the CSP 1A is constructed, a plurality of chips (chip 1 and chip 2 in this embodiment) are arranged in an overlapping manner in order to reduce the mounting area of the CSP 1A without impairing the strength.
【００１７】図１のようにＣＳＰ１Ａ内部のチップ１及
びチップ２を重ねる際に、形状の小さなチップ１をイン
ターポーザ４と呼ばれる基板上に異方性導電フィルム等
を用いて接続を行う。チップ１の上から、底面側１０に
座グリ部１２を設けた形状の大きなチップ２を、形状の
小さなチップ１を覆うように配置し、チップ２とインタ
ーポーザ４との接続はワイヤーボンディング３を用いて
行う。When the chip 1 and the chip 2 inside the CSP 1A are stacked as shown in FIG. 1, the chip 1 having a small shape is connected to a substrate called an interposer 4 by using an anisotropic conductive film or the like. From the top of the chip 1, a large chip 2 having a spot facing portion 12 on the bottom surface 10 is arranged so as to cover the small chip 1, and the wire bonding 3 is used to connect the chip 2 and the interposer 4. Do it.
【００１８】チップ２の強度を保持するために、チップ
１の天面１５は、直接、又は、緩衝材などを介して、チ
ップ２に設けられた座グリ部１２の凹部における天井部
２７を鉛直方向に下方から支える。In order to maintain the strength of the chip 2, the top surface 15 of the chip 1 is vertically or directly on the ceiling 27 in the recess of the counterbore 12 provided on the chip 2, either directly or through a cushioning material. Support from below.
【００１９】実施の形態に係るＣＳＰのチップスタック
構造は上記の如く構成されているので、以下に掲げる効
果を奏する。Since the chip stack structure of the CSP according to the embodiment is configured as described above, it has the following effects.
【００２０】チップ１の上から、座グリ部１２を設けた
チップ２をチップ１を覆うように配置することで、ＣＳ
Ｐ１Ａの厚みを薄くできる。また、ＣＳＰ１Ａの外周の
ボンディング用ＰＡＤ面積が削減でき、形状を小型にで
きる。更に、ウエハーを薄くする必要がないため、通常
のウエハーの取り扱いができる。By disposing the chip 2 provided with the spot facing portion 12 from above the chip 1 so as to cover the chip 1, the CS
The thickness of P1A can be reduced. Further, the bonding PAD area on the outer periphery of the CSP 1A can be reduced, and the shape can be reduced. Furthermore, since it is not necessary to thin the wafer, normal wafer handling can be performed.
【００２１】なお、本実施の形態においては、２個のチ
ップを重ねる例で説明したが、３個以上のチップを重ね
る場合にも適用可能である。また、本実施の形態におい
ては、本発明はそれに限定されず、本発明を適用する上
で好適なＣＳＰのチップスタック構造に適用することが
できる。In the present embodiment, an example in which two chips are stacked has been described, but it is also applicable to a case where three or more chips are stacked. Further, in the present embodiment, the present invention is not limited thereto, and can be applied to a CSP chip stack structure suitable for applying the present invention.
【００２２】また、上記構成部材の数、位置、形状等は
上記実施の形態に限定されず、本発明を実施する上で好
適な数、位置、形状等にすることができる。Further, the number, position, shape, etc. of the above-mentioned constituent members are not limited to those in the above-mentioned embodiment, and any number, position, shape, etc. suitable for carrying out the present invention can be adopted.
【００２３】なお、各図において、同一構成要素には同
一符号を付している。In each figure, the same components are designated by the same reference numerals.
【００２４】[0024]
【発明の効果】本発明は以上のように構成されているの
で、以下に掲げる効果を奏する。Since the present invention is configured as described above, it has the following effects.
【００２５】第１の効果は、ＣＳＰを重ねる際に、強度
を損ねることなく、厚みを薄くできることである。The first effect is that when the CSPs are stacked, the thickness can be reduced without impairing the strength.
【００２６】第２の効果は、ＣＳＰの外周のボンディン
グ用ＰＡＤ面積が削減でき、形状を小型にできることで
ある。The second effect is that the bonding PAD area on the outer periphery of the CSP can be reduced and the shape can be reduced.
【００２７】第３の効果は、ウエハーを薄くする必要が
ないため、通常のウエハーの取り扱いが可能である。The third effect is that since it is not necessary to thin the wafer, it is possible to handle the wafer normally.
【図１】本発明の実施の形態に係るＣＳＰのチップスタ
ック構造の概略を示す図である。FIG. 1 is a diagram schematically showing a chip stack structure of a CSP according to an embodiment of the present invention.
【図２】従来技術におけるＣＳＰのチップスタック構造
の一例を示す図である。FIG. 2 is a diagram showing an example of a CSP chip stack structure in a conventional technique.
１ チップ（第１のチップ） １Ａ ＣＳＰ ２ チップ（第２のチップ） ３ ワイヤーボンディング ４ インターポーザ １０ 底面側 １２ 座グリ部 １５ 天面 ２７ 天井部 １０１ チップ １０２ チップ １０３ ワイヤーボンディング １０４ インターポーザ 1 chip (1st chip) 1A CSP 2 chips (2nd chip) 3 wire bonding 4 Interposer 10 Bottom side 12 counterbore part 15 Top 27 Ceiling 101 chips 102 chips 103 wire bonding 104 Interposer
Claims (6)
プスタック構造であって、 前記ＣＳＰに実装される第１のチップと、底面側から座
グリ部が設けられた第２のチップとを備え、 前記第１のチップは、前記第２のチップに設けられた座
グリ部の凹部の内側に配置されることを特徴とするＣＳ
Ｐのチップスタック構造。1. A chip stack structure of a CSP having a plurality of chips mounted thereon, comprising: a first chip mounted on the CSP; and a second chip provided with a spot facing portion from the bottom surface side. The CS is characterized in that the first chip is arranged inside a recess of a spot facing provided on the second chip.
P chip stack structure.
部の凹部における天井部を鉛直方向に下方から支えるこ
とを特徴とする請求項１に記載のＣＳＰのチップスタッ
ク構造。2. The chip stack structure of the CSP according to claim 1, wherein the top surface of the first chip supports a ceiling portion of the recess of the spot facing portion in the vertical direction from below.
は、緩衝材などを介して、前記座グリ部の凹部における
天井部を鉛直方向に下方から支えることを特徴とする請
求項１又は２に記載のＣＳＰのチップスタック構造。3. The top surface of the first chip supports the ceiling portion of the recess of the spot facing portion from below in the vertical direction directly or via a cushioning material or the like. Alternatively, the CSP chip stack structure according to Item 2.
プスタック構造の構成方法であって、 前記ＣＳＰ内部の第１のチップ及び第２のチップを重ね
る際に、前記第１のチップをインターポーザ上に異方性
導電フィルムなどを用いて接続を行う第１の工程と、 前記第１のチップの上から、底面側に座グリ部を設けた
第２のチップを、前記第１のチップを前記座グリ部の凹
部で覆うように配置する第２の工程と、 前記第２のチップと前記インターポーザとの接続を、ワ
イヤーボンディングを用いて行う第３の工程とを備える
ことを特徴とするＣＳＰのチップスタック構造の構成方
法。4. A method of constructing a chip stack structure of a CSP in which a plurality of chips are mounted, wherein the first chip is placed on an interposer when the first chip and the second chip inside the CSP are stacked. A first step of connecting using an anisotropic conductive film or the like, and a second chip provided with a spot facing portion on the bottom surface side from above the first chip, the first chip A CSP, comprising: a second step of arranging so as to cover the recessed portion of the spot facing portion; and a third step of connecting the second chip and the interposer by wire bonding. How to construct a chip stack structure.
における天井部を、前記第１のチップの天面で、鉛直方
向に下方から支える工程を含むことを特徴とする請求項
４に記載のＣＳＰのチップスタック構造の構成方法。5. The second step includes a step of vertically supporting a ceiling portion of the recessed portion of the spot facing portion from below in a vertical direction on a top surface of the first chip. 5. A method of configuring a chip stack structure of CSP described in 1.
Ｐのチップスタック構造を有することを特徴とする半導
体装置。6. The CS according to any one of claims 1 to 3.
A semiconductor device having a P chip stack structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001276246A JP2003086734A (en) | 2001-09-12 | 2001-09-12 | Chip stack structure of csp |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001276246A JP2003086734A (en) | 2001-09-12 | 2001-09-12 | Chip stack structure of csp |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003086734A true JP2003086734A (en) | 2003-03-20 |
Family
ID=19100977
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|---|---|---|---|
| JP2001276246A Pending JP2003086734A (en) | 2001-09-12 | 2001-09-12 | Chip stack structure of csp |
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| Country | Link |
|---|---|
| JP (1) | JP2003086734A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203776A (en) * | 2004-01-13 | 2005-07-28 | Samsung Electronics Co Ltd | Multichip package, semiconductor device used for the same, and manufacturing method thereof |
| JP2006179607A (en) * | 2004-12-21 | 2006-07-06 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| CN1306606C (en) * | 2003-04-02 | 2007-03-21 | 纬创资通股份有限公司 | Manufacturing method of heat radiation fin |
| JP2009229349A (en) * | 2008-03-25 | 2009-10-08 | Oki Semiconductor Co Ltd | Acceleration sensor package |
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|---|---|---|---|---|
| JPH0555454A (en) * | 1991-08-22 | 1993-03-05 | Honda Motor Co Ltd | Semiconductor device and its manufacture |
| JP2000299431A (en) * | 1999-04-14 | 2000-10-24 | Sharp Corp | Semiconductor device and its manufacture |
-
2001
- 2001-09-12 JP JP2001276246A patent/JP2003086734A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555454A (en) * | 1991-08-22 | 1993-03-05 | Honda Motor Co Ltd | Semiconductor device and its manufacture |
| JP2000299431A (en) * | 1999-04-14 | 2000-10-24 | Sharp Corp | Semiconductor device and its manufacture |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306606C (en) * | 2003-04-02 | 2007-03-21 | 纬创资通股份有限公司 | Manufacturing method of heat radiation fin |
| JP2005203776A (en) * | 2004-01-13 | 2005-07-28 | Samsung Electronics Co Ltd | Multichip package, semiconductor device used for the same, and manufacturing method thereof |
| JP2006179607A (en) * | 2004-12-21 | 2006-07-06 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP4553720B2 (en) * | 2004-12-21 | 2010-09-29 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2009229349A (en) * | 2008-03-25 | 2009-10-08 | Oki Semiconductor Co Ltd | Acceleration sensor package |
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