JPS58225653A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58225653A
JPS58225653A JP10890282A JP10890282A JPS58225653A JP S58225653 A JPS58225653 A JP S58225653A JP 10890282 A JP10890282 A JP 10890282A JP 10890282 A JP10890282 A JP 10890282A JP S58225653 A JPS58225653 A JP S58225653A
Authority
JP
Japan
Prior art keywords
oxide film
phosphorus
film
layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10890282A
Other languages
Japanese (ja)
Inventor
Hiroshige Takahashi
高橋 広成
Hirokazu Miyoshi
三好 寛和
Akira Nishimoto
西本 章
Akira Ando
安東 亮
Moriyoshi Nakajima
盛義 中島
Masaharu Tokuda
徳田 正治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10890282A priority Critical patent/JPS58225653A/en
Publication of JPS58225653A publication Critical patent/JPS58225653A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To reduce influence of polarization due to phosphorus and obtain a device with less fluctuation of threshold value by stacking an oxide film including phosphorus on an oxide film not including impurity. CONSTITUTION:A non-volatile memory device is formed by the conventional method, and an oxide film 10 including phosphorus in the thickness of about 2,000Angstrom is stacked on an oxide film 9 not including impurity in the thickness of about 6,000Angstrom . Therefore, in the case of a non-volatile memory device in the double electrode structure, the film 9 exists even when the phosphorus within the film 10 is poralized, electric field intensity is weakened due to film thickness and thereby influence of electric field due to poralization is reduced. Accordingly, fluctuation of threshold voltage of the element itself can be reduced almost to zero, thereby stabilizing the function and improviding performance of semiconductor device.

Description

【発明の詳細な説明】 この発明は半導体装置に関し、特に素子部分と配線部分
とを分離する層間絶縁膜の改良に係わるものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an improvement in an interlayer insulating film that separates an element portion from a wiring portion.

従来例による半導体装置として、二重電極構造管もつ不
揮発性メモリ装置の概要構成を第1図に示しである。こ
の第1図において、符号(1)ハ半導体基板上の素子間
分離のための厚いフィールド酸化膜、(2)はソース、
ドレイン拡散層、(3)は両拡散層間の基板上に形成さ
れた第1ゲート酸化膜、(4)はこの酸化膜上にあって
浮遊ゲートとなる第1多結晶シリコン層、(5)it、
このシリコン層上に形成された第2ゲート酸化膜、(6
)はこの酸化膜上にあって制御電極となる第2多結晶シ
リコン層、(1)はこrらの上を覆う薄い酸化膜、(8
)は層間絶縁膜としての気相成長で生成されたリンを含
む酸化膜である0 この従来構成にあっては、第1多結晶シリコン層(4)
に電子を注入することにより、メモリ素子としてのMO
8型トランジスタのしきい値電圧を変化させ、このしき
い値電圧の違いを利用してデータ記憶を行なう工うにし
ている。この場合、層間絶縁膜としての酸化膜(8)は
素子上に形成される図示省略した配線部分との絶縁をな
しており、この酸化膜(8)は気相成長法に↓つて生成
された段階では、基板上の素子表面の起伏に応じ、その
表面状態もまた起伏の多いものとなっているが、このリ
ンを含む酸化膜(8)はHz / Ot  雰囲気中で
の高温熱処理により、いわゆるだれを生じて表面全体が
平坦化され、その上に形成さね、るアルミニウムなどに
よる配線の表面起伏に基づく断線を防止するのである。
As a conventional semiconductor device, a schematic configuration of a nonvolatile memory device having a double electrode structure tube is shown in FIG. In FIG. 1, (1) C is a thick field oxide film for isolation between elements on the semiconductor substrate, (2) is a source,
a drain diffusion layer, (3) a first gate oxide film formed on the substrate between both diffusion layers, (4) a first polycrystalline silicon layer on this oxide film and serving as a floating gate, (5) it ,
A second gate oxide film (6
) is the second polycrystalline silicon layer on this oxide film and serves as a control electrode, (1) is a thin oxide film covering these, (8
) is an oxide film containing phosphorus produced by vapor phase growth as an interlayer insulating film.0 In this conventional structure, the first polycrystalline silicon layer (4)
MO as a memory element by injecting electrons into
The threshold voltage of the 8-type transistor is changed, and this difference in threshold voltage is used to store data. In this case, the oxide film (8) as an interlayer insulating film insulates the wiring portion (not shown) formed on the element, and this oxide film (8) is produced by vapor phase growth. At this stage, the surface condition is also uneven according to the undulations of the element surface on the substrate, but this phosphorous-containing oxide film (8) undergoes a high-temperature heat treatment in an Hz/Ot atmosphere, resulting in a so-called The entire surface is flattened by the drooping, thereby preventing wire breakage due to surface undulations of the wiring formed on top of the aluminum or the like.

しかし乍らこのような層間絶縁膜を二重電極構造の不揮
発性メモリ装置に適用すると、リンを含む酸化膜中のリ
ンの分極によってメモリ素子のしきい値電圧がばらつく
不都合があった。
However, when such an interlayer insulating film is applied to a nonvolatile memory device having a double electrode structure, there is a problem in that the threshold voltage of the memory element varies due to the polarization of phosphorus in the phosphorus-containing oxide film.

この発明は従来のこのような欠点に鑑み、層間絶縁膜を
不純物を含−1ない下層酸化膜とリンを含む上層酸化膜
との2層構造として、リンによる分極の影響を少なくシ
、シきい値電圧のばらつきのない半導体装置全提供する
ものである。
In view of these conventional drawbacks, the present invention provides an interlayer insulating film with a two-layer structure consisting of a lower oxide film containing no impurities and an upper oxide film containing phosphorus, thereby reducing the influence of polarization caused by phosphorus. The present invention provides a semiconductor device with no variation in voltage value.

以下、この発明に係わる半導体装置の一実施例につ含、
第2図を参照して説明する。
Hereinafter, one embodiment of the semiconductor device according to the present invention will be described.
This will be explained with reference to FIG.

この実施例は前記従来例と同様に二重電極構造をもつ不
揮発性メモリ装置に適用した場合であって、図中、同−
省号は同一または相当部分を示しており、この実施例で
は前記層間絶縁膜としての酸化膜(8)に変えて、下部
の第1層をシラン(Sic&)ガス、および酸素(Oz
 )ガス雰囲気下に、温度T=430℃で気相成長法に
より生成させた厚さ約600OAの酸化膜(9)とし、
その上部の第2層をシラン(5IH4)ガス、酸素(O
x )ガス、お↓びホスフィン(PHs)ガス雰囲気下
に、温度T−430℃で同様に気相成長法により生成さ
せた厚さ約200OAの酸化膜(10)としてなる2層
にしkものである。
This embodiment is applied to a non-volatile memory device having a double electrode structure similar to the conventional example, and is shown in FIG.
The names indicate the same or equivalent parts, and in this example, instead of using the oxide film (8) as the interlayer insulating film, the first layer at the bottom is made of silane (Sic&) gas and oxygen (Oz).
) An oxide film (9) with a thickness of about 600 OA was produced by a vapor phase growth method at a temperature T = 430° C. in a gas atmosphere,
The second layer on top of the silane (5IH4) gas, oxygen (O
x) A two-layer oxide film (10) with a thickness of about 200 OA was produced in a similar manner by vapor phase growth at a temperature of T-430°C in a phosphine (PHs) gas atmosphere. be.

従ってこの実施例においては、そn、ぞnに気相成長法
によって形成さj、た、膜厚的6000Aの不純物を含
まない第1層酸化膜(9)と、膜厚的2000Aのリン
を含む第2層酸化膜(10)との2層構造に、rる層間
絶縁膜としたから、こ11.を二重電極構造の不揮発性
メモリ装置に適用した場合、第2層酸化膜(10)内の
リンが分極しても、不純物を含まない第1層酸化膜(9
)の在任にエフ、しがも間膜(9)が比較的Jvいため
に電界強度が弱くなって、分極による電界の影響を少な
くシ、かつこれに工っで素子自体のしきい値電圧のばら
つき全殆んどなく一、−c、=ヵt −c’ @ 6゜
アあう。         1なお前記実施例は二重電
極構造を有する不揮発性メモリ装置に適用した場合につ
いて述べたが、浮遊ゲートお工び何らかのトラップによ
り電荷を蓄積させてメモリ装置とする場合にも適用でき
ることは勿論であり、またこのような電荷の蓄積を利用
したメモリ装置以外にも、任意型式の半導体メモリ装置
に適用して、2層々間絶縁膜の効果を期待し得るもので
ある。
Therefore, in this example, the first layer oxide film (9), which does not contain impurities and has a thickness of 6000 Å, is formed by vapor phase epitaxy, and the phosphorus oxide film has a thickness of 2000 Å. This 11. When applied to a nonvolatile memory device with a double electrode structure, even if phosphorus in the second layer oxide film (10) is polarized, the first layer oxide film (9) containing no impurities
), the electric field strength is weakened because the membrane (9) is relatively Jv, which reduces the influence of the electric field due to polarization, and by working on this, the threshold voltage of the element itself is reduced. There is almost no variation at all, 1, -c, = cat -c' @ 6°a. 1. Although the above embodiment has been described for the case where it is applied to a non-volatile memory device having a double electrode structure, it goes without saying that it can also be applied to a memory device in which charge is accumulated using a floating gate or some kind of trap. In addition to memory devices that utilize such charge accumulation, the present invention can be applied to any type of semiconductor memory device, and the effect of the two-layer insulating film can be expected.

以上詳述したようにこの発明に工i、げ、層間絶縁膜を
有する半導体装置にあって、この層間絶縁膜を下部第1
層の不純物を含まない酸化膜と、上部第2層のリンを含
む酸化膜との2層構造と【2て、リンの分極による装置
機能への影響を排除したから、簡単かつ実施容易な構成
であるにも拘らず、装置機能の安定性、ならびに特性向
上に寄与するところが大きいものである。
As described in detail above, the present invention provides a semiconductor device having an interlayer insulating film.
The two-layer structure consists of an oxide film that does not contain impurities, and an oxide film that contains phosphorus as the second upper layer [2] The structure is simple and easy to implement because it eliminates the influence of phosphorus polarization on the device function. Despite this, it greatly contributes to the stability of device functions and improvement of characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例による二重電極構造の不揮発性メモリ装
置の概要構成を示す断面図、第2図はこの発明の一実施
例を二重電極構造の不揮発性メモリ装置に適用した場合
の概要構成を示す断面図である。 (1)・・・・フィールド酸化膜、(2)・・・・ソー
ス、ドレイン拡散層、(3)・・・・第1ゲート酸化膜
、(4)・・・・第1多結晶シリコン層、(5)・・・
・第2ゲート酸化膜、(6)・・・・第2多結晶シリコ
y4、(7)・・・・酸化膜、(9)お↓び(10)・
・・・不純物を含まない第1層、およびリンを含む第2
層酸化膜(層間絶縁膜)。 代理人 葛 野 信 −
FIG. 1 is a sectional view showing the general configuration of a conventional nonvolatile memory device with a double electrode structure, and FIG. 2 is an overview of an embodiment of the present invention applied to a nonvolatile memory device with a double electrode structure. FIG. 3 is a sectional view showing the configuration. (1)...Field oxide film, (2)...Source and drain diffusion layer, (3)...First gate oxide film, (4)...First polycrystalline silicon layer , (5)...
・Second gate oxide film, (6)...second polycrystalline silicon y4, (7)...oxide film, (9) and (10)・
...The first layer does not contain impurities, and the second layer contains phosphorus.
Layer oxide film (interlayer insulation film). Agent Shin Kuzuno −

Claims (1)

【特許請求の範囲】[Claims] 素子部分と配線部分とを気相成長により生成される眉間
絶縁層にエリ分離した構造の半導体装置において、前記
層間絶縁層を2層構造とし、下部第1層を不純物を含ま
ない酸化膜、その上部第2層をリンを含む酸化膜から構
成したことを特徴とする半導体装置。
In a semiconductor device having a structure in which an element part and a wiring part are separated by a glabellar insulating layer produced by vapor phase growth, the interlayer insulating layer has a two-layer structure, and the lower first layer is an oxide film containing no impurities, and an oxide film containing no impurities. A semiconductor device characterized in that the upper second layer is made of an oxide film containing phosphorus.
JP10890282A 1982-06-22 1982-06-22 Semiconductor device Pending JPS58225653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10890282A JPS58225653A (en) 1982-06-22 1982-06-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10890282A JPS58225653A (en) 1982-06-22 1982-06-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58225653A true JPS58225653A (en) 1983-12-27

Family

ID=14496520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10890282A Pending JPS58225653A (en) 1982-06-22 1982-06-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58225653A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845177A (en) * 1971-10-12 1973-06-28
JPS5247689A (en) * 1975-10-15 1977-04-15 Toshiba Corp Process for production of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845177A (en) * 1971-10-12 1973-06-28
JPS5247689A (en) * 1975-10-15 1977-04-15 Toshiba Corp Process for production of semiconductor device

Similar Documents

Publication Publication Date Title
US5442223A (en) Semiconductor device with stress relief
US5063431A (en) Semiconductor device having a two-layer gate structure
US5378905A (en) Ferroelectric field effect transistor with fluoride buffer and IV-VI ferroelectric
JPH0465548B2 (en)
JPS583380B2 (en) Semiconductor device and its manufacturing method
KR920013709A (en) Nonvolatile semiconductor memory device and manufacturing method thereof
JPH0640582B2 (en) Method for manufacturing insulating gate field effect transistor
US4542400A (en) Semiconductor device with multi-layered structure
JP3071302B2 (en) Method for manufacturing semiconductor device
US5821560A (en) Thin film transistor for controlling a device such as a liquid crystal cell or electroluminescent element
US5001527A (en) Semiconductor device with thin insulation film
KR950012749A (en) Semiconductor device and manufacturing method
US5237196A (en) Semiconductor device and method for manufacturing the same
JPH04326766A (en) Thin film transistor for liquid crystal and its method of manufacturing
US6146963A (en) Methods for forming ferroelectric capacitors having a bottom electrode with decreased leakage current
JPH07183409A (en) Semiconductor device and manufacture thereof
JPS58225653A (en) Semiconductor device
JPH09167807A (en) Semiconductor device and its manufacture
JP2538830B2 (en) A method for partial oxidation of silicon using a ceramic barrier layer.
JPS5978576A (en) Semiconductor device and manufacture thereof
JPH05129630A (en) Production of nonvolatile semiconductor storage device
JP3232661B2 (en) Semiconductor storage device
JP2612098B2 (en) Manufacturing method of insulating film
JPH01192157A (en) Semiconductor device
JPS6196748A (en) Dielectric isolated substrate and manufacture thereof