JPS58222411A - Device for correcting error - Google Patents

Abstract

PURPOSE:To correct effectively errors without lowering the packing density when the number of block data which is omitted and contains errors is in the range of error correctable number, by correcting said block data by using the syndrome of the line or row. CONSTITUTION:Since each row of the 1st-3rd rows is short of the block data by one, each of the block data omitted from the 1st-3rd rows is replaced with a syndrome at a data replacing and correcting circuit 9 based on the detected output of the output terminal 8a of an omitted block detecting circuit 8. Furthermore, erroneous block data is present in the 2nd row and the syndrome is not the original block data, an error flag signal ''1'' is produced for this block data at an error flag controlling circuit 15 and the syndrome is supplied to a data modifying circuit 16 together with the error flag signal ''1'' and modified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction device suitable for application to a digital recording/reproducing device such as a digital VTR.

A digital VTR has a tape guide drum with one or more rotating magnetic heads, and the rotating magnetic heads pass digital information signals, that is, digital video signals and/or digital audio signals, as shown in FIG. Data is recorded on the magnetic tape TP so as to form a tilted magnetic trunk T, and it is also reproduced. In the case of a digital video signal, one field or a plurality of fields thereof are recorded on one magnetic trunk T.

By the way, during reproduction, the digital information signal of the portion st at the beginning of ab of the rotating magnetic head of the magnetic trunk T is often missing. Such a loss of digital information signal is
No negative impact on error correction. In order to solve this problem, conventionally, a warning signal that does not include digital information is recorded in the first part st of the magnetic truss T. However, this is undesirable because it reduces the recording density of information.

In view of this, the present invention provides a method for reproducing digital information signals recorded on a recording medium such as a magnetic tape, so that even if a signal is missing at the beginning of reproduction, error correction will not be adversely affected. First, we would like to propose an error correction device that does not involve a decrease in information storage density.

The error correction device according to the present invention supplies a digital information signal consisting of block data with an absolute address and block parity reproduced from a recording medium, and corrects the data in a matrix arrangement for each block of the digital information signal. error correction possibility determining means for determining whether the number of block data and block parities with missing rows or columns and errors is less than the number that can be corrected; and a matrix form of the digital information signal for each block. When the number of block data with missing or erroneous rows or columns in the arrangement and the number of block parities is less than the number that can be corrected, the block data with the missing or error is processed using the syndrome of that row or column. The data correction circuit to correct (correct or reproduce) and the number of missing rows or columns in the matrix arrangement of digital information signals for each block, block data with errors, and block parity exceed the number that can be corrected. The data correction circuit sometimes corrects missing or erroneous block data.

The digital information signal recorded on one magnetic track T in FIG. 1 is, for example, 102 CRC (
Cyclic redundancy check) Block data I) i, t, Dl, 2,..., Dl, 6,...
, D2,1・””Dl7.1% Dl7.2・°°・D
l7.6 and subsequent block parity P1, P2,
..., P7, and each block data and block parity includes a CILCC (cyclic redundancy check code), and K, parallel 8 pins, 216 samples, that is, 1728 pins are collected from the focus signal. ing. The parity pl-p is, for example, vertical simple even parity. These block data are arranged in a matrix of 17 rows and 6 columns as shown in FIG. 3, and block parities P1 to P6 are arranged at the bottom of each column. Then, as shown in FIG. 4, for this block data and block parity,
Absolute addresses from 1st to 108th addresses are assigned in the row direction. Therefore, when one magnetic trunk is reproduced, digital information signals are reproduced in the order of these absolute addresses.

Next, referring to FIG. 2, a stone explaining the apparatus of the embodiment is shown in which the magnetic tape is reproduced and the digital information signal supplied to the input terminal (1) is as shown in FIGS. 5 and 6. An example will be explained in which the block data at the first to third addresses are missing. In this case, as shown by diagonal lines in FIGS. 5 and 6, block data Di5, D26, D3, 2 and 107th address Di5, D26, D3, 2 and 107th address,
It is assumed that there is an error in the block parity P5 of the address, but the other blocks are correct.

Digital information signal from input terminal (1) (Fig. 5, 6)
and FIG. 7A) is supplied to a CRC circuit (2), a head address launch circuit (3), a syndrome calculation circuit (4), and a delay compensation circuit (5).

On the output side of the CRC circuit (2), the digital information signal C
An error flag signal (see the left side of FIG. 7B) for each block is output, and the error flag signal indicates the block data and block at addresses 5, 12, 14, and 107 that have errors. It is a binary number "1" for parity, and a binary number "0" for other error-free block data and block parity. If there is an error in even 1 bit out of 1728 bits in the block data or block parity, the error flag signal becomes 1''.The error flag signal at the 4th address to the 108th address is stored in the error memory (6). (The power is an address counter for this memory (6).

The head address launch circuit (3) launches the fourth address of the digital information signal, which is the address of the first reproduced block data. Based on the launch output of the launch circuit (3), the missing block detection circuit (8) detects the address of the missing block data, and when there is one missing block data in a certain column, the first output terminal ( A first detection output is generated at the terminal 8a), and when there are two or more missing block data, a second detection output is generated at the second output terminal (8b).

Also, based on the latch output of the launch circuit (3), the address signal at the time of writing supplied from the address counter (7) to the error memory (6) starts from the fourth address.

The syndrome calculation circuit (4) calculates syndromes S1 to S6 for the block data and block parity of the first to sixth columns.

The digital information signal is supplied to the data replacement 6 data correction circuit (9) via a delay compensation circuit (5) that takes into account the writing time of the error memory (6).

α barrel is the number of missing columns in the matrix 'fill-like arrangement of digital information signals for each process, and the number of block data and block parities with errors that can be corrected (1 in the case of simple parity). This is a means for determining the possibility of error correction for determining whether or not the error is below.

The error flag signal from the CRC circuit (2) is supplied to the error detection circuit 0, which detects whether or not there is an error in the block data and block parity of the first to sixth columns. Here, the second column from FIGS. 5 and 6,
It is detected that there is an error in the block data or block parity in the fifth and sixth columns.

0υ is a circuit for determining the possibility of error correction, which includes a CRC
An error flag signal from the circuit (2) and first and second detection signals from the missing pronk detection circuit (8) are supplied. This discrimination circuit structure can be corrected when there is no missing block data in each of the first to sixth columns and the number of block data or block parities with errors is one or less (in the case of simple parity). When the number of signals is two or more, a correctable signal is generated from the discrimination circuit 0υ, and a correctable signal is generated for the first to third columns and the fifth column, and uncorrectable signals are generated from the discrimination circuit 0υ.

Syndrome calculation circuit (4), error detection circuit a
Repeating circuits (121, C3, (14) are connected to the next stage of the error correction possibility determining circuit 0υ, and when reading the error memory (6), the block data of each read address is Synchronizing with each block parity, the syndromes S1 to aS of the columns to which it belongs (FIG. 7C), the error presence/absence signal Ex=Eg (FIG. 7D), and correction for each block data and block parity are Each of the command signals C1-C6 (FIG. 7E) is repeatedly generated.

Further, (151 is an error-7 lag control circuit, 061 is a data modification circuit, and (17) is an output terminal.

The data replacement/data correction circuit (9) receives digital information signals from the delay compensation circuit (5) and the first and second output terminals (8a') of the missing block detection circuit (8).
The first and second detection signals from (8b), the syndrome s1% s6 from the repeating circuit (12+), and the correction command signals 01 to C6 from the repeating circuit αa are supplied.

The error flag control circuit a receives the error flag signal read from the error memory (6) and the first and second output terminals (8a) and (8b) of the missing block detection circuit (8).
The first and second detection signals of the repeat circuit 0, the signals El to E6 indicating the presence or absence of errors of the repeat circuit
) and a correction command signal cl-C6 are supplied.

Then, the data replaced or data corrected digital information signal (FIG. 7 F) from the data replacement/data correction circuit (9) and the controlled error flag signal (FIG. 7 G) from the error flag control circuit 09 are transmitted. It is supplied to data modification circuit Qf9.

Now, when the error memo (January 6) is in the reading state, the 7th
The error flag signal is read out as shown on the right side of FIG.

However, the error flags at addresses 1 to 3 are not read out.

Syndrome 81-S obtained from repetitive circuit a'IJ
6 (Figure 7C) is as follows. However, ■ is a symbol indicating modulo 2.

S1= D2,1■D3,1■・・・・・・■
PIS2== D2,2■D3,2■・・・
・・■P283””D2,3■D3,3■・
...■P3S4-I)114■D2,4■D3,
4■・・・・・・CF) P485=D15■D25■D
3 5■・・・・・・■P5S6-D16■D26■D
36 ■・・・・・・■ The presence/absence of error signal El=Es (Fig. 7 D) obtained from the P6 repeating circuit α is set to “1”.
If "," and "nothing" are set as "0," then the result is as follows.

Er = E3 = E4 = O H2 = E5 = E6 = 1 The correction command signal C1-〇s (Fig. 7E) obtained from the repeating circuit 0 is 1" for uncorrectable and '0" for correctable.
Then, it becomes as follows.

C1=C2=Ca=C5=1C4-06-0 First, since block data is missing one by one in the first to third columns, the first output terminal (8a) of the missing block detection circuit (8) ← to the first detection output.

Based on the data, the missing block data at the first to third addresses are replaced by the data replacement/data correction circuit (9) to perform the data replacement/data correction circuit (9). Replace with S2,83. In this case, there is no error in the first and third columns, so the syndrome S1+8
3 are equal to the original block data DI, 1°Dl, and 3, respectively, and do not require modification, so the error flag control circuit (15
At this time, an error flag signal "0" is generated for each of these block data as shown in FIG. 7G. These syndrome and error flag signals are then supplied to a data modification circuit Q6).

Since there is one piece of block data with an error in the second column, syndrome S2 is caused by the original block data ZD1,2.
(However, there is a high possibility that the values will be similar), so the error flag control circuit 09 sends an error flag signal "'1" to this block data as shown in FIG. 7G.
" is created, and at the same time, the syndrome Sl is supplied to the data modification circuit aeK and modified.

Syndrome 81-S in place of missing block data
3 is used to correct other block data in that column.
,,jjl,.

Since it does not contribute, the block data D2,1 to D2,3% of the first 1st column to the third column D3,1 to D3,3...
...The error flag signals for Dl7.1 to D17.3 are those read from the error immo January 6) and are obtained on the output side of the error flag control circuit Q5), and are sent to the correction circuit along with the block data and block parity. is supplied to αe. Block data D3, 2 is not corrected, but is modified by data modification circuit Ql19.

Next, there is no missing block data in the fourth to sixth columns. There is no error in the fourth column, so there is no problem.

There are two errors in the fifth column, so block data D
Since correction of 1 and 5 is impossible, correction is performed by the correction circuit ae. There is one error in the 6th column, so the block data D2,6 is D2,6■S6 using Jindromura.
The data is corrected by the calculation in the data replacement/data correction circuit (9). Therefore, the error flag signal "1" at the 12th address read from the error memo January 6) is corrected to "0" in the error flag control circuit a9.

Next, the digital information signal supplied to the input terminal (1) of the device shown in FIG.
A case where block data of an address is missing will be explained. In this case, for simplicity, it is assumed that there is no error in either block data or block parity.

First, in the first and second columns, two pieces of block data are missing and cannot be reproduced, so the missing block detection circuit (8
) Based on the second detection output from the second output terminal (8b) of ″
lO" and sends it to the data modification circuit αeK together with the error flag signal "1" generated by the error flag control circuit α9 for modification. In the third to sixth columns, one piece of block data is missing. Therefore, the block data corresponds to syndromes 83 to 83, respectively, as in the case of Figs. 5 and 6.
It is sufficient to replace it with S6. Other explanations will be omitted.

Note that the digital information signal may be of any type, such as a digital video signal or a digital audio signal. Further, the parity does not matter, such as vertical parity, horizontal parity, odd parity, even parity, black parity of number parity, simple parity, or other parity.

When arranging the blocks in a matrix, the rows and columns may be exchanged.

According to the present invention described above, when reproducing a digital information signal recorded on a recording medium such as a magnetic tape, even if a signal is missing at the beginning of reproduction, it does not adversely affect error correction. Accordingly, it is possible to obtain an error correction device that does not cause a decrease in information recording density.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the recording pattern of a magnetic tape, FIG. 2 is a block diagram showing an embodiment of the error correction device according to the present invention, and FIGS. 3 to 6 are diagrams showing the arrangement of block data and block parity. FIG. 7 is a diagram showing a time chart for explaining the apparatus of FIG. 2, and FIGS. 8 and 9 are layout diagrams showing the arrangement of block data and block parity.゛(8), Yoga, 7. . 72 □ 工; -9 yo two. Engineering. 0υ is a data replacement circuit, 0υ is a circuit for determining the possibility of error correction, ae is a data modification circuit, and ae is a means for determining the possibility of error correction. Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] By supplying a digital information signal consisting of block data with absolute addresses and block parity reproduced from a recording medium, omissions in rows or columns and errors in the matrix arrangement of blocks of the digital information signal are provided. error correction possibility determining means for determining whether or not the number of block data and block parity is less than or equal to the number for which error correction is possible; When the number of block data and block parity with missing rows or columns in the row or column 2- is less than the number that can be corrected, the block data with the missing or error is processed using the syndrome of the row or column. and a data correction circuit that corrects missing rows or columns in the matrix arrangement of each block of the digital information signal, and when the number of block data and block parities with errors exceeds the number that can be corrected. or a data modification circuit for modifying block data with an error.