JPH0244584A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPH0244584A
JPH0244584A JP63194358A JP19435888A JPH0244584A JP H0244584 A JPH0244584 A JP H0244584A JP 63194358 A JP63194358 A JP 63194358A JP 19435888 A JP19435888 A JP 19435888A JP H0244584 A JPH0244584 A JP H0244584A
Authority
JP
Japan
Prior art keywords
circuit
output
error correction
signal
interpolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63194358A
Other languages
Japanese (ja)
Other versions
JP3062659B2 (en
Inventor
Shingo Ikeda
信吾 池田
Motoichi Kashida
樫田 素一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP19435888A priority Critical patent/JP3062659B2/en
Application filed by Canon Inc filed Critical Canon Inc
Priority to DE68929548T priority patent/DE68929548T2/en
Priority to DE68929394T priority patent/DE68929394T2/en
Priority to EP89114373A priority patent/EP0353757B1/en
Priority to EP01124427A priority patent/EP1189455A3/en
Priority to EP97106187A priority patent/EP0794666B1/en
Priority to DE68928449T priority patent/DE68928449T2/en
Priority to SG9606923A priority patent/SG95576A1/en
Priority to EP97106172A priority patent/EP0793383B1/en
Publication of JPH0244584A publication Critical patent/JPH0244584A/en
Priority to US08/468,571 priority patent/US6084730A/en
Application granted granted Critical
Publication of JP3062659B2 publication Critical patent/JP3062659B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the constitution of a whole system by transmitting the flag signal of error uncorrectable data at the time of recording and reproducing as well and totally executing interpolation in a receiving side. CONSTITUTION:The reproducing output of an electro-magnetic converting system 14 is inputted to an error correcting circuit 34 and an error due to the recording and reproducing is corrected according to an error correcting code by an ECC adding circuit 12. Then, an interpolating flag 35 is outputted to the uncorrectable data and the signal 35 is added in each data from the circuit 34 by an adder circuit 36 and sent through an ECC adding circuit 38 to a transmitting path 26. In the receiving side, a transmission error is corrected by an error correcting circuit 40 and an interpolating flag 42 is outputted to an interpolating flag signal 41 corresponding to the signal 35 and the uncorrectable data. The signals 41 and 42 are added 44. According to an adding output, an interpolating circuit 32 executes interpolation processing to the output of an extending circuit 30.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデータ伝送システムに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to data transmission systems.

〔従来の技術〕[Conventional technology]

従来、ディジタル・テレビジョン信号を帯域圧縮して磁
気テープに記録し、当該磁気テープの再生信号を再び帯
域圧縮して伝送路に送出する伝送WEは、公知である。
Conventionally, a transmission WE is known that compresses the band of a digital television signal and records it on a magnetic tape, compresses the playback signal of the magnetic tape again, and sends the signal to a transmission path.

その構成例を第2図に示す。An example of its configuration is shown in FIG.

第2図において、ディジタル・テレビジョン信号は、帯
域圧縮回路10により帯域圧縮され、誤り訂正符号(F
 CC)付加回路12に印加される。
In FIG. 2, a digital television signal is subjected to band compression by a band compression circuit 10 and an error correction code (F
CC) is applied to the additional circuit 12.

誤り訂正付加回路12は、記録再生に伴う誤りを検出し
訂正するための誤り訂正符号を付加する。
The error correction addition circuit 12 adds an error correction code for detecting and correcting errors during recording and reproduction.

ECC付加回路12の出力は、磁気ヘッド及び磁気記録
媒体からなる電磁変換系14を介して誤り訂正回路16
に供給される。誤り訂正回路16は、ECC付加回路1
2で付加された誤り訂正符号を使って、電磁変換系14
における記録再生による誤りを訂正する。誤り訂正回路
16は訂正不能である場合には補間フラグ信号17を出
力する。伸長回路18は、誤り訂正回路16の出力に対
し、帯域圧縮回路10の帯域圧縮処理とは逆の伸長処理
を施し、補間回路20は、誤り訂正回路16からの補間
フラグに従い、誤り訂正不能データを補間する。回路1
0〜回路20の部分は、所謂ディジタルVTR装置に相
当しており、補間回路20の出力は、通常のディジタル
・テレビジョン信号である。
The output of the ECC addition circuit 12 is sent to an error correction circuit 16 via an electromagnetic conversion system 14 consisting of a magnetic head and a magnetic recording medium.
is supplied to The error correction circuit 16 includes the ECC addition circuit 1
Using the error correction code added in step 2, the electromagnetic conversion system 14
Correct errors caused by recording and playback. The error correction circuit 16 outputs an interpolation flag signal 17 when the error cannot be corrected. The expansion circuit 18 performs an expansion process on the output of the error correction circuit 16 that is opposite to the band compression process of the band compression circuit 10, and the interpolation circuit 20 performs an expansion process on the output of the error correction circuit 16, which is opposite to the band compression process performed by the band compression circuit 10. Interpolate. circuit 1
0 to circuit 20 correspond to a so-called digital VTR device, and the output of interpolation circuit 20 is a normal digital television signal.

補間回路20の出力は、伝送のための帯域圧縮回路22
に印加され、そこで帯域圧縮されて、ECC付加回路2
4で伝送のための誤り訂正符号(ECC)を付加される
。帯域圧縮回路22及びECC付加回路24は、所謂コ
ーデック(CODEC)のコーダ部に相当する。
The output of the interpolation circuit 20 is transmitted to a band compression circuit 22 for transmission.
is applied to the ECC adding circuit 2, where it is band-compressed and sent to the ECC adding circuit 2.
4, an error correction code (ECC) for transmission is added. The band compression circuit 22 and the ECC addition circuit 24 correspond to a coder section of a so-called codec.

ECC付加回路24の出力データは伝送路26を介して
、受信側の誤り訂正回路28に人力する。
The output data of the ECC addition circuit 24 is input to the error correction circuit 28 on the receiving side via the transmission line 26.

誤り訂正回路28はECC付加回路24が付加した誤り
訂正符号に従って、伝送誤りを訂正する。
The error correction circuit 28 corrects transmission errors according to the error correction code added by the ECC addition circuit 24.

誤り訂正回路28は訂正不能の場合には、補間フラグ信
号29を出力する。伸長回路30は誤り訂正回路28の
出力に対し、帯域圧縮回路22での帯域圧縮処理に対応
する伸長処理を施し、補間回路32は、誤り訂正回路2
8からの補間フラグ信号29に従い、訂正不能データ部
分を補間する。
The error correction circuit 28 outputs an interpolation flag signal 29 when the error cannot be corrected. The expansion circuit 30 performs expansion processing corresponding to the band compression processing in the band compression circuit 22 on the output of the error correction circuit 28, and the interpolation circuit 32 performs expansion processing on the output of the error correction circuit 28.
According to the interpolation flag signal 29 from 8, the uncorrectable data portion is interpolated.

回28〜32がコーデックのデコーダ部に相当し、補間
回路32の出力はディジタル・テレビジョン信号である
The circuits 28 to 32 correspond to the decoder section of the codec, and the output of the interpolation circuit 32 is a digital television signal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来例では、電磁変換系14と伝送路26で発
生するデータ・エラーの補間を別々に行っており、2個
の補間回路20.32が必要である。また、補間回路2
0で補間を行うために、伸長回路18により圧縮データ
を一旦伸長しており、従って、データ伝送のために、再
度、帯域圧縮回路22で帯域圧縮している。
However, in the conventional example, data errors occurring in the electromagnetic conversion system 14 and the transmission line 26 are interpolated separately, and two interpolation circuits 20 and 32 are required. Also, interpolation circuit 2
In order to perform interpolation with 0, the compressed data is once expanded by the expansion circuit 18, and therefore, for data transmission, the band is again compressed by the band compression circuit 22.

このように、従来例ではシステム構成上、無駄が多(、
従って、装置が大型化し、高価格化しがちである。
In this way, in the conventional example, there is a lot of waste due to the system configuration (,
Therefore, the device tends to be large and expensive.

そこで本発明は、より簡潔な構成のデータ伝送システム
を提示することを目的とする。
Therefore, an object of the present invention is to present a data transmission system with a simpler configuration.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係るデータ伝送システムは、ディジタル画像信
号を帯域圧縮する帯域圧縮手段と、当該帯域圧縮手段に
よる帯域圧縮信号を記録再生すると共に、記録再生時の
誤りを訂正する能力を具備する記録再生手段とを具え、
当該記録再生手段の再生データ及び再生時の誤り訂正不
能を示すフラグ信号を伝送媒体に出力する。
A data transmission system according to the present invention includes a band compression means for band compression of a digital image signal, and a recording and reproducing means having the ability to record and reproduce the band compressed signal by the band compression means and to correct errors during recording and reproduction. and
The reproduced data of the recording/reproducing means and a flag signal indicating that error correction is not possible during reproduction are output to the transmission medium.

〔作用〕[Effect]

記録再生時の誤り訂正不能データについては、そのフラ
グ信号をも伝送して受信側で一括して補間するので、シ
ステム全体として構成を簡略化できる。伝送エラー・レ
ートは充分に低いので、受信側において当該フラグ信号
を誤って理解する可能性は極めて小さい。
Regarding uncorrectable error data during recording and reproduction, the flag signal is also transmitted and interpolated all at once on the receiving side, so the overall system configuration can be simplified. Since the transmission error rate is sufficiently low, the possibility that the flag signal will be misunderstood on the receiving side is extremely small.

〔実施例〕〔Example〕

以下、図面を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の構成ブロック図を示す。第
1図において、第2図と同じ構成要素には同じ符号を付
しである。帯域圧縮回路10、ECC付加回路12及び
電磁変換系14については、第2図の場合と同様である
。電磁変換系14の再生出力は誤り訂正回路34に入力
され、誤り訂正回路34はECC付加回路12で付加さ
れた誤り訂正符号に従い、電磁変換系14での記録再生
による誤りを訂正し、訂正不能のデータに対しては補間
フラグ信号35を出力する。加算回路36は、誤り訂正
回路34から出力される所定量のデータ毎に、例えばそ
の後ろに補間フラグ信号35を付は加える。ECC付加
回路38は、加算回路36からのデータに対して誤り訂
正符号を付加し、伝送路26に送出する。
FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, the same components as in FIG. 2 are given the same reference numerals. The band compression circuit 10, ECC addition circuit 12, and electromagnetic conversion system 14 are the same as in the case of FIG. The reproduction output of the electromagnetic conversion system 14 is input to the error correction circuit 34, and the error correction circuit 34 corrects errors caused by recording and reproduction in the electromagnetic conversion system 14 according to the error correction code added by the ECC addition circuit 12, and corrects errors that cannot be corrected. An interpolation flag signal 35 is output for the data. The addition circuit 36 adds, for example, an interpolation flag signal 35 after each predetermined amount of data output from the error correction circuit 34. The ECC adding circuit 38 adds an error correction code to the data from the adding circuit 36 and sends it to the transmission line 26.

受信側では、伝送路26を伝送したデータは誤り訂正回
路40に入力し、誤り訂正回路40は、ECC付加回路
38で付加された誤り訂正符号を使って伝送誤りを訂正
する。誤り訂正回路40はまた、補間フラグ信号35に
対応する補間フラグ信号41を出力すると共に、訂正不
能データに対して補間フラグ信号42を出力する。補間
フラグ信号41.42は加算回路44に印加される。加
算回路44は論理的にはオア回路として機能し、何れか
の補間フラグ信号41.42が補間の必要性を示す場合
に、そのフラグ信号を補間回路32に印加する。
On the receiving side, the data transmitted through the transmission path 26 is input to an error correction circuit 40, and the error correction circuit 40 corrects transmission errors using the error correction code added by the ECC addition circuit 38. The error correction circuit 40 also outputs an interpolation flag signal 41 corresponding to the interpolation flag signal 35, and also outputs an interpolation flag signal 42 for uncorrectable data. Interpolation flag signals 41 and 42 are applied to adder circuit 44. Adder circuit 44 logically functions as an OR circuit, and applies that flag signal to interpolation circuit 32 when any of the interpolation flag signals 41, 42 indicates the necessity of interpolation.

伸長回路30は、誤り訂正回路40の出力データに対し
て、帯域圧縮回路10での帯域圧縮処理に対応する伸長
処理を施する。補間回路32は、加算回路44の出力に
従って、伸長回路30の出力に対して補間処理を行う。
The decompression circuit 30 performs decompression processing on the output data of the error correction circuit 40 that corresponds to the band compression processing performed by the band compression circuit 10 . The interpolation circuit 32 performs interpolation processing on the output of the expansion circuit 30 according to the output of the addition circuit 44.

なお、通常、伝送路26でのエラー・レートは非常に小
さいので、誤り訂正回路34の出力する補間フラグ信号
が伝送路26を介して伝送されても、伝送中に誤りを生
じることはほとんどなく、補間フラグ信号の伝送誤りに
よる画質劣化は、殆ど考えられない。
Note that since the error rate on the transmission line 26 is normally very small, even if the interpolation flag signal output from the error correction circuit 34 is transmitted via the transmission line 26, almost no errors will occur during transmission. , image quality deterioration due to transmission errors in the interpolation flag signal is almost unthinkable.

また、上述実施例では画像信号を伝送する構成としたが
、本発明は画像信号に限らず、音声信号などの他の情報
信号をディジタル・データとして伝送するシステムにつ
いても適用できることはいうまでもない。
Further, although the above-described embodiment has a configuration in which image signals are transmitted, it goes without saying that the present invention is applicable not only to image signals but also to systems that transmit other information signals such as audio signals as digital data. .

〔発明の効果〕〔Effect of the invention〕

以上の説明から容易に理解できるように、本発明によれ
ば、1回の補間処理で済み、また、帯域圧縮及び伸長処
理も1回で済む。従って、システム全体の構成を小型化
し、軽量化することができる。
As can be easily understood from the above description, according to the present invention, only one interpolation process and one band compression and expansion process are required. Therefore, the overall system configuration can be made smaller and lighter.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の構成ブロック図、第2図は従
来例の構成ブロック図である。 1〇−帯域圧縮回路 12.38−誤り訂正符号付加回
路 14−電磁変換系 18,30・−伸長回路 20
.32−・補間回路 26・−伝送路 34.40−誤
り訂正回路 35. 41. 42−補間フラグ信号 
36−加算回路 特許出廓人 キャノン株式会社
FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram of the configuration of a conventional example. 10 - Band compression circuit 12.38 - Error correction code addition circuit 14 - Electromagnetic conversion system 18, 30 - Expansion circuit 20
.. 32--Interpolation circuit 26--Transmission line 34.40-Error correction circuit 35. 41. 42-Interpolation flag signal
36- Adder circuit patent distributor Canon Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] ディジタル信号を帯域圧縮する帯域圧縮手段と、当該帯
域圧縮手段による帯域圧縮信号を記録再生すると共に、
記録再生時の誤りを訂正する能力を具備する記録再生手
段とを具え、当該記録再生手段の再生データ及び再生時
の誤り訂正不能を示すフラグ信号を伝送媒体に出力する
ことを特徴とするデータ伝送システム。
A band compression means for band compression of a digital signal, recording and reproducing a band compression signal by the band compression means,
A data transmission comprising a recording and reproducing means having the ability to correct errors during recording and reproducing, and outputting reproduced data of the recording and reproducing means and a flag signal indicating inability to correct errors during reproduction to a transmission medium. system.
JP19435888A 1988-08-05 1988-08-05 Digital information processing method Expired - Fee Related JP3062659B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP19435888A JP3062659B2 (en) 1988-08-05 1988-08-05 Digital information processing method
EP97106172A EP0793383B1 (en) 1988-08-05 1989-08-03 Information transmission system with record/reproducing device
EP89114373A EP0353757B1 (en) 1988-08-05 1989-08-03 Information transmission system with record/reproducing device
EP01124427A EP1189455A3 (en) 1988-08-05 1989-08-03 Information transmission system with record / reproducing device
EP97106187A EP0794666B1 (en) 1988-08-05 1989-08-03 Information transmission system with record/reproducing device
DE68928449T DE68928449T2 (en) 1988-08-05 1989-08-03 Information transmission system with recording / playback device
DE68929548T DE68929548T2 (en) 1988-08-05 1989-08-03 Information transmission system with a recording / reproducing device
DE68929394T DE68929394T2 (en) 1988-08-05 1989-08-03 Information transmission system with recording / playback device
SG9606923A SG95576A1 (en) 1988-08-05 1989-08-03 Information transmission system with record/reproducing device
US08/468,571 US6084730A (en) 1988-08-05 1995-06-06 Information transmission system using data compression and/or error detection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19435888A JP3062659B2 (en) 1988-08-05 1988-08-05 Digital information processing method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP32778498A Division JP3387837B2 (en) 1988-08-05 1998-11-18 Information processing apparatus and method

Publications (2)

Publication Number Publication Date
JPH0244584A true JPH0244584A (en) 1990-02-14
JP3062659B2 JP3062659B2 (en) 2000-07-12

Family

ID=16323251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19435888A Expired - Fee Related JP3062659B2 (en) 1988-08-05 1988-08-05 Digital information processing method

Country Status (1)

Country Link
JP (1) JP3062659B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155509A (en) * 1982-03-11 1983-09-16 Sony Corp Reproducer for audio signal
JPS58222411A (en) * 1982-06-18 1983-12-24 Sony Corp Device for correcting error
JPS59167145A (en) * 1984-03-02 1984-09-20 Hitachi Denshi Ltd Error correcting system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155509A (en) * 1982-03-11 1983-09-16 Sony Corp Reproducer for audio signal
JPS58222411A (en) * 1982-06-18 1983-12-24 Sony Corp Device for correcting error
JPS59167145A (en) * 1984-03-02 1984-09-20 Hitachi Denshi Ltd Error correcting system

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