JPS58221177A - Tester for integrated circuit - Google Patents

Abstract

PURPOSE:To enable testing of an optional circuit in an optional testing period, by detecting the dissidence of an expected value signal and the output of an integrated circuit, etc., and blocking the output of a dissidence circuit during said period. CONSTITUTION:The dissidence between the output of an expected value signal and the output of an integrated circuit is detected with a dissidence circuit 10, and the period since the rise of the expected value signal until the rise of the output of the integrated circuit as well as since the fall of the expected value signal until the fall of the output of the integrated circuit are detected with an edge extraction circuit 14, and the output of the circuit 10 is blocked with an edge removing circuit 13 during said detection periods. Then, the integrated circuit of optional constitution is tested without receiving the limit in the test period by a strobe signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an integrated circuit testing device used to determine whether the integrated circuit is functional or not when manufactured.

[Technical background of the invention]

FIG. 1 shows an example of a conventional integrated circuit testing device.
In the diagram, the strobe signal of strobe signal generation circuit 1 (
c) in 1st. Apply to one input of the second AND dart 2.3. The other input of the first AND gate 2 is given the expected value signal (, ) to be output from the integrated circuit under test, and the other input of the second AND gate 2 is given the test signal. The output signal (b) of the integrated circuit to be executed is given to the output signal (b) of the integrated circuit.Then, the output of each AND dart 2 and 3 is given to the mismatch detection circuit 4, and when a mismatch between the two outputs is detected, a detection signal (d
).

Figure 2 is a waveform diagram explaining the operation of the above test equipment (,)
is an expected value signal, (b) is an output signal, (c) is a strobe signal, and (d) is a detection signal. Here, the Stroop signal (,) is, for example, as shown in FIG. The OR circuit 9 may be used to obtain the logical sum of the Q outputs of the Fritsuno flops 6, 7, and 8.

Therefore, in the waveform diagram shown in FIG. 2, the integrated circuit test is performed as follows:
The test is performed for a period of ``''-'n6, respectively, and a mismatch between the expected value signal (,) and the output signal (b) during this test period is detected.

[Problems with conventional technology]

Generally, in an integrated circuit, its output signal (b) lags behind the expected value signal (IL) due to delays caused by internal calculations. Therefore, when the expected value signal (,) and the output signal (b) are directly compared by a mismatch detection circuit, not only the original malfunction part but also the part where the rising and falling timings of the signal are deviated are regarded as malfunctions. In order to prevent such false detection, it is necessary to
, strobe signal (c) so that the falling part is not included.
need to be set. For this reason, there was a problem in that the test period was limited and the test could not be conducted in an arbitrary period. Furthermore, in such a device, it is necessary to change the strobe signal according to the test conditions of each output of the integrated circuit, which has the disadvantage that the configuration of the strobe signal generation circuit becomes complicated. Furthermore, since the test period differs depending on the integrated circuit to be tested, there is a drawback that the maximum count value of the strobe signal generation circuit must be changed each time.

[Purpose of the invention]

The present invention was developed in view of the above circumstances, and an object of the present invention is to provide an integrated circuit testing device that does not require a strobe signal and can thereby test any integrated circuit in any test period. This is the purpose.

[Summary of the invention]

That is, the present invention detects a mismatch between the expected value signal and the output of the integrated circuit using a mismatch detection circuit, and also detects the mismatch between the rising edge of the expected value signal and the output of the integrated circuit, and from the falling edge of the expected value signal to the output of the integrated circuit. The edge extraction circuit detects the period until the falling edge of , and the output of the mismatch detection circuit is blocked during this detection period.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG. 4 below.

This will be explained in detail with reference to the drawings. That is, the expected value signal (,) to be output from the integrated circuit under test is applied to the mismatch detection circuit 10 and the first edge detection circuit 11. Further, the output signal (f) of the integrated circuit to be tested is applied to the mismatch detection circuit 10 and the second edge detection circuit 12. The first and second edge detection circuits 11 and 12 each generate a detection pulse (h) of a predetermined width in response to each rising and falling edge of the expected value signal (,) and the output signal (f) of the integrated circuit. ) (1) is output. When the mismatch detection circuit 10 detects a mismatch between the expected value signal (,) and the output signal (f), it supplies a detection signal (g) to the edge removal circuit 135-. On the other hand, the first. Second edge detection circuit 11.12
The detection pulse (h) (1) is applied to the edge extraction circuit 14, and after the detection pulse (h) of the first edge detection circuit 11 is output, the detection pulse (1) of the second edge detection circuit 12 is output. During this period, an extraction signal (j) is obtained and applied to the edge removal circuit 13. The edge removal circuit 13 ignores and does not output the detection signal (g) of the mismatch detection circuit 10 during the period when the extraction signal (j) is provided from the edge extraction circuit 14, and does not output the detection signal (g) from the mismatch detection circuit 10 during the period when the extraction signal (j) is not provided. Only the detection signal (g) is output as the mismatch signal (h).

With such a configuration, if the expected value signal (,) and the output signal (f) of the integrated circuit are given as shown in the waveform diagram shown in FIG. Signal (g) is output as shown in p1 to p6. On the other hand, the first step is performed in synchronization with the rise and fall of the expected value signal (,).

The detection pulse (h) from the current detection circuit 11 is a1~!
It is output as shown in 14. Similarly, detection pulses 0) are output from the second edge detection circuit 12 as indicated by r1 to r8 in the figure in synchronization with the rising edge (6-) and the falling edge (9) of the output signal (f). Each detection/gus (h) (1) is an edge extraction circuit 14.
given to. This edge extraction circuit 14 sets, for example, a detection pulse (h) (i), and detects a detection pulse (h) (1) at the frizzoffs o and f applied to the reset terminal.
An extracted signal Q+ is obtained corresponding to the outputs 81 to rH, and similarly outputs 112. An extracted signal q2 is obtained corresponding to r2. Then, the output r3 of the detection pulse (1) of the second edge detection circuit 12. At r4, the edge extraction circuit 14 is already in the reset state, so the output does not change. Then, corresponding to the output 8B+r6 of the detection pulse (h) (1), the extraction signal q
3, and the extracted signal q4 corresponding to the output [14+r8
get. The edge removal circuit 13 ignores the detection signal (g) of the mismatch detection circuit 10 during the period when the edge extraction circuit 14 provides the extraction signal ql''q4.

Therefore, the output pI +pz + of the above detection signal (g)
I) 41p6 are the extraction signals Ql +q3 +qa, respectively.
It is ignored because it matches +q4. Therefore, only the output p3ppS of the detection signal (g) is the mismatch signal (
k), and malfunctions of the integrated circuit can be detected.

FIG. 6 is a block diagram showing a specific example of the present invention, in which exclusive OR (EXI+EX2) is used as the mismatch detection circuit 10 and the edge removal circuit 14, respectively. Also number 1. As the second edge detection circuit 11.12, the expected value signal (,) and the output signal (f) of the integrated circuit are respectively exclusive-OR'd. It is provided via DL, , and DL2.

In addition, the edge extraction circuit 14 is connected to two-man powered and three-man powered NOR, N0R2 cross-connected, and the third input of N0R2 is used as a reset terminal R for setting the initial state. There is.

Therefore, according to the above embodiment, it is possible to remove the mismatch portion due to the delay of the output signal of the integrated circuit with respect to the expected value signal and detect only the true mismatch portion without using a strobe signal.

Therefore, the configuration of the device can be simplified, there is no restriction on the test period, and integrated circuits with different contents can be tested using the same test device.

〔Effect of the invention〕

As described above, the present invention can detect a mismatch between both signals by removing the mismatch portion caused by the delay of the output signal of the integrated circuit with respect to the expected value signal, without using a strobe signal. Therefore, since a strobe signal generation circuit is not required, the configuration can be simplified, and the test period is not limited by the strobe signal, and an integrated circuit of any configuration can be tested. can be provided.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of a conventional test device;
3 is a block diagram showing an example of the strobe signal generation circuit of the device shown in FIG. 1, and FIG. 4 is an embodiment of the present invention. Block diagram showing an example, No. 5
The figure is a waveform diagram explaining the operation of the above embodiment, and FIG. 6 is a block diagram showing a concrete example of the present invention. 10... Mismatch detection circuit, 11.12... Edge detection circuit, 13... Edge removal circuit, 14... Edge extraction circuit. Applicant's agent Patent attorney Takehiko Suzue 10-

Claims (1)

[Claims] a mismatch detection circuit that is given an output signal of an integrated circuit to be tested and an expected value signal to be output from the integrated circuit and detects a mismatch between the two signals; a first edge detection circuit that outputs;
Detection step 4' by detecting the edge of the output signal of the integrated circuit.
and an edge extraction circuit that outputs an extraction signal until the detection pulse of the edge detection circuit of the rear cylinder 2 is applied after receiving the detection pulse of the first edge detection circuit. and an edge removal circuit that prevents the detection signal from the mismatch detection circuit from being output while the edge extraction circuit is receiving the extraction signal.