JPH04204067A - Logic tester with variable filter - Google Patents

Abstract

PURPOSE:To simply and rapidly detect hair-like noise of predetermined pulse width or less by judging the signal state of a digital signal after a variable set time from the rising and falling points of times of the digital signal of an object to be tested. CONSTITUTION:By properly setting a delay time setting switch 33, a delay signal (b) is obtained from a delay circuit 12 and directly inputted to a D-type flip-flop (IFF) 13 as a clock and also inputted to an FF 14 as a reversal delay signal (d) by an inverter 32. When the state of the delay signal (b) at a rising point of time is in an 'L' state with respect to the FF 13, that is, the state is in an 'H' state as a reversal input signal, the rising thereof is judged to be caused by noise of positive polarity or a hair-like pulse and an 'H' state is obtained as a judging signal (e). Further, a judging signal (f) is obtained from the FF 14 and the OR of the judging signals (e),(f) is taken and a judgment result (g) is obtained to be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is directed to a logic system with a variable filter for detecting and displaying noise of a predetermined pulse width or less or whisker-like pulses mixed into a digital signal. This is related to Tsukutester.

[Prior Art] Until now, in logic tests using logic testers that are generally used to adjust and check the operation of digital circuits, the signal state of the digital signal to be tested is "H". , "L" state and the presence or absence of a pulse signal are detected.

Note that as a logic tester used to adjust and check the operation of a digital circuit, the one described in, for example, Japanese Unexamined Patent Application Publication No. 10894/1988 is known. In this case, a delay circuit with a fixed delay time is used.

[Problem to be Solved by the Invention] However, in the case according to the above publication, since the delay time in the delay circuit is fixed, the pulse signal to be detected must have a pulse width equal to or less than the delay time. Therefore, a pulse signal whose pulse width exceeds the delay time cannot be detected, and its applicable range is narrow.

Incidentally, one of the causes of malfunction of digital circuits is the presence of whisker-like pulses and noise in digital signals. When designing the circuit, operation delays in various digital elements were not sufficiently considered, resulting in unexpected round pulse signals being generated in addition to the desired pulse signals, or due to other causes. As a result, there are surprisingly many malfunctions caused by these factors, such as noise being mixed into digital signals. Furthermore, in order to investigate the causes of such malfunctions, it is essential to analyze and observe digital signal waveforms using logic analyzers, synchroscopes, etc., so it takes a lot of time to investigate the causes. is the reality.

An object of the present invention is to provide a logic tester with a variable filter that can detect and display whisker-like pulses and noise existing in digital signals simply and quickly, and even with extremely small pulse widths. It is in.

[Means for Solving the Problem] The above purpose is to test the digital signal after a variable set time (less than the original minimum specified pulse width of the signal) from each of the rising and falling points of the digital signal to be tested. This is achieved by providing means for detecting positive polarity or negative polarity noise or whisker-like pulses mixed in a digital signal by determining the state, and means for displaying the detection result.

[Function] If the signal state of the digital signal is in the "L" state after a variable set time has elapsed from the rising edge of the digital signal to be tested, the signal state of the digital signal should be in the "L"state; It can be determined that positive polarity noise or whisker-like pulses exist, and in this case, the larger the variable setting time is set, the more noise and whisker-like pulses with various pulse widths can be detected. It is.

The above situation is the same for the fall of the digital signal, and if the signal state of the digital signal is in the "H" state after a variable set time from the falling point, the signal state of the digital signal is in the "H" state. It can be determined that negative polarity noise or whisker-like pulses exist in the state that should exist.

[Example] The present invention will be explained below with reference to FIGS. 1 to 4.

First, the logic tester according to the present invention will be explained.
FIG. 2 shows the general configuration of the entire system. In this case, the digital signal to be tested is branched into the logic level etc. detection circuit 2 and the pulse detection circuit 1 through the input terminal 4 and the buffer gate 30, so that a predetermined test is performed on the digital signal. It is becoming more and more popular. That is, in the logic level detection circuit 2,
The logic level (including intermediate levels) is monitored and displayed by constant analog monitoring of the signal level on the digital signal line as the test object, and the presence or absence of input/output pulse signals is detected. The detection circuit 1 is designed to detect whisker-like pulses and noise. The detection results from the logic level etc. detection circuit 2 and the pulse detection circuit 1 are displayed in a predetermined manner on the display circuit 3.
Logic tests can be easily performed on digital signals as test targets.

Now, FIG. 1 shows one part of the pulse detection circuit 1 according to the present invention.
FIG. 3 shows a specific configuration of the delay circuit 12 in this configuration, and FIG. 4 shows the operation of the pulse detection circuit shown in FIG. 1. As shown in FIG. 4, the input signal a to the pulse detection circuit l includes a positive polarity pulse P whose pulse width is less than the minimum prescribed pulse width of the original signal, and a negative polarity pulse P2. However, the idea is to detect pulses with such a pulse width using a pulse detection circuit.

Here, to explain the operation of the pulse detection circuit shown in FIG. 1 with reference to FIG. 4, the input signal a is delayed by the delay circuit 12 and obtained as a delayed signal. T depends on the setting signal from the delay time setting switch 33. As shown in FIG. 3, the input signal a is delayed by each of a plurality of delay elements 21 having different delay times, and a delayed signal a is selectively obtained from any of the delay elements 21 via the selector 22. This is determined by the setting signal from the delay time setting switch 38.

By appropriately setting the delay time setting switch 33, a desired delayed input signal a1, that is, a delayed signal, can be obtained from the delay circuit 12. (hereinafter simply referred to as F/F) 13 can be used as a direct clock input, or as an F/F.
F14 is converted into an inverted delayed signal d by an inverter 32, and is also manually input as a clock input. On the other hand, input signal a is F/F 14
As direct data input for F/F 13
are converted into inverted input signals C by an inverter 31, and then inputted as data inputs. Therefore, the state of the inverted input signal C at the rising edge of the delay signal S is stored in the F/F 13.
14, the state of the input signal a at the falling edge of the delay signal S is latched, but since F/Fs 13 and 14 are set, the positive polarity pulse P and the negative polarity pulse P described above are latched. The pulse P♀ of can be detected.

That is, first, to explain F/F 13, if the input signal a is in the "L" state at the time of the rise of the delayed signal, and therefore is in the "H" state as an inverted input signal, then the rising edge is of positive polarity. Since the F/F 13 is placed in the set state at the time of the rise, the judgment signal e as the Q output is "H".
Next, to explain the F/F 14, if the input signal a is in the state of "H" or is in the "H" state at the falling edge of the delayed signal, then the falling edge is caused by negative polarity noise. This is said to be caused by a whisker-like pulse, and F
Since /F 13 is placed in the set state, an "H" state is obtained as the determination signal f as its Q output. Judgment signal e.

f is logically summed by the OR gate 15 to obtain the final judgment result g, which is then displayed on the display circuit. In this example, either judgment signal e or f is "H". ”
At the point when it transitions to the state, check the judgment result g and set F/F13,
14 is to be immediately and forcibly reset.

Although the operation of the pulse detection circuit shown in FIG. 1 has been described above, there are various other possible configurations of the pulse detection circuit. For example, it is conceivable to detect each of the rising and falling edges of the input signal a, delay the signal by a desired time using a delay circuit, and use it as a clock input to F'/F. Another possibility is to AND the clock input and each inverted input signal C9'' input signal a using an AND gate, and trigger the monostable multivibrator based on the AND result. There is.

[Effects of the Invention] As explained above, according to claims 1 to 3, whisker-like pulses and noise existing in a digital signal can be easily and quickly detected, and even whisker-like pulses and noise with an extremely small pulse width can be detected.・It will be possible to display the information.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a specific configuration of the pulse detection circuit according to the present invention, FIG. 2 is a diagram showing the overall general configuration of the logic tester according to the present invention, and FIG. FIG. 4 is a diagram showing a specific configuration of the delay circuit shown in the figure, and FIG. 4 is a diagram showing the operation of the pulse detection circuit shown in FIG. 1. 12...Delay circuit 13.14...D-type flip-flop 15...OR gate 31.32...Inverter 33...Delay time setting switch Patent applicant Hitachi Communication Systems Co., Ltd. Agent Patent attorney Akimoto True truth

Claims (1)

[Claims] 1. A logic tester for detecting and displaying noise of a predetermined pulse width or less or whisker-like pulses mixed in a digital signal, which detects and displays a rising point of a digital signal as a test object; Means for detecting positive polarity noise, negative polarity noise, or whisker-like pulses mixed in the digital signal by determining the signal state of the digital signal after a variable set time from each falling point, and the means A logic tester with a variable filter, comprising: means for displaying detection results from the filter. 2. A logic tester for detecting and displaying noise of a predetermined pulse width or less or whisker-like pulses mixed in a digital signal, comprising means for variably setting a delay of a digital signal as a test object; means for detecting positive polarity or negative polarity noise or whisker-like pulses mixed in the digital signal by determining the signal state of the digital signal at each of the rising and falling points of the digital signal from the means; A logic tester with a variable filter, comprising: and means for displaying detection results from the means. 3. A logic tester for detecting and displaying noise with a predetermined pulse width or less mixed in a digital signal, or whisker-like pulses, which detects the rising and falling points of the digital signal being tested. a rising/falling means for detecting rising and falling edges; a delay means for variably setting a delay for each of the rising and falling detection results from the delay means; and determining the signal state of the digital signal at each of the rising and falling detection results from the delaying means. The apparatus comprises a noise detection means for detecting positive polarity or negative polarity noise or whisker-like pulses mixed in a digital signal, and means for displaying a detection result from the noise detection means. Logic tester with variable configuration filter.