JPS58220216A - Error correcting device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit, by decoding the output of a counter which counts pointers showing the errors of digital information words and extracting the erroneous addresses in a block by a sequence control circuit based on the counting result of said counter. CONSTITUTION:The pointers showing errors of the digital information words are applied to a clock input terminal 10 and counted 13. A memory 15 reads in the value of a counter 16 with the number of errors used as addresses. A decoder 14 delivers an output corresponding to the presence or absence of errors from the address of a counter 13. The conditions are discriminated from the output of the decoder 14, and the word address within an error block is supplied to an input terminal 9. Then the word address delivered to an output terminal 17 of the memory 15, the head address of the block within a register 19 and the check word in a register 21 are added ALU to obtain a corrected word. The outputs of the decoder 14 are counted 22 and connected to the addresses of an ROM23. Thus a sequence controlling circuit is obtained to perform a correcting process. This action can detect effectively the error words only.

Description

Detailed Description of the Invention Page 2 The present invention relates to a 0 error correction device for decoding 911'v signal 0, and its purpose and purpose is to correct errors that can simplify the circuit. The goal is to provide equipment.

Generally, when a digital recording/reproducing device decodes a digital signal into an analog signal, it memorizes errors that occur due to dropouts of the recording medium, corrects them, obtains correct original information, and so on. For example, an error correction device is provided for recording and reproducing reproduced audio signals without deteriorating sound quality. □
FIG. 1 shows a conventional error correction device. In Figure 1,
1 is a demodulated data input terminal, 2 is a pointer terminal indicating an error, 3 is a correction circuit, 6 is a counter for counting error pointers, 7 is a correction circuit for determining and decoding the counted value. As shown in □ in Figure 2, in the rows of acoustic digital data Do to D3 within one block of data, there is a chi.
Since it is necessary to provide the keywords P and Q, there is a strong tendency that the correction circuit 5 and the condition determination and control 3-page circuit 7 become complicated.

However, conventional error correction circuits do not usually store error addresses, but instead simply delay the data and correct it when the error state is known, which can lead to errors. Words are not retained and the position must be determined again at the time of correction, and all words must be inspected, which has the disadvantage that the correction operation becomes complicated.

The present invention solves these conventional drawbacks,
The structure is such that the circuit can be simplified by providing a circuit that can effectively find only the word that has caused an error in the complicated control table.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The error correction device of the present invention will be described below with reference to drawings of embodiments. FIG. 3 shows an embodiment of the present invention,
In FIG. 3, 13 is a counter, and counter 16
After clearing the data, a word error grain inter is applied to the clock input terminal 1o to count errors. A memory 15 reads the value of the counter 16 using the number of errors as an address. Further, 14 is a decoder, which can obtain outputs corresponding to no error, 1 error word, etc. from the address of the counter 13.

This determines the condition and loads the word address in the first error block to the input end 9, thereby outputting the word address in the second error block to the output end 17 of the memory 16. can be obtained. This address and the start address of the block stored in the register 19 are sent to the ALU 18.
The error effective address can be obtained by adding .

A corrected recitation can be obtained by adding half of the check word P stored in the register 21 to the error word in addition to this effective address.

Further, 22 is a counter, and by connecting the output of this counter 22 to the address of the ROM 23, a sequence control circuit can be configured and a correction process can be executed.

As described in detail above, according to the present invention, the output of the first counter for counting the pointer indicating an error in the digital 5-digital information word is taken as an address, and the output of the first counter is used as an address, and the second A sequential control circuit configured to extract an error address within a block from a memory that stores the output of the counter as input data in accordance with the result of a judgment circuit that decodes the output of the first counter and determines an error state. This has the advantage that only the word in which an error has occurred can be found effectively without complicated control, thereby simplifying the circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional error correction device, Fig. 2 is a data structure diagram of one block in which an error check word and a data word are combined in the same device, and Fig. 3 is a block diagram showing an embodiment of the present invention. It is. 13, 16, 22---Counter, 14 a
ssess decoder, 16-...e memory, 19
,21...as register, 1s-*----AL
U, 23-*----*ROM0 Figure 1

Claims (1)

[Claims] a memory for storing as input data the output of a second counter for counting an address other than the address, and decoding the output of a first counter for counting a pointer indicating an error in the digital information word; a sequence control circuit that includes a determination circuit that determines an error state, retrieves an intra-block error address from the memory according to the result of the determination circuit; and a sequence control circuit that converts the intra-block address into an effective error address and detects an error word. 1. An error correction device comprising: an arithmetic operation unit for performing a check word operation, and the arithmetic operation unit is controlled by the order control circuit.