JPS58219828A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To detect a synchronizing signal and to protect synchronization for the lack of the synchronizing signal, by using a window output generated from a counter synchronously controlled by a synchronizing signal included in a digital input signal, a counter counting the window output and a gate circuit. CONSTITUTION:When an input signal consisting of one frame of N bits is inputted to a terminal 1 in each frame, a synchronizing signal detecting circuit 3 detects a synchronizing signal and outputs the signal to gate circuits 4, 10. An 1/N frequency divider 5 is cleared every time when the outputs of the gate circuits are turned to ''H'' and sends an output to an output terminal 9. The output of a window generator 6 is ''H'' during the period from the output of the frame synchronization controlling signal from the frequency divider 5 to several bits before and after the N-th bit of the succeeding output and inputted to the gate 4 through a selector 8. When the detecting circuit 3 is synchronized with the frequency divider 5, the output of the gate circuit 4 is turned to ''H'' and errors due to noises are prevented only when the output signal of the circuit 3 is entered into a window generated by the window generator 6. If the synchronizing signal is not detected because of dropout or the like, a counter 7 counts up the output of the window generator 6 and outputs the counted value to the divider 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronization circuit that can detect a synchronization signal included in a digital input signal and perform appropriate synchronization protection when the synchronization signal is lost.

[Technical background of the invention]

Recently, digital audio systems have been developed because they enable high-quality audio reproduction.

Digital audio systems include those that use magnetic tape and those that use disks.

2. Description of the Related Art As a method using a disk, a connoisseur disk (CD) system, in which digital information recorded on a disk is optically read out using a laser beam, has been developed and is about to be put into practical use.

In the case of a computer-ready disc, as is well known, the digital information is E F (eight to fourteen
) The signals are modulated, arranged in a frame in a predetermined format, and recorded on the disk. One frame includes a frame synchronization signal placed at the beginning, a plurality of audio information words, bits for error correction, and has a total of 588 channel bits. The synchronization signal is 24 channels 2. ) and has a specific change/4' turn that can be distinguished from other information.

The frame synchronization signal is used to generate a control signal for dividing frames and dividing data within a frame into predetermined units when reproducing audio information. For this reason, the playback device is provided with a synchronization signal detection circuit. Also,
A synchronization protection circuit is provided which is used in combination with the synchronization signal detection circuit and has a function of interpolating the synchronization signal in the event that the synchronization signal is lost due to scratches or scratches on the disk.

FIG. 1 shows a conventional synchronization circuit including a synchronization signal detection circuit and a synchronization protection circuit, and FIGS. 2A and 2B show timing diagrams for explaining the entire operation thereof.

In FIG. 1, a 1-frame N-bit input signal including a synchronization signal applied to input terminal 1 is applied to clock terminal 2 every frame, and contains black and white components included in the reproduced signal from the disk. The synchronization signal is applied to a synchronization signal detection circuit 3 together with a clock signal generated based on the output of the PLL circuit to be detected, and a synchronization signal is detected. The output of the synchronization signal detection circuit 3 is connected to the dart circuit 4.

The output of the dart circuit 4 is a 1/N signal that divides the clock signal.
It is connected to the clear terminal of the frequency divider (N-ary counter) 5.

The output of the 1/N frequency divider 6 is connected to a window generator 6, which output is connected to a counter 7 which is cleared by the output of the dart circuit 4.
connected to.

Selector 8 connects the output of window generator 6 or counter 7 to the dart circuit 40 control terminal. The output of IA frequency divider 5 is connected to output terminal 9.

In the synchronization circuit configured as described above, the synchronization signal detection circuit 3 detects the synchronization signal included in the input signal for each frame and outputs it to the dart circuit 4. The dart circuit 4 controls the supply of the synchronization detection signal of the synchronization signal detection circuit 3 to the 17N frequency divider 6 in accordance with the output of the selector 8 . The 1/N frequency divider 5 is cleared every time the output of the dart circuit 4 becomes ``H''.
A frame synchronization control signal is output to the output terminal 9 every N pins and g of the black and red signals. The window generator 6 sets its output to @H# for several bits before and after the Nth bit when the next frame synchronization control signal is supposed to be output after the branching unit 6 outputs the frame synchronization control signal tube, i.e. Create a window and selector 8
via f-) circuit 4? Make conductive. When synchronization is established between the synchronization signal detection circuit 3 and the branch divider 5, the selector 8 supplies the output of the window generator 6 to the dart circuit 4 to generate a window created by the synchronization signal of the previous frame. The output signal of the synchronization signal detection circuit 3 is supplied to the frequency divider 5. This prevents malfunctions caused by noise other than the true synchronization signal.

If the frame synchronization signal cannot be detected due to mud, goud, etc., the output of the synchronization signal detection circuit 3 and f
-) The output of circuit 4 is missing as shown in FIG. 2 (4). Even in this case, the output terminal 9 is
As shown in FIG. 2, an output signal appears every υN bits and 5s due to the division operation of the frequency divider 5. That is, the synchronization signal is interpolated. If no synchronization signal is detected, the counter 2 is not cleared and is counted every frame by the windowing force of the window generator 6. When the counter 7 reaches a preset count (for example, 4 frames), its output becomes ``H''.
When the output of selector BFi counter 7 becomes 'H', dart circuit 4'ff: opens. In this state, the first signal output from the synchronization signal detection circuit 3 is output from the f-) circuit 4 and clears the frequency divider 6 and counter 7. In this case, the frequency divider 5 is configured to output an output signal to the output terminal 9 when cleared.

However, as shown in FIG. 2(B), if the output of the synchronization signal detection circuit that starts after the output of the counter 7 becomes "H#" is noise, the frequency divider and the counter 7 is cleared. Therefore, the window generator 6 creates a window of several bits before and after the Nth bit from this noise. Therefore, even though the synchronization signal is correctly detected after the noise, the window generator 6 does not generate a window after the noise. Since the timing of the window output of the device 6 and the output of the synchronous signal detection circuit 3 do not match,
ff-) No output signal is output from the circuit 4. After the frequency divider 5 is cleared by noise, an erroneous synchronization control signal is output to the output terminal 9 every N bits by the 1/N frequency division operation. Then, the frequency divider 5 and the counter 7 can be synchronized only after the output of the counter becomes H# and a correct synchronization signal is detected.

[Problems with background technology]

As explained above, conventional synchronous circuits have a drawback in that when a synchronous signal is lost for some reason, an erroneous synchronous control signal is generated due to the influence of noise and the like.

[Purpose of the invention]

An object of the present invention is to provide a synchronous circuit configured to reduce the effects of noise and the like.

[Summary of the invention]

The 4-J circuit according to the present invention includes a synchronous signal detection circuit that receives a digital input signal including a synchronous signal for each frame and detects the synchronous signal, and a synchronous signal detection circuit that counts clock pulses and pulses and is synchronously controlled by the output of the synchronous signal detection circuit. a first counter that generates a synchronization control signal; a window generator that is controlled by the counter; and a window generator that outputs the output of the synchronization signal detection section to the counter that is controlled by the window output generated by the window generator. The first dart circuit to be connected and the window output generated by the window generator are counted, and when a predetermined value is reached, the output state is changed and all first dart circuits are controlled and synchronized regardless of the output of the window generator. a second counter that connects the output of the signal detection circuit to the first counter; and a second counter that connects the output of the signal detection circuit to the second counter under the control of the window output of the window generator A second gate circuit is provided which is connected to the synchronous signal detection circuit and clears the second counter by the output signal of the synchronization signal detection circuit.

[Embodiments of the invention]

First, an overview of an optical digital audio disc playback device to which an embodiment of the present invention is directed will be described.

As shown in FIG. 3, digital information recorded on a disk 113 mounted on a turntable 121 driven by a disk motor 111 is reproduced by an optical pickup device 114. The optical pickup device transfers the radar beam from the semiconductor laser 114a to the beam sinter RXB and the objective beam! 114 e to the recording surface of the disk 113 to produce a predetermined change Ml.
(EFM) and a bit representing PCM digital data including an audio information signal with interleaving is guided to a four-split photodetector 114d via an objective lens 114a and a beam sinter 114bk.
It is configured to obtain two reproduction signals. The pickup device is linearly driven in the radial direction of the disk 113 by a feed motor 115.

The four output signals of the 4-split photodetector 114d are supplied to the matrix circuit 116 and subjected to predetermined matrix calculation processing, thereby generating a focus error signal F,) racking error signal T and a high frequency signal (modulated digital information). ) separated into RF.

The focus error signal F is sent to the focus search circuit 110.
is supplied to the focus servo system FS of the optical pickup device 114 along with the focus search signal from the optical pickup device 114.

In addition, the tracking error signal T is transmitted to the pickup device 114, along with a search control signal given from the system controller 117, which will be described later.
and is also supplied to the feed motor 116 to perform linear tracking control of the pickup device.

The high frequency signal RF is used as the main data component by the reproduction processing system 118.
is supplied to In the reproduction processing system, the modulated digital information RF is guided to a waveform shaping circuit 120 controlled by a slice level (eye pattern) detector 119, and only digital data components from which analog components have been removed are extracted. The data component is supplied to the PLL type synchronous clock regeneration circuit 121 and the edge detector 122a of the first signal processing system 122. The synchronous clock signal from the synchronous clock regeneration circuit 121 is the synchronous signal of the first signal processing system 122. The signal is supplied to a separating black and white signal generation circuit 122b to generate a synchronizing signal separation black and white signal.

The edge detector 122a converts EFM data (NRZ) into N
Edge (change point) of RZI modulated high frequency signal RF
It functions to detect and convert into the original EFM data. The output signal of the edge detector 122a is the synchronization signal detection circuit 1
22c, the synchronizing signal is separated using a synchronizing signal separation clock generated based on the synchronizing clock extracted by the synchronizing clock reproducing circuit 121 from the high frequency signal RF of NRZ I, and the demodulating circuit 122d
Each data is demodulated using the original number of bits.

The synchronization signal separated by the synchronization signal detection circuit 122c is supplied to the input data processing timing signal generation circuit 122f together with the synchronization signal separation clock via the synchronization signal protection circuit 122e. The synchronization signal protection circuit 122e has a function of interpolating the synchronization signal in order to prevent malfunction when an erroneous detection occurs in the synchronization signal detection circuit 122c.

The demodulated signal output from the demodulation circuit 122d is supplied to the input/output control circuit 123a of the second signal processing system 123, which will be described later, via the data bus input/output control circuit 122qf, and the control signal and display signal, which are subcodes, are The components are supplied to a control display processing circuit 122h and a subcode processing circuit 122I. Subcode processing circuit 12
The subcode data subjected to necessary error detection and correction in step 21 is supplied to the system controller 117 via the system controller interface circuit 122qf.

The system controller 117 is a microcomputer,
It is equipped with an interface circuit and a driver integrated circuit, and controls the playback device to a desired state according to commands given by the control switch 124, and also outputs the above-mentioned subcodes (for example, index information of played songs).
It is displayed on the display 125.

The timing signal from the timing signal generation circuit 122f is sent to the input/output control circuit 12 via the data selection circuit 122j.
Automatic frequency control (AFC) and automatic phase control are applied to the frequency detector 122 and the phase detector 122t to drive the disk motor 111 in a constant linear velocity (CLD) manner via the force modulator 122mf. (APC) 'i do. The phase detector 122t is supplied with a system clock generated by a system clock generation circuit 122p driven by a crystal oscillator 122n.

The demodulated data that has passed through the input/output control circuit 123* of the second signal processing system 123 is sent to a four-drome detector 123b for error detection and correction.

Error pointer control circuit 1 ;! 3 e, correction circuit 1
23d and a data output circuit 12.9e f, which undergoes necessary error correction, dinning leave, error correction, etc., to a digital-to-analog (D/A) converter 126.
is supplied to The external memory control circuit 123f cooperates with the data selection circuit 122j to control the external memory 127 in which data necessary for correction is written, and inputs the data necessary for correction via the input/output control circuit 123IL.

The timing control circuit 123g receives the system clock signal from the system clock generation circuit 122p and generates timing control signals necessary for error correction and correction and D/A conversion.

The muting control circuit 123h is the output from the error pointer control circuit 123c or the system controller 1.
The output circuit 123 is activated at the time of error correction and at the start and end of operation of the playback device based on the control signal given through the output circuit 17.
Muting is performed by controlling e.

The audio signal converted into analog by the D/A converter 126 is passed through a low pass filter (LPF) 22g and an amplifier 12.
The speaker 130 is driven through the 9.

Hereinafter, the synchronous circuit fc according to the present invention will be described in Figs. 4 and 5 (
This will be explained with reference to 4) and (B).

FIG. 4 shows a synchronous circuit according to the present invention, in which the same parts as in the conventional synchronous circuit shown in FIG. 1 are given the same reference numerals. This synchronous circuit is constructed by adding a dart circuit 10 to a conventional synchronous circuit. This date circuit is controlled by the window output of the window generator 6 and is provided to clear the counter 7 by the output signal of the synchronization signal detection circuit 3.

In such a synchronization circuit, when one frame of N-bit input signals including a synchronization signal is applied to the input terminal 1 for each frame, the synchronization signal detection circuit 3 detects the synchronization signal included in the input signal for each frame. The detection signal is sent to the dirt circuit 4.
and output to 1θ. The 1/N frequency divider 5 is cleared every time the output of the dart circuit 4 becomes 'H' and sends a synchronization control signal to the output terminal 9.The frequency divider 5 outputs the frame synchronization control signal from the window generator 6. After the output, the next frame synchronization control signal is supposed to be output between several pits before and after the Nth bit.
If H' is not present, this window output is applied to the r-) circuit 4 via the selector 8. When normal synchronization is established between the synchronization signal detection circuit 3 and the frequency divider 5, the output of the start circuit 4 will be activated only when the output signal of the synchronization signal detection circuit 3 enters the window created by the window generator 6. When the counter 7 reaches 'H', it prevents errors caused by noise other than the synchronization signal.If the counter 7 is properly synchronized, the counter 7 detects the frame by the output signal of the synchronization signal detection circuit 3 via the f-) circuit 10. Cleared every time.

If the frame synchronization signal cannot be detected due to dropout or other reasons, or if the synchronization is lost, the counter 7 will not be cleared by the output signal of the f-to circuit 1θ and will be counted up for each frame by the window generator 6. be done.

When the counter 7 counts the preset number of frames (for example, 4 frames), the output is sent to @H'' as shown in FIG. The dart circuit 4 is opened, and the output of the sync signal detection circuit 3 is connected to the frequency divider 5. While the output of the counter 7 is "H#", the sync signal is detected by the sync signal detection circuit 3. In this case, the first output signal clears the frequency divider 5. Therefore, the next output signal enters within the window created by the window generator 6, thereby clearing the frequency divider 5 and the counter 7. After this, when the synchronization signal detection circuit 3 normally detects the synchronization signal, the frequency divider 5 and the counter 7 are cleared for each frame via the gate circuits 3 and 10, respectively.

If, as shown in Figure 5 (1'l), the first output signal of the synchronization signal detection circuit 3 is noise after the output of the counter 7 reaches 'H', then the synchronization signal is detected normally. In this case, the noise output clears the divider 5 but does not clear the counter 2. When the synchronization signal detection circuit 3 successively outputs the synchronization signal detection signal after the noise output, the first The frequency divider 5 is cleared by the detection signal, but since the f-) circuit 10 is closed, the counter 7 is cleared.
is not cleared. At the timing when the second detection signal is output from the synchronization signal detection circuit 3, the signal gate circuit 10 is opened by the output of the window generator 6. Therefore, the frequency divider 5 and the counter 7Fi are connected to the dirt circuit 4 and It is cleared by the second detection signal via 10.

Therefore, from then on, the dart circuit 4 is opened every frame by the output of the window generator 6, and the synchronization between the synchronization signal detection circuit 3 and the frequency divider 5 is restored.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a synchronization circuit that can quickly recover synchronization even when affected by noise and has reduced effects of noise and the like.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of a conventional synchronous circuit, Fig. 2) and (T'') are timing diagrams for explaining the operation of the synchronous circuit of Fig. A block diagram of a usable optical digital audio disc playback device, FIG. 4 is a diagram showing the configuration of a synchronization circuit according to an embodiment of the invention, and FIGS. 5(A) and (B) are similar to FIG. This is a timing diagram for explaining the operation of the synchronization circuit. Wang P. Patent Attorney Patent Attorney Takehiko Suzue 1.1 Figure 1 Procedural Amendments Showa 8.-23 Director General of the Patent Office Kazuo Wakasugi Dear ■, Case Indication Special 111! +1 1985-10282 JJ No. 2, Name of Invention Synchronous Circuit 3゜Relationship with the Nagisa Case to Amend Special W (Applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent 6, Specification Subject to Amendment 7, Statement of Contents of Amendment No. 19, Next to line 7, insert the following: 1...Input terminal, 2...Clock terminal, 3゛° synchronization signal Detection circuit, 4, 10...271 circuit, 5... External frequency divider (first counter), 6... Window generator, 7...
・Counter (second counter), 8...Selector, 9
...Output terminal.

Claims (1)

[Claims] A synchronous signal detection circuit that receives a digital input signal containing a synchronous signal for each frame and detects the synchronous signal, and a synchronous signal detection circuit that counts clock noculus and is synchronously controlled by the output of the synchronous signal detection circuit to generate a synchronous control signal. a window generator that generates a solution output under the control of the counter; and a window generator that generates a solution output under the control of the counter; and a window generator that generates an output of the synchronization signal detection circuit under the control of the solution output generated by the window generator. A first dart circuit connected to and controlled synchronously, a second counter that counts the solution output of the window generator and changes the output state when it reaches a predetermined value, and a second counter that is controlled by the solution output of the window generator. Connect the output of the synchronization signal detection circuit to the second counter and generate the synchronization signal! a second e-) circuit that clears a second counter every time an output signal is output from the detection circuit; and means for controlling the circuit and connecting the output of the synchronous signal detection circuit to the first counter.'! ! f-Featured synchronous circuit.