JPS5921107B2 - PCM recording/playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PCM recording and reproducing apparatus that eliminates loss of digital signals during splicing editing.

As an example of the application of conventional digital recording technology, PC
A recording/reproducing device based on the M method is known.

Among these, a fixed head type PCM recording/reproducing apparatus using magnetic tape and having multi-tracks has the advantage of not only a simple mechanism but also splicing editing. Editing is essential, especially in PCM recording and playback devices for audio signals, and splicing editing is especially
It has the advantage of being possible with just one device. Splicing editing
This is done by pasting and joining the necessary parts with splicing tape, but there are problems such as deterioration of the recording condition near the cut surface due to cutting the magnetic tape, misalignment of the angle during pasting, gaps, etc.
Due to elongation of the splicing tape, deterioration of contact with the head during tape running, etc., signal loss occurs when the spliced area is reproduced.

This signal loss cannot be completely eliminated even when splicing is performed using a jig, and when splicing is normally performed by hand, the signal is lost for several milliseconds. Even if the signal recording speed is about 1 Mbps (bits per second), this amount is several thousand bits, which is much larger than the several tens of bits that normally occur due to scratches or dust on the magnetic tape. For this reason, dropout correction methods are ineffective, and when converted to the original analog signal, noise is generated, and especially in the case of acoustic signals, the sound quality is significantly impaired. This invention was made to eliminate such drawbacks, and is a PCM that eliminates signal loss due to splicing editing by delaying the reproduced data for a certain period of time in memory and filling in the missing data from memory at the splicing editing point. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention, which aims to provide a recording and reproducing apparatus, will be described below by taking a fixed head type PCM recording and reproducing apparatus using a frame distribution method.

FIG. 1 is a recording diagram of signals recorded on a magnetic tape using the frame distribution method. As shown in the figure, one frame consists of a frame synchronization bit, a data bit, and a check bit. The data bits are usually allocated for several samples, and the check bits are codes with high burst error detection ability, such as CRCC (Cyclic Redundant).
ancyCheckCharacter) code, etc. are assigned additional bits. FIG. 2 is a signal system diagram showing one embodiment of the present invention.

In FIG. 2, 1 is a reproduction signal input terminal, 2 is a frame synchronization separation circuit, 3 is a code check circuit, 4 is an edit detection circuit, 6 is a memory circuit, 5 is a control circuit, 69 is a capacitance detection circuit, and 70 is a Speed control signal generation circuit 7, 68 are output terminals. A reproduced signal input from each track to an input terminal 1 is separated into frame synchronization bits by a frame synchronization separation circuit 2, and the speed of parallel signals for the number of multi-tracks is converted into one serial signal. This serial signal is sent to the memory circuit 6 after checking whether the data is erroneous in the code check circuit 3. On the other hand, the erroneous retrieval output is sent to the edit detection circuit 4, and the presence or absence of splicing editing is detected. When splicing editing is detected, an editing detection signal is sent to the control circuit 5.
Controls not to write data to the memory 6 circuit.
Then, when the editing part is finished, data is written as usual. On the other hand, data is read from the memory circuit continuously without interruption, and data is sent to the output terminal 7. Also, capacitance detection circuit 6
The amount of memory in the memory circuit 6 is detected at 9, and a speed control signal generation circuit 70 generates a speed control signal, which is supplied from an output terminal 68 to the speed control circuit. Each circuit will now be described in detail.

FIG. 3 is a signal system diagram of the edit detection circuit 4, and FIG. 4 is a signal waveform diagram thereof. In the figure, 8, 9, 10 are input terminals 11, 12, 13 are D flip-flops, 14 is an inverter, 15 is an AND circuit, 16 is an NC circuit, 17 is an R-
S flip-flop 18 is an output terminal. The error check output a from the input terminal 8 is delayed in three stages by the clock b from the input terminal 9 through three D flip-flops 11, 12, and 13, and is input to an AND circuit 15 and an NCR circuit 16. The clock C from the input terminal 10 and the inverted output sent to the inverter 14 become inputs to the AND circuit 15 and the NCR circuit 16, respectively, and the R-S flip-flop 1
7 sends the edit detection signal d to the output terminal 18. Here, in FIG. 4, the dotted line portion of the error check output a indicates that an error has been detected. This edit detection circuit detects when three consecutive erroneous retrieval outputs a occur, that is, when three consecutive frames of serial data signals are erroneously generated. In the frame distribution method, this means that there is an error in the width direction of the magnetic tape by three tracks, but errors in the width direction are a phenomenon unique to splicing editing, and this seems to be an adequate detection method. FIG. 5 is a signal waveform diagram of the memory circuit 6 and control circuit 5.
FIG. 6 is the signal system diagram.

In the figure, 19, 20, 21, 42, 45, 47 are input terminals, 22, 29 are counter circuits, 23, 24, 31 are T flip-flops, 25, 26, 27, 28, 32,
33, 34, 35, 36, 37, 48 are AND circuits, 3
8, 39, 40, 41 are decoder circuits, 43, 46, 7
1 and 72 are output terminals, and 44 is a memory. Input terminal 1
A frame signal for writing is sent from input terminal 9, and a frame signal for reading is sent from input terminal 21, respectively.
The counter circuit counts the capacity of the memory 44,
The frequency is divided by T flip-flops 23, 24, 30, 31 and AND circuits 25, 26, 27, 28 and 34, 35, 3
At steps 6 and 37, gates for timing required for each memory are created. As shown in FIG. 5, the signal waveform is created by ANDing the reset pulse i from the input terminal 20 and the control gate f in order to keep the phase relationship between the control gates E, f and G, h constant.
The input of the circuit 32 and its output and the control gate e are ANDed.
It is used as an input to the circuit 33. And AND circuit 32,3
By resetting the T flip-flops 30 and 31 with the outputs of 3, the phase relationship between writing and reading to the memory 44 is maintained. Assume that the edit detection signal d is input here from the input terminal 47. τ is d in Figure 4
This is the inverted signal of The write frame signal from the input terminal 19 is A while the edit detection signal d is at the 0 level.
The ND circuit 48 prevents the signal from being input to the counter circuit 22. Therefore, as shown by control gates E and f in FIG. 5, the signal is expanded in time in the middle. However, if this temporal expansion is within the capacity of one memory, it will be completely absorbed,
The data is sent to the output terminal 45 without any loss. Considering the memory capacity here, considering the signal loss time Ms due to splicing editing for a 1 Mbps signal, 5 ms corresponds to 5 kbit, which can be easily configured based on recent IC memory conditions. In addition, 1 in Figure 5 F and h
244 represents four numbers of the memory 44, and indicates that writing or reading is performed at each timing.

The above configuration is effective for one splicing edit location, but if there are two or three splicing edit locations, the data stored in the memory 44 may become O. .

Therefore, if the amount of data stored in the memory 44 is detected and the amount of data is controlled to be kept constant by increasing the running speed of the magnetic tape when the amount of data falls below a certain amount, splicing editing can be performed many times. becomes possible. FIG. 7 shows a signal waveform diagram of the capacity detection circuit 69 for detecting the amount of data in the memory, and FIG. 8 shows a signal system diagram. In Figure 8, 4
9, 50 are input terminals, 51, 52, 53, 54 are one shot multi, 55, 56 are AND circuits, 57 is R-S
Flip-flop 58 is an output terminal. Input terminal 4
A control gate h1 for reading and a control gate f for writing enter from 9 and 50, respectively, and one-shot multipliers 51 and 53 are activated at each rising edge to form gates j and k. The output l obtained by passing these two gates through the AND circuit 55 is the output from the R-S flip-flop 57.
This is the glue set input. Then, the one-shot multi 52 is operated at the falling edge of gate j, and the one-shot multi 54 is operated at the falling edge of gate k, so that gates N and m are activated, respectively.
is created. The output 0 obtained by passing these two gates through an AND circuit 56 becomes a set input to an R-S flip-flop 57. When the edit detection signal d arrives, the write control gate f is time-expanded by the time d is at the 1 level, as shown in FIG. So Gate JI:. The phase of K, m(5n is shifted, and the set pulse O is created. By detecting the phase shift of the control gates F, h in this way, the capacity of the memory is detected. Then, the R-S flip-flop 57 sends a speed control signal p to an output terminal 58. Next, the running speed of the magnetic tape is adjusted.

Speed control of the reproduction system is performed by controlling the phase of the control signal from the reproduction signal and the control signal from the reference clock. Therefore, if the control signal from the reference clock is changed, the running speed will also change. At this time, it is sufficient to synchronize and change the control signals within a range that does not disrupt the phase control. FIG. 9 shows a signal system diagram of the speed control signal generation circuit 70 that changes the control signal from the reference clock. In the figure, 59 and 66 are input terminals, 6
0 is an M frequency divider circuit, 61 is an (M-1) frequency divider circuit, 62,6
3 is a control signal generation circuit, 64 is a selection circuit, and 65 is M・(
M-1) Frequency dividing circuit, 67 is a D flip-flop, and 68 is an output terminal. The reference clock signal input from the input terminal 59 is sent to the M frequency divider circuit 60 and the (M-1) frequency divider circuit 61.
The frequency is divided by , and two types of control signals are generated by control signal generation circuits 62 and 63. The speed control signal p from the input terminal 66 is input to the M. (M-1) Synchronized with the clock from the frequency dividing circuit 65 and sent to the selection circuit 64. The selection circuit 64 selects the output from the control signal generation circuit 62 when the output signal of the D flip-flop 67 is at the ``0'' level, and selects the output from the control signal generation circuit 63 when it is at the ``1'' level. The control signal obtained in this way is supplied to the speed control circuit from the output terminal 68, and
The traveling speed will be adjusted. As described above, according to the present invention, an output signal can be continuously supplied by compensating for signal loss due to splicing editing from memory.

[Brief explanation of the drawing]

FIG. 1 is a signal recording diagram recorded on a magnetic tape using the frame distribution method, FIG. 2 is a signal system diagram according to an embodiment of the present invention, FIG. 3 is a signal system diagram of the edit detection circuit 4, and FIG.
The figure shows the signal waveform diagram, Figure 5 shows the signal waveform diagram of the memory circuit and control circuit, Figure 6 shows the signal system diagram, Figure 7 shows the signal waveform diagram of the capacitance detection circuit, and Figure 8 shows the signal system diagram. , FIG. 9 is a signal system diagram of the speed control signal generation circuit. In the figure, 4 is an edit detection circuit, 5 is a control circuit, 6 is a memory circuit, 69 is a capacitance detection circuit, and 70 is a speed control signal generation circuit.

Claims (1)

[Claims] 1. In a PCM recording and reproducing device that samples an analog signal, pulse encodes each sampled value, and records it on a medium, means for storing data in a certain amount of memory and then reading it out during reproduction, and a splicing editing part. A PCM comprising a means for detecting a signal and a means for compensating for signal loss due to splicing editing with data stored in a memory.
Recording and playback device. 2. PCM recording and reproducing according to claim 1, comprising means for detecting the amount of data stored in the memory, and means for controlling the traveling speed of the medium to maintain a constant amount of data stored in the memory. Device.