JPH0227754B2 - DOKISHINGOKENSHUTSUKAIRO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronization signal detection circuit for detecting a synchronization signal having a specific change pattern included in a digital modulation signal.

[Technical background of the invention]

Recently, digital audio systems have been developed because they enable high-quality audio reproduction. Digital audio systems include those that use magnetic tape and those that use disks. A compact disc (CD) system was developed that uses a disc to optically read out the digital information recorded on the disc using a laser beam.
It is about to be put into practical use.

In the case of a compact disc, digital information is arranged in frames in a predetermined format and subjected to modulation (EFM) before being recorded on the disc.
One frame includes a frame synchronization signal placed at the beginning, a plurality of audio information words, and error correction bits, and is composed of 588 channel bits as a whole. The synchronization signal consists of 24 channel bits and has a specific variation pattern. That is, the synchronization signal has first to third changing points,
The interval between the first and second change points corresponds to 11 bits, and the interval between the second and third change points corresponds to 11 bits.

The frame synchronization signal is used to generate a control signal for dividing frames and dividing data within a frame into predetermined units when reproducing audio information. For this reason, the playback device is provided with a synchronization signal detection circuit.

FIG. 1 shows a conventional synchronizing signal detection circuit, and FIG. 2 shows a waveform diagram for explaining its operation.

This synchronous signal detection circuit is composed of D-flip-flop circuits 1 and 2, an exclusive OR gate 3, an N+1 stage shift register 4, an inverter 5 connected to the output of a predetermined stage of the register 4, and a NOR circuit 6. The D-flip-flops 1 and 2 and the exclusive OR gate 3 constitute an edge detector, which detects the change point of the digital modulation signal read from the disk and outputs a reproduced signal. This reproduction signal is applied to the shift register 4 and
It is also supplied to the EFM demodulation circuit.

FIG. 2A shows the input signal applied to the D-flip-flop circuit 1, which input signal includes a frame synchronization signal having a specific variation pattern. This frame synchronization signal has first, second, and third changing points, and if T is one period (1 bit time) of the clock signal shown in FIG. 2B, the first and second changing points are Both the interval and the interval between the second and third change points are set to 11T.

FIGS. 2C and 2D show the waveforms of the output signals at the outputs Q ₁ and Q 2 of the D-flip-flop circuits 1 and ₂ , respectively, and there is a phase difference of 1T between the output signals. Therefore, an output signal A of pulses corresponding to the change point of the input signal as shown in FIG. 2E is obtained from the exclusive OR gate 3. When a portion of the output signal A corresponding to the synchronization pattern is input to the shift register 4, a synchronization signal detection pulse is obtained from the NOR circuit 6 as shown in FIG. 2F.

[Problems with background technology]

In such a synchronization signal detection circuit, as the period (NT) of the synchronization signal increases, the number of shift register stages and the number of input terminals of the NOR circuit must be increased, which causes the problem of an increase in the number of elements. arise. Furthermore, as the number of elements increases, a problem arises in that the delay time between gates cannot be ignored.

[Purpose of the invention]

An object of the present invention is to provide a synchronization signal detection circuit that can be configured with a small number of elements.

[Summary of the invention]

In order to receive a digital input signal containing a synchronization signal having a specific change pattern and detect the synchronization signal, the synchronization signal detection circuit of the present invention counts clock pulses and counts edges corresponding to change points (edges) of the input signal. A counter that is cleared by the detection pulse and a NAND gate that receives a predetermined output of this counter and the edge detection pulse as inputs are provided to check the interval between the change points of the input signal and calculate the interval between the change points of the input signal. When corresponds to the interval between one change point of the synchronization signal and the next change point, it is detected that a part of the synchronization signal has been input. A reset-priority flip-flop comprising a D-flip-flop circuit is provided which is set by the edge detection pulse and reset by the output of the NAND gate;
When the gate detects that a part of the synchronizing signal has been input, it is reset by the output of the NAND gate, thereby storing that a part of the synchronizing signal has been input. A NOR circuit is provided that receives the output of the NAND gate and the output of the reset-priority flip-flop circuit, and when the counter and the NAND gate detect that another part of the sync signal is input, the sync signal is output. Generates a detection pulse.

〔Effect of the invention〕

The synchronous signal detection circuit of the present invention can be configured using a counter with a small number of bits, a logic gate with a small number of inputs, and a D-flip-flop circuit, so the number of elements can be reduced compared to a conventional circuit using a shift register. . Delay time can also be shortened by reducing the number of elements.

[Embodiments of the invention]

First, an overview of an optical digital audio disc playback device to which an embodiment of the present invention is directed will be described.

As shown in FIG.
The digital information recorded on the disk 113 mounted on the turntable 121 driven by the optical pickup device 114 is reproduced by the optical pickup device 114. The optical pickup device irradiates the recording surface of the disk 113 with a laser beam from a semiconductor laser 114a through a beam splitter 114b and an objective lens 114c, and generates an audio information signal in a form with predetermined modulation (EFM) and interleaving. The reflected light from the pit representing the PCM digital data including the objective lens 114c,
The beam is guided to a four-split photodetector 114d via a beam splitter 114b to obtain four reproduced signals. The pick-up device is feed motor 1
15 linearly drives the disk 113 in the radial direction.

The four output signals of the four-split photodetector 114d are supplied to the matrix circuit 116 and subjected to predetermined matrix calculation processing, thereby generating a focus error signal F, a tracking error signal T, and a high frequency signal (modulated digital information). Separated into RF.

The focus error signal F is supplied to the focus servo system FS of the optical pickup device 114 together with the focus search signal from the focus search circuit 110. Further, the tracking error signal T is supplied to the tracking servo system TS of the pickup device 114 together with a search control signal given from a system controller 117, which will be described later, and is also supplied to the feed motor 115 to perform linear tracking control of the pickup device. .

The high frequency signal RF is supplied to the reproduction processing system 118 as the main data component. In the re-output processing system, the modulated digital information RF is guided to a waveform shaping circuit 120 controlled by a slice level (eye pattern) detector 119, and only digital data components from which analog components have been removed are extracted. The data component is
The signal is supplied to a PLL type synchronous clock regeneration circuit 121 and an edge detector 122a of the first signal processing system 122.

The synchronous clock signal from the synchronous clock regeneration circuit 121 is supplied to the synchronous signal separation clock generation circuit 122b of the first signal processing system 122 to generate a synchronous signal separation clock.

The edge detector 122a functions to detect edges (change points) of the high frequency signal RF in the form of NRZI modulated EFM data (NRZ) and convert it into the original EFM data. The output signal of the edge detector 122a is guided to a synchronization signal detection circuit 122c,
The synchronization signal is separated using the synchronization signal separation clock generated based on the synchronization clock extracted from the high frequency signal RF of NRZI by the synchronization clock regeneration circuit 121, and the demodulation circuit 122d
Each data is demodulated using the original number of bits.

The synchronization signal separated by the synchronization signal detection circuit 122c is supplied to the input data processing timing signal generation circuit 122f together with the synchronization signal separation clock via the synchronization signal protection circuit 122e.
The synchronous signal protection circuit 122e is the synchronous signal detection circuit 1
22c has a function of interpolating the synchronization signal in order to prevent malfunction when an erroneous detection occurs.

The demodulated signal output from the demodulation circuit 122d is sent to the input/output control circuit 12 of the second signal processing system 123, which will be described later, via the data bus input/output control circuit 122g.
3a, and the control signal and display signal components, which are subcodes, are supplied to the control display processing circuit 122h and the subcode processing circuit 122.
i. The subcode data subjected to necessary error detection and correction by the subcode processing circuit 122i is supplied to the system controller 117 via the system controller interface circuit 122g.

The system controller 117 is equipped with a microcomputer, an interface circuit, and a driver integrated circuit, and controls the playback device to a desired state according to commands given by the control switch 124, as well as controlling the above-mentioned subcodes (for example, when playing a song). index information) is displayed on the display 125.

The timing signal from the timing signal generation circuit 122f controls the input/output control circuit 122g via the data selection circuit 122j, and is also applied to the frequency detector 122k and phase detector 122l to drive the disk motor 111 via the PWM modulator 122m. Performs automatic frequency control (AFC) and automatic phase control (APC) for constant linear velocity (CLV) driving. A system clock generated by a system clock generation circuit 122p driven by a crystal oscillator 122n is supplied to the phase detector 122l.

Input/output control circuit 12 of second signal processing system 123
The demodulated data passed through 3a is sent to a syndrome detector 123b for error detection and correction, an error pointer control circuit 123c, and a correction circuit 123.
The data is supplied to the digital-to-analog (D/A) converter 126 via the data output circuit 123e and the data output circuit 123e after undergoing necessary error correction, deinterleaving, error correction, and other processing. External memory control circuit 123
f is an external memory 127 in which data necessary for correction is written in cooperation with the data selection circuit 122f.
is controlled to take in data necessary for correction via the input/output control circuit 123a.

Timing control circuit 123g receives the system clock from system clock generation circuit 122p and generates timing control signals necessary for error correction and correction and D/A conversion.

The muting control circuit 123h controls the output circuit 123e to perform muting based on the output from the error pointer control circuit 123c or the control signal given via the system controller 117, at the time of error correction and at the start and end of operation of the playback device. Let's do it.

The audio signal converted into analog by the D/A converter 126 is passed through a low pass filter (LPF) 128,
A speaker 130 is driven via an amplifier 129.

Hereinafter, a synchronization signal detection circuit according to an embodiment of the present invention, which is directed to detecting a synchronization signal having a change pattern as described above, will be explained with reference to FIGS. 4 and 5.
Let me explain with reference to the diagram.

FIG. 4 shows a synchronizing signal detection circuit, and FIG. 5 shows a timing diagram explaining its operation. In FIG. 4, an input terminal ₁₁ receiving a synchronizing signal having a predetermined variation pattern shown in FIG.
Q ₁ is connected to input D ₂ of D-flip-flop circuit 13. The outputs Q ₁ and Q ₂ of flip-flop circuits 12 and 13 are connected to the input of exclusive OR gate 14. A clock input terminal 15 receives the clock signal shown in FIG. Flip-flop circuits 12, 13 and exclusive OR gate 14 constitute an edge detector as described above.

A 4-bit counter 16 is provided for counting the clock signal applied to terminal 15. The outputs 2 ¹ , 2 ³ of this counter 16 and the exclusive OR gate 14
The output of is connected to the input of a three-input NAND gate 17. The output of exclusive OR gate 14 is also connected to the clear terminal CL of counter 16. A carry terminal Ca of the counter 16 is connected to an enable terminal EN via an inverter 18.

A D-flip-flop circuit 19 is provided, and the output Q ₃ and the output of the exclusive OR gate 14 are ORed.
Connected to the input of gate 20. The output of this OR gate 20 and the output of NAND gate 17 are ANDed.
It is connected to the input of gate 21, and its output is connected to input _D3 of flip-flop circuit 19. A clock terminal CK of flip-flop circuit 19 is connected to clock input terminal 15. D-flip-flop circuit 19, OR gate 20 and AND gate 21 constitute a reset priority type flip-flop circuit.

Output _Q3 of flip-flop circuit 19 and NAND
The output of gate 17 is connected to the input of NOR circuit 22, and its output is connected to output terminal 23.

The operation of the synchronizing signal detection circuit configured in this way will be explained with reference to the timing diagram of FIG. 5. When an input signal having the synchronization pattern shown in FIG. 5A is applied to the input terminal 11, the signals shown in FIGS. 5c and 5D are obtained from the outputs Q ₁ and Q ₂ of the flip-flop circuits 12 and 13. Since there is a phase difference of one period (T) of the clock signal between the outputs Q ₁ and Q ₂ , the output A of the exclusive OR gate 14 has a pulse with a pulse width of 1T as shown in FIG. can get. Each pulse of the exclusive OR gate 14 is obtained corresponding to an edge (change point) of the input signal, thereby converting the NRZI signal into an NRZ signal. Even if the input signal is inverted, the output A of the exclusive OR gate remains unchanged.

4-bit counter 16 is exclusive OR gate 14
It is cleared each time the output A of the circuit becomes "H", and the number of clocks until the output A becomes "H" next time is counted. The first changing point of the synchronization signal (“L”
→ “H”) and the third change point (“L” → “H”) is NT (N = 22 in the example),
The output of counter 16 is N/2-1 (when N=22
10) and output A is “H”, Fig. 5 F
As shown in the figure, the output B of the NAND gate 17 is “L”
become. In other words, only when the interval from when the output A of the exclusive OR gate 14 becomes "H" to when it becomes "H" corresponds to N/2 clocks.
The output B of the NAND gate 17 becomes "L".

If there is an interval of 15T or more from when the output A of the exclusive OR gate 14 becomes "H" until it becomes "H" again, the output of the carry terminal Ca of the counter 16 changes from "L" to "H". Since the enable terminal EN becomes "L", the counter 16 stops counting the clock.

The flip-flop circuit 19, OR gate 20 and AND gate 21 are set when A is "H", and B
It constitutes a reset-prioritized flip-flop circuit in which the output is reset at "L". Therefore,
Corresponding to the second change point (from "H" to "L") of the synchronizing signal, the output _Q3 of the flip-flop circuit 19 becomes "L" as shown in FIG. 5G. This means that the input of a part of the synchronization pattern has been memorized.

Then, when the output B of the NAND gate 17 becomes "L" in response to the detection of the third changing point of the synchronization signal, the NOR circuit 22
The output becomes "H", and a synchronizing signal is detected.

In the embodiment shown in FIG. 4, the period NT of the synchronization pattern to be detected is 22 bit times, so a 4-bit counter 16 is sufficient. The relationship between the number N of bits of the synchronization pattern and the number B of bits of the counter is 2 ^B > N/2.

Therefore, by configuring a bit number counter and (N/2-1) detection circuit that satisfy this relationship, the detection circuit can be configured in the same manner as shown in FIG. 4 for any period of synchronization pattern.

Although the synchronization signal detection circuit described so far is aimed at detecting synchronization patterns with a duty factor of 50%, synchronization patterns with a duty factor other than 50% also change the input of the NAND gate 17. It can be similarly detected by

In Figure 6, the period is 22T, but the period is 12T and
A detection circuit for a synchronization signal with a duty of 10T is shown. That is, when the output A of the exclusive OR gate 14 is "H" and the output of the counter 16 is "11" or "9", the NAND gate 17
The outputs “2 ⁰ ” and “2 ³ ” of the counter 16 are directly connected to the NAND gate 1 through the inverter 24a, and the output “2 ² ” is connected to the NAND gate 1 through the inverter 24a so that the output B of the counter 16 becomes “L”.
7 input.

According to such a configuration, as shown in the timing diagram of FIG. 7, especially as shown in FIG. 7D, the synchronization pattern is
The 12T section is detected when the output of the counter 16 becomes "11", and the 10T section is detected when the output of the counter 16 becomes "9".

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional sync signal detection circuit, FIG. 2 is a timing diagram thereof, and FIG. 3 is a block diagram of an optical digital audio disc playback device to which the sync signal detection circuit of the present invention can be applied. , FIG. 4 is a diagram showing the configuration of a synchronizing signal detection circuit according to an embodiment of the present invention, FIG. 5 is a timing diagram thereof, FIG. 6 is a diagram showing a modified example of the synchronizing signal detecting circuit of the present invention, Figure 7 is the timing diagram. 11...Input terminal, 15...Clock terminal, 1
2, 13, 19...D-flip-flop circuit,
14...Exclusive OR circuit, 16...4-bit counter, 17...NAND gate, 18, 24...
Inverter, 20...OR gate, 21...AND
Gate, 22...NOR circuit.

Claims (1)

[Claims] 1. A synchronization signal detection circuit that receives a digital input signal containing a synchronization signal with a specific change pattern and detects the synchronization signal, and uses a counter that counts clock pulses to detect the difference between one change point of the input signal and the next change point. The first method detects that a part of the synchronization signal has been input when it corresponds to the interval between the change point of the synchronization signal and the next change point.
circuit means, and a second circuit means for storing that a part of the synchronization signal is inputted in response to the output of the first circuit means.
and generating a synchronization signal detection signal in response to the outputs of the first circuit means and the second circuit means when another part of the synchronization signal is further detected by the first circuit means. A synchronous signal detection circuit comprising: third circuit means.