JPS6310509B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a motor control device for a digital disc player. [Technical background of the invention and its problems] Recently, digital audio disks (DADs) (hereinafter simply referred to as disks) in which audio signals are digitized as digital data signals (PCM) and recorded on disks using uneven pit rows, and this technology have been developed. Digital disc players have been developed that detect pit rows on a disc and reproduce the original audio signal. This makes it possible to reproduce audio signals with high fidelity, which was previously considered impossible with analog disc players. By the way, such a digital disk player uses so-called AFC control, which controls the system clock signal, which is the reference clock for the operation of the entire device, and the synchronization signal component of the digital data signal read from the disk to have a predetermined frequency ratio. This is what we do. This allows the CLV to maintain a constant relative speed between the disk and the pit detection pick-up.
The digital disc player is also made compatible with the (constant linear velocity) system. However, such digital disc players cannot detect the synchronization signal when a burst error occurs due to dirt on the disc, or when the cycle of the synchronization signal shifts due to uneven rotation due to vibration, etc. The problem was that it was difficult to accurately and stably control the rotating motor. [Object of the invention] This invention was made in view of the above points,
Provided is a good motor control device for a digital disk player that can be easily configured and can stably drive the rotation of a motor for driving disk rotation even if a synchronization signal of a read digital data signal is shifted or missing. The purpose is to [Summary of the Invention] That is, the present invention provides a digital disc player that reads out a digital data signal from a disc on which a digital data signal accompanied by a synchronization signal is recorded for each frame, and a method for detecting the synchronization signal from the read digital data signal. a first means for detecting; and a first means provided to each part of the digital disc player, which divides the reference clock of the digital disc player by a number of bits corresponding to one frame of the digital data signal and synchronizes with the detected synchronization signal. a second means for deriving a synchronization signal and a window pulse to compensate for the loss of the synchronization signal and a period shift thereof; a third means for synchronizing the synchronization signal with the synchronization signal in a state where the synchronization signal starts to be detected again after the number reaches a predetermined number; and a controlled device based on the synchronization signal obtained from the second means. fourth means for generating a frequency signal and detecting and holding a frequency component of the controlled frequency signal; and a fourth means for detecting and holding a frequency component of the controlled frequency signal; A fifth means for controlling a rotary drive motor, and a state in which the synchronization signal is synchronized with the detected synchronization signal again by the third means, and the next detection target in the fifth means. The present invention is characterized in that it includes a sixth means for prohibiting the holding of the frequency component of the control frequency signal, so that the motor for driving the disk rotation can be driven stably. [Embodiment of the Invention] First, before explaining an embodiment of the present invention, an outline of a well-known digital disc player for compact disc (CD) type optical disc playback to which this invention is applied will be explained. . That is, as shown in FIG. 1, the turntable 1 is rotated by a disk motor 111.
A disk 113 mounted on the optical pickup 112 is played back by an optical pickup 114. in this case,
The optical pickup 114 is a semiconductor laser 114.
A beam splitter 114b transmits the light emitted from the
The signal surface of the disk 113 is irradiated through the objective lens 114c, and the pit corresponding to the digital PCM data of the audio signal to be reproduced, that is, the digital data signal, is recorded on the disk in a form with predetermined EFM modulation and interleaving. The objective lens 11 collects reflected light from uneven surfaces with different reflectances.
4c, the beam splitter 114b leads to a four-division photodetector 114d, and the four reproduction signals photoelectrically converted by the four-division photodetector 114d can be outputted to the outside. The disk 113 is linearly driven in the radial direction. The four reproduced signals from the four-division photodetector 114d are then supplied to the matrix circuit 116 and subjected to predetermined matrix calculation processing, thereby being separated into a focus error signal F, a tracking error signal, and a high frequency signal RF. . Of these, the focus error signal F is used together with the focus search signal from the focus search circuit 110 to drive the focus servo system FS of the optical pickup 114. Further, the tracking error signal T is sent to the optical pickup 1 along with a search control signal given via a system controller 117, which will be described later.
It is used to drive the 14 tracking servo systems TS and to perform linear tracking control on the pick-up feed motor 115. The remaining high frequency signal RF is then supplied to the reproduction signal processing system 118 as the main reproduction signal component. That is, the reproduced signal processing system 118 first guides the reproduced signal to a waveform shaping circuit 120 controlled by a slice level eye pattern detector 119, separates unnecessary analog components and necessary data components, and extracts only the data component. A synchronous clock regeneration circuit 121 and a first signal processing system 122 are of PLL type.
edge detector 122a. Here, the synchronous clock from the synchronous clock regeneration circuit 121 is used to generate a synchronous signal separation clock in the first signal processing system 122 for data demodulation. On the other hand, the edge detector 1
The reproduced signal passing through 22a is sent to a synchronization signal detector 122.
The synchronizing signal is separated by the synchronizing signal separating clock guided by the demodulating circuit 122d.
is guided and EFM demodulated. Among these, the synchronization signal is transmitted to the synchronization signal protection circuit 122.
The signal is guided to the input data processing timing signal generation circuit 122f together with the synchronization signal separation clock through the signal line e in a state where it is protected from malfunction. Further, the demodulation signal is sent to a second signal processing system 12 (described later) via a data bus input/output control circuit 122g.
The control signal and display signal components, which are subcodes, are supplied to the input/output control circuit 123a of No. 3, and the control signal and display signal components, which are subcodes, are guided to a control display processing circuit 122h and a subcode processing circuit 122i. The subcode data subjected to necessary error detection and correction by the subcode processing circuit 122i is sent to the system controller 117 via the system controller interface circuit 122g.
is supplied to Here, the system controller 117 includes a microcomputer, an interface circuit, a driver integrated circuit, etc., and controls the DAD playback device to a desired state based on command signals from the control switch 124, and also controls the above-mentioned subcodes, such as Display unit 1 shows the index information of the played song.
25. The timing signal from the input data processing timing signal generation circuit 122f is provided to control the data path input/output control circuit 122g via the data selector circuit 122j, and is also used to control the data path input/output control circuit 122g. 1
22l and a PWM modulator 122m for automatic frequency control AFC and automatic phase control APC for driving the disk motor 111 in a constant linear velocity CLV method. In this case, the frequency detection circuit 122k and the phase detector 122l are supplied with a system clock from a system clock generation circuit 122p which operates based on an oscillation signal from the crystal oscillator 122n. The demodulated data passing through the input/output control circuit 123a of the second signal processing circuit 123 is sent to the syndrome detector 1 for error detection and correction or correction.
23b, error pointer control circuit 123c, correction circuit 123d, and data output circuit 123e, the digital-analog D/A undergoes necessary error correction, deinterleaving, error correction, etc.
Converter 126. In this case, the external memory control circuit 123f works with the data selector circuit 122j to select the external memory 127 in which data necessary for correction is written.
By controlling the input control circuit 123
The data necessary for correction is taken in through a. Further, the timing control circuit 123g is configured to supply timing control signals necessary for error correction and correction and D/A conversion based on the system clock from the system clock generation circuit 122p. Further, the muting detection control circuit 123h is configured to perform predetermined control signals necessary for error correction and for starting and terminating the operation of the DAD playback device based on the output from the error pointer control circuit 123c or the control signal given via the system controller 117. It is used to perform muting control. Then, the audio signal converted back to an analog signal by the D/A converter 126 is passed through a low-pass filter 128 and an amplifier 129, and then sent to a speaker 130 for sounding. An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 shows the configuration of a digital disc player according to the present invention. That is, the optical pickup 11 reads signals recorded on the disk 12, and its output section includes the recording signal processing circuit 13, which is composed of the matrix circuit 116, the reproduction signal processing system 118 , etc. shown in FIG. Through the synchronization signal detector 12
It is connected to the input end of the synchronization signal detection circuit 14 corresponding to 2c. The output end of this synchronization signal detection circuit 14 is connected to the input end of a synchronization signal compensation circuit 15 corresponding to the synchronization signal protection circuit 122e. The synchronizing signal compensation circuit 15 compensates for missing synchronizing signals and period deviations contained in the read digital data signal, and performs synchronization to synchronize the operations of each part of the digital disc player with the synchronizing signal. The synchronizing signal compensation circuit 15 includes AND circuits 151 and 152, which will be described later, and its input terminals are commonly connected to one input terminal of each of the AND circuits 151 and 152. . The output terminal of one of the AND circuits 151 is commonly connected to reset terminals Ra and _R1 of a 1/N frequency divider 153 and an asynchronous frame counter 154, which will be described later, and one input terminal of an OR circuit 155, respectively. The output terminal of the other AND circuit 152 is
It is connected to the other input terminal of the OR circuit 155. The output terminal of the OR circuit 155 is connected to a reset terminal Rb of another I/N frequency divider 156, which will be described later. Each of the above-mentioned I/N frequency dividers 153 and 156 is constituted by, for example, an N (number of bits constituting one frame of a digital data signal) counter, etc., and each input terminal Ca and Cb is connected to a terminal T in common. ₁ to the system clock generation circuit 1.
It is connected to a reference signal generation circuit (not shown) corresponding to 22p, and counts system clock signals (pulses) which serve as a supplied reference clock. Each counting output section of the I/N frequency dividers 153 and 156 corresponds to the first window generator 1.
57 and to each input of a second window generator 158. These window generators 157 and 158 are operated several clocks (system clock signal ) is adapted to output a window pulse whose level changes from a low level (hereinafter referred to as L level) to a high level (hereinafter referred to as H level). 1st above
The output terminal of the window generator 157 is connected to the input terminal _C1 of the asynchronous frame counter 154, and also to one input terminal _I1 of a switching circuit 159, which will be described later. The output terminal of the second window generator 158 is connected to the other input terminal I ₂ of the switching circuit 159. The asynchronous frame counter 154 counts the wind pulses of the first window generator 157 and is reset by the output signal of the AND circuit 151, and becomes abnormal when the counted value exceeds a predetermined number (for example, 4). Outputs the status signal from the output terminal.
The output terminal of the asynchronous frame counter 154 is
It is connected to the control input terminal S ₀ of the switching circuit 159 and the other input terminal of the AND circuit 152 . For example, the switching circuit 159 selects the signal at the input terminal _I1 when the control input terminal _S0 is at the L level, and selects and outputs the signal at the input terminal _I2 when the control input terminal S0 is at the H level. It is connected to the other input terminal of the AND circuit 151. The output terminal of the I/N frequency divider 153 becomes the output terminal of the synchronization signal compensation circuit 15 , and is connected to the input terminal of the controlled frequency generation circuit 16 corresponding to a part of the timing signal generation circuit 122f. has been done. Incidentally, the output signal of the synchronization signal compensation circuit 15 is as follows:
Although not shown, it is supplied as a synchronization signal to each part of the digital disc player, and is designed to initialize, for example, the address designation counter of the memory 127, etc. Furthermore, the period of the system clock signal is set to be equal to, for example, the period during which one bit of the digital data signal is read. Synchronous signal compensation circuit 15 configured as described above
A synchronizing signal for each frame of the digital data signal detected by the synchronizing signal detection circuit 14 is supplied to one input terminal of each of the AND circuits 151 and 152. The above I/N frequency divider 15
3 is reset each time the output of the AND circuit 151 becomes H level, and supplies a synchronizing signal to the controlled frequency generating circuit 16. The output of the first window generator 153 is the output of the first window generator 153.
After the N frequency divider 153 outputs a synchronization signal, it outputs a window pulse for a period corresponding to several bits before and after the timing of outputting the next synchronization signal, and sets its output terminal to H level. This output is supplied to one input terminal of the AND circuit 151 via the switching circuit 159. Therefore, the synchronization signal detection circuit 14 and I/
When normal synchronization with the N frequency divider 153 is established, when the output signal (pulse) of the synchronization signal detection circuit 14 enters the window pulse generated by the first window generator 153. only and circuit 1
The output of 51 becomes H level to prevent errors caused by noise other than the synchronization signal. On the other hand, if the synchronization signal of the read digital data signal cannot be detected for reasons such as dropout, or if the synchronization is lost, the asynchronous frame counter 154 uses the first window generator 157 to detect the synchronization signal of the digital data signal. It is counted up every time one frame is read out. And asynchronous frame counter 1
When 54 counts a preset number of frames (for example, 4 frames), its output terminal becomes H level. This causes the second window generator 158
The output of is supplied to the other input terminal of the AND circuit 151 via the switching circuit 159, and
The other input terminal of the other AND circuit 152 is set to H level. Therefore, when normal synchronization is achieved (that is, when the output of the asynchronous frame counter 154 is at L level), the I/N frequency divider 156
is the OR circuit 15 based on the output of the AND circuit 152.
Since it is reset via I/N frequency divider 153, it is synchronized with the I/N frequency divider 153. On the other hand, when the output of the asynchronous frame counter 154 becomes H level, the I/N frequency divider 156
is reset via the AND circuit 152 and the OR circuit 155 when the synchronization signal is detected by the synchronization signal detection circuit 14. That is, in this state, the second window generation 158 is synchronized, and its window pulse is synchronized with the output of the synchronization signal detection circuit. Therefore, when the output of the asynchronous frame counter 154 is at H level after a predetermined period has elapsed, the pulse that is first output from the synchronization signal detection circuit 14 and resets the I/N division period 156 is the digital data. If the signal is a synchronous signal, the next synchronous signal (pulse) output from the synchronous signal detection circuit 14 resets the I/N frequency divider 153 and the asynchronous frame counter via the AND circuit 151. Thereafter, the synchronization signal output from the synchronization signal detection circuit 14 is extracted via the AND circuit 151 for each frame of the digital data signal by the output of the first window generator 157, and the synchronization signal output from the synchronization signal detection circuit 14 is 14 and I/N frequency divider 1
This is to synchronize with 53. Furthermore, if the pulse output from the synchronization signal detection circuit 14 is noise after the output of the asynchronous frame counter 154 is set to H level,
This pulse resets and synchronizes the I/N divider 156. However, from this point on, unless the output pulse of the synchronizing signal detection circuit 14 is included in the window pulse generated by the second window generator 158, the AND circuit 151
No output signal is output from. Therefore, when regular synchronization signals are detected consecutively after the noise is output, the second and subsequent synchronization signals are taken out from the AND circuit 151 and the synchronization signals are This allows synchronization between the signal detection circuit 14 and the I/N frequency divider 153. By the way, the controlled frequency generation circuit 16 is as follows:
For example, it is a frequency divider, which divides the frequency of the synchronization signal supplied to the input terminal by a predetermined number and outputs it as a controlled frequency signal, and the output terminal is the frequency detector 122k.
The edge detection circuit 171 is connected to the input terminal of the edge detection circuit 171 that constitutes the frequency detection circuit 17 corresponding to the frequency detection circuit 17. This edge detection circuit 171 detects, for example, a falling edge of the frequency controlled signal, and its output terminal is connected to the input terminal INe of the AFC detection control circuit 172. The AFC detection control circuit 172 outputs the output signal (that is, the edge detection signal) of the edge detection circuit 171 as a latch pulse to a latch circuit 173, which will be described later, and then outputs a reset pulse for the AFC counter 174. The output terminal Oe is connected to the latch pulse input terminal Lf of the latch circuit 173, and the reset pulse output terminal Of is connected to the reset input terminal Rf of the AFC counter 173. AFC counter 1 above
Reference numeral 74 detects, for example, the period (that is, the frequency component) between falling edges of the controlled frequency, and a reference signal such as a system clock, for example, is supplied to the counting input terminal via the terminal _T2 . The counting output section is connected to the latch input section of the latch circuit 173 and the input section of an AFC outside control area detection circuit 175, which will be described later. The above-mentioned AFC control area outside detection circuit 175 has the above-mentioned
It detects the state in which the rotational speed of the disk 11 is within the control range based on the count value of the AFC counter 174. If the rotational speed is lower than the control range, a latch set signal is output, and the rotational speed is higher than the control range. It is designed to output a latch reset signal when the The AFC control area outside detection circuit 175 detects the latch set signal output terminal Os.
is connected to the latch reset signal input terminal Ls of the latch circuit 173, and the latch reset signal output terminal Oc is connected to the latch reset signal input terminal Ls of the latch circuit 173.
is connected to the latch set signal input terminal Lc of the latch circuit 173. The output section of the latch circuit 173 will be described later.
It is connected to the input section of the PWM converter 18, and when a latch pulse is supplied, the count value of the AFC counter is latched. Regardless of this latch pulse, when a latch set signal is supplied, all of the output section For example, the bits of the output section are set to the H level, and when a latch reset signal is supplied, all the bits of the output section are set to the L level, for example. The PWM converter 18 is the PWM modulator 1
22m, and the above latch circuit 1
73 into a pulse width signal having a pulse width corresponding to the output signal. The output end of the above PWM converter 18 is a low pass filter (LPF)
19 to a rotational speed control input terminal of a motor 20 that rotationally drives the disk. The LPF 19 converts the pulse width signal output from the PWM converter 18 into a DC level, and provides the motor 20 with a rotational speed control signal at, for example, a voltage level. That is, the period (frequency component) of the controlled frequency signal detected by the frequency detection circuit 17 is converted into a rotational speed control signal by the PWM converter 18 and LPF 19, and is applied to the motor 20.
is controlled so that the period of the controlled frequency is approximately constant. When the frequency detection circuit 17 detects that the controlled frequency signal is outside the control range, it controls the output of the latch circuit 173 to quickly control the rotational speed of the motor 20 (that is, the rotational speed of the disk). This allows the user to enter the area. By the way, the output terminal of the above synchronization signal detection circuit is
The output terminal of the asynchronous frame counter 154 is connected to the second input terminal of the 3-input AND circuit 21, and the output terminal of the second window generator 158 is connected to the first input terminal of the 3-input AND circuit 21. is connected to the third input terminal of the three-input AND circuit 21. The output terminal of the above 3-input AND circuit 21 is as above.
It is connected to the control input terminal Il of the AFC detection control circuit 172. Although omitted in the above description, the AFC detection control circuit 172 does not output the latch pulse at the next falling edge of the controlled frequency signal when the latch prohibition pulse is input to the control input terminal, and outputs the latch pulse to the latch circuit 173. This prohibits the count value of the AFC counter 174 from latching. The means for inhibiting the output of this latch pulse includes, for example, a flip-flop whose output is set (H level) by the latch inhibit pulse and reset (L level) by the reset pulse of the AFC counter 174, and the output of this flip-flop is set to H level. The output of the latch timing pulse, which becomes the latch pulse, is prohibited during the period when the level is set. The operation of the apparatus of this embodiment configured as described above will be explained with reference to the timing diagram of FIG. However, the signals a to j in FIG. 3 correspond to the signal lines with the same reference numerals in FIG. are each output signal (wind pulse) of the first window generator 157 and second window generator 158, d is the output signal of the AND circuit 151, e is the output signal of the asynchronous frame counter 154, and f is the 1/N minute The output signal of the frequency generator 153 to the controlled frequency generation circuit 16, g is the output signal of the edge detection circuit 171 (pulse indicating latch timing), h is the output signal of the 3-input AND circuit 21,
i is a flip-flop output signal for inhibiting latch pulse output provided inside the AFC detection control circuit 172, and j is an output signal (latch pulse) from the latch pulse output terminal Oe of the AFC detection control circuit 172. In order to make the explanation easier to understand, here,
The controlled frequency generation circuit 16 is a 1/N frequency divider 153
It is assumed that the signal f from the signal f is output as is to the edge detection circuit 171 without being frequency-divided. Also, 1/N
It is assumed that the frequency divider 153 outputs a signal f that becomes H level when the count value of the N-ary counter constituting the divider 153 is, for example, "1" (that is, immediately after reset). Therefore, in Fig. 3, the synchronization signal is not detected due to the influence of track jump, etc. (state of synchronization signal a before time to), and when the synchronization signal is detected at time to, the pulse of synchronization signal a is If the output signal b of the first window generator 157 deviates from the window pulse, during that time the AND circuit 151 does not output a reset pulse as shown in FIG. 3d. Therefore, the 1/N frequency divider 153 outputs interpolation pulses (pulses indicated by diagonal lines in FIG. 3f) without synchronization with the synchronization signal a. At the same time, the asynchronous frame counter 154 counts the window pulses that are not synchronized with the synchronization signal a out of the output signal b of the first window generator 157, for example twice in succession, to generate an H level signal. Output and switching circuit 159
The output of the second window generator 158 is the output signal c
AND circuit 1 at time to.
52 and a 1/N frequency divider 156 to synchronize the window pulses of the second window generator 158 to the pulses of the synchronization signal a. Therefore, when the pulse of the synchronization signal a is detected within the window pulse of the second window generator 158 at time t1, the output signal d of the AND circuit 151
The 1/N frequency divider 153 and asynchronous frame counter 154 are reset (reset at falling edge).
The window pulse of the first window generator 157 is synchronized with the synchronization signal a. Up to this point, in the frequency detection circuit 17, the edge detection circuit 172 detects the falling edge of the output of the controlled frequency generation circuit 16, that is, the output signal f of the 1/N frequency divider 153, and generates a pulse signal indicating the latch timing. Output g and receive this
The AFC detection control circuit 172 outputs a latch pulse j to the latch circuit 173. Therefore, at time t1, the synchronization circuit signal a, the second
Since the output signal c of the window generator 158 and the output signal e of the asynchronous frame counter 154 are both at H level, the 3-input AND circuit 21 disables the latch as shown in FIG. 3h to the AFC detection control circuit 172. A pulse is output. Then, the AFC detection control circuit 172 sets the internal flip-flop output to H level, and as shown in FIG.
A latch prohibition signal as shown in FIG. Forbidden latch pulse). Then, the AFC detection control circuit 172 at time t ₂
By generating a reset pulse for the AFC counter 174, the flip-flop output is reset to the L level. As a result, latch circuit 1
73 does not latch the count value of the AFC counter 174 and uses the previous count value of the AFC counter 174 using PWM.
It supplies the converter 18. After that, when a synchronization signal is detected every predetermined period,
The I/N division period 153 supplies a predetermined synchronization signal to the input end of the controlled frequency generation circuit 16 and other parts of the digital disc player. By the way, a CD type digital disc player is designed to trace the pit row of the disc from the inner circumference toward the outer circumference. Therefore, when the synchronization signal is lost once and then detected again, the rotational speed of the disk remains constant, and inevitably there will be a phase shift in the synchronization signal before and after the loss. . As a result, _one cycle period of the controlled frequency signal (from the falling edge of the signal in FIG. 3f to the falling edge of the signal in FIG. The period up to the edge becomes shorter, and the period (that is, the frequency component) of the controlled frequency signal detected by the AFC counter 174 temporarily becomes an abnormal value. However, the count value of this AFC counter 174 is
3, an abnormal value will not be supplied to the PWM converter 18, and the rotational speed control signal supplied to the rotational speed control input terminal of the motor 20 will not change suddenly. Therefore, the apparatus shown in FIG. 2 can stably control the rotation of the disk drive motor 20 without abruptly changing it, and thus can stably perform disk playback. It goes without saying that the present invention is not limited to the above embodiments, and that various modifications and applications are possible without departing from the gist of the present invention. [Effects of the Invention] As detailed above, according to the present invention, it is easy to configure, and the rotation of the disk rotation drive motor can be stably controlled even if there is a shift or omission of the synchronization signal of the read digital data signal. A motor control device for a digital disc player can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing a digital disc player to which the present invention is applied, FIG. 2 is a diagram showing the configuration of an embodiment of a motor control device for a digital disc player according to the present invention, and FIG. FIG. 3 is a timing diagram used to explain the operation of the device shown in FIG. 2; 11...Optical pickup, 12...Disk, 13...Recording signal processing circuit, 14...Synchronizing signal detection circuit, 15 ...Synchronizing signal compensation circuit, 15
1,152...AND circuit, 153,156...
I/N frequency divider circuit, 154...Asynchronous frame counter, 155...OR circuit, 157, 158...
Window generation circuit, 159...Switching circuit, 16...Controlled frequency generation circuit, 17 ...Frequency detection circuit, 1
71...Edge detector, 172...AFC detection control circuit, 173...Latch circuit, 174...
AFC counter, 175...AFC control area outside detection circuit, 18...PWM converter, 19...Low pass filter, 20...Motor, 21...3 input AND circuit.

Claims (1)

[Claims] 1. In a digital disc player that reads a digital data signal from a disc on which a digital data signal accompanied by a synchronization signal is recorded for each frame, a first means for detecting the synchronization signal from the read digital data signal; Deriving a synchronization signal and a wind pulse that are provided to each part of the disc player, divide the reference clock of the digital disc player by a number of bits corresponding to one frame of the digital data signal, and synchronize with the detected synchronization signal. death,
a second means for compensating for the loss of the synchronization signal and its period shift; a third means for synchronizing the synchronization signal with the synchronization signal in a state where the synchronization signal has started to be detected, and generating a controlled frequency signal based on the synchronization signal obtained from the second means; a fourth means for detecting and holding a frequency component; and a fifth means for controlling the motor for driving the disk rotation so that the frequency component of the controlled frequency signal held by the fourth means is substantially constant. and detecting a state in which the synchronization signal is again synchronized with the detected synchronization signal by the third means, and prohibiting the fifth means from holding the frequency component of the next detected controlled frequency signal. A motor control device for a digital disc player, comprising the sixth means.