JPS58219769A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance accuracy in self-alignment for gates in conductive regions different in resistivities, by determining self-aligning sizes in correspondence with the thickness of an oxide film in a polysilicon layer. CONSTITUTION:On the surface of a P type silicon semiconductor substrate 30, a field silicon oxide film 32 and a silicon oxide film 34 for gate insulation are formed. On a silicon nitride film 36 for gate insulation, a phosphorus doped silicon layer 38 is selectively arranged. With an oxide film 44 as a mask, an N<+> type region 46 for a source and an N<+> type region 48 for a drain are formed. Then, the nitride film 36 is selectively removed. By silicon oxide etching, the surfaces of the regions 46 and 48 are exposed. Thereafter, contact holes to the polysilicon layer 38 are provided. Then, a source electrode layer 50, a drain electrode layer 52, and a wiring layer are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device such as a silicon gate MO8 type FF1T (field effect transistor), and uses side oxidation of a gate polysilicon layer to form a gate in conductivity type regions having different resistivities. This improves self-alignment accuracy.

Conventionally, a self-alignment process using over-etching of a polysilicon layer is known, but this method has the drawback of large variations because the alignment dimensions of the cell 7 are determined depending on the amount of etching. That is, the etching process generally has large fluctuations (approximately ±20%), and it is also difficult to measure the amount of overetching.

An object of the present invention is to provide a novel method for manufacturing a semiconductor device that improves the self-alignment accuracy of conductivity type regions having different resistivities (for example, N+ type and N- type source regions) with respect to the gate.

The manufacturing method invented by Jin selectively places a polysilicon layer on the surface of a semiconductor substrate via an insulating film, then oxidizes this polysilicon layer to form a silicon oxide film on at least its side surfaces. A conductivity type region with relatively low resistivity is formed by impurity doping treatment using the film as a mask, and after this or before the formation of the silicon oxide film, a region with relatively high resistivity is formed by impurity doping treatment using the polysilicon layer as a mask. A conductivity type region is formed.

The present invention will be described below with reference to embodiments shown in the accompanying drawings.

FIG. 1(a) to Tdl show silicon oxide (MO8) type F in the integrated circuit manufacturing process according to an embodiment of the present invention.
It shows the manufacturing process of ET.

First, in the step (a), the front surface of the semiconductor substrate 10 made of P-type silicon! [ ] is selectively oxidized to form a relatively thick field silicon oxide film 12i, a relatively thin silicon oxide film 14 as a gate insulating film is thermally generated on the substrate surface portion not covered with this oxide film 12. Then, a gate polysilicon layer 16 is formed by depositing phosphorus-doped polysilicon on the oxide film 14 and patterning it according to a predetermined gate pattern.

Next, in step (b), a silicon oxide film 18 is formed to cover the sawn surfaces (top and side surfaces) 1 of the polysilicon layer 16 to a thickness of 45 μm, for example, by low-temperature oxidation treatment. At this time, the thickness of the oxide film on the surface portion of the substrate not covered with the polysilicon layer 16 is 0.15~
Increase by 0.2 μm. Note that since the polysilicon layer 16 is doped with phosphorus, its oxidation rate is about three times faster than that of the silicon substrate. Then, by selective ion implantation of phosphorus or arsenic using the oxide film 18 as a mask, an N+ type region for a source and an N''! region 22 for a drain are formed on the substrate surface. The lateral diffusion depth of + or n can be 0.35 Pm.

Next, in step (C), silicon oxide etching is performed on the entire surface to reduce the thickness of the oxide film 18 and other oxide films. In this case, oxide film 1
Since it contains 8 t'i phosphorus, the etching speed is fast. Then, by selectively implanting N-type impurities using the polysilicon layer 16 as a mask, an N-type region 26 for a source and an N-type region 26 for a drain are formed on the substrate surface.
form. Here, the N-type region or the lateral diffusion depth d! can be set to 0.2 μm, and the self-alignment dimension JiQ with respect to the N+ type region or n polysilicon layer 16 can be set to 1 μm.

After this, in the step (d), a silicon layer, sides, etc. are deposited on the substrate (3) by CvD (Chemical Paper Deposition) method or the like to form film scales, and the following steps are performed. Performs normal process processing.

In the above embodiments, the N-type regions may be formed before oxidizing the polysilicon layer 16'.

FIG. 2 (al~+81 shows the manufacturing process of a silicon gate MO8 type FET among the integrated circuit manufacturing processes according to another embodiment of the present invention.

First, in the step (a), P
A field silicon oxide film 32 and a gate insulating silicon oxide film 34 are formed on the surface of a semiconductor substrate I made of silicon. Then, on top of the oxide film U, a silicon nitride film 36 for gate insulation is formed at a thickness of 10-3.
After forming the nitride film to a thickness of 0 nm, a 500 nm thick phosphorus-doped polysilicon layer is selectively disposed on the nitride film in the same manner as in FIG. Thereafter, an N-type region for a source and an N-type region 42 for a drain are formed by selective ion implantation of N-type impurities using a polysilicon layer metal mask.

Next, in the step (b), a low-temperature oxidation treatment is performed to cover the true surface of the wrinkled silicon layer (a silicon oxide film 44 is formed with a thickness of 0.45 μm. At this time, the distance between the polysilicon layers is 0.45 μm. It decreases by .2 μm.It also acts to prevent oxidation of the surface of the substrate on which the nitride film is formed.
.

Next, in step (C), an N+ type region 46 for a thin source and a door-shaped region 48 for a drain are formed by selective ion implantation of N type determining impurities using the oxide film 44 as a mask.

Next, in the step (d), the nitride film 36 is selectively removed using the oxide film 44'i as a mask, and then the surfaces of the N+ type regions 46 and 48 are exposed by full silicon oxide etching. In this silicon oxide etching, the thickness of the oxide film increases by ~50
Since the oxide film 44 is as thin as nanometers, most of the oxide film 44 remains as it is.

8 After this, in the step (e), after forming a contact hole for the polysilicon layer, electrode metal is sputtered on the entire surface and patterned appropriately, thereby forming a gap between the source electrode layers, the drain electrode layer 52, etc. An electrode/wiring layer is formed, and then a passivation film 54 made of silicon oxide or the like is formed by CVD.

Incidentally, the embodiment shown in FIG. 2 and 9 can also be implemented without a silicon nitride film.

As described above, according to the present invention, the cell 7 alignment dimension is determined according to the oxide film thickness of the polysilicon layer, so the dimension reproducibility is high (within ±5%) and measurement is easy. The accuracy is also high (within ±3 inches). Therefore, the self-alignment precision with respect to the gate of conductivity type regions having different resistivities is much higher than that when conventional over-etching is used.

[Brief explanation of the drawing]

FIGS. 1A to 1D are cross-sectional views of a substrate showing the manufacturing process of a silicon MO8 type FIT according to an embodiment of the present invention, and FIGS. FIG. 3 is a cross-sectional view of a substrate showing the manufacturing process of a silicon-based MO8 type FBT according to an embodiment of the present invention. 10, 30... semiconductor substrate, 12, 14, 18
, 34, 44-・Silicon oxide film, 16.3
8...Polysilicon layer, rib, 46...N+ for source
Type region, 22, 48... N+ type region for drain, 24
, 40...N-type region for source, ah. String... N-W area for drain. Applicant Nippon Musical Instruments Manufacturing Co., Ltd. Agent Patent Attorney Satoshi Izawa Figure 2

Claims (1)

[Claims] 1. A step of (a) selectively arranging a polysilicon layer on the surface of a conductive type semiconductor substrate via an M edge film;
)l A step of oxidizing the exposed surface of the polysilicon layer to form a silicon oxide film covering the polysilicon layer; (cl) Using the silicon oxide film as a mask, the substrate surface is selectively doped with an impurity that determines the opposite conductivity type. f(1) selectively applying opposite conductivity to the substrate surface using the polysilicon layer as a mask before the step (b) or after the tc+ step; doping with a type-determining impurity to form a region of opposite conductivity type having a relatively high resistivity.