JPS58219756A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS58219756A
JPS58219756A JP10283682A JP10283682A JPS58219756A JP S58219756 A JPS58219756 A JP S58219756A JP 10283682 A JP10283682 A JP 10283682A JP 10283682 A JP10283682 A JP 10283682A JP S58219756 A JPS58219756 A JP S58219756A
Authority
JP
Japan
Prior art keywords
lead
leads
dummy
frame
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10283682A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamamoto
浩 山本
Shigeki Takeo
竹尾 重樹
Kiyoshi Usui
臼井 清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10283682A priority Critical patent/JPS58219756A/en
Publication of JPS58219756A publication Critical patent/JPS58219756A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of burrs by blocking the outflow of resin at the time of a mold process by a method wherein dummy leads are placed side by side between each external lead, and then the top end of this dummy lead is arranged in proximity to a mold part. CONSTITUTION:A mounting part 13 whereon a semiconductor element is placed is arranged inside surrounded by the longitudinal frame 11 and the transverse frame 12 of a frame. In the periphery of the mounting part 13, many internal leads 14 are so arranged as to put the top ends in proximity to each other, and then joined to the transverse frame 12 by the external lead 15 which is the extension of the lead 14. The dummy leads 20 are arranged between the external leads 15 and joined to the transverse frame 12. The top end of the dummy lead 20 is set in parallel to and sufficiently in proximity to the mold part 17, but the clearance of 0.1mm. at least is provided. Further, supporting pieces 21 serving also to prevent the outflow of resin are arranged outside the external leads 15 at both ends, and joined to the longitudinal frame 11.

Description

【発明の詳細な説明】 〔発明の技術的分野〕 との発明は、例えばDIP (デエアル・インライン・
パッケージ)タイプ及びSIP (シングル・インライ
ン・パッケージ)タイプの半導体装置を製造する場合に
おいて、モールド樹脂のパリ発生防止機能をもつ半導体
装置用リードフレームに関する。
[Detailed description of the invention] [Technical field of the invention]
The present invention relates to a lead frame for a semiconductor device that has a function of preventing paris from forming in a mold resin when manufacturing semiconductor devices of the package type and the SIP (single in-line package) type.

〔発明の技術的背景〕[Technical background of the invention]

従来、例えばDIPタイプパッケージおよびSIPタイ
プ/々ツケージ用のリードフレームは、それぞれ第1図
および第2図に示すように、フレームの縦枠11と横枠
12に囲まれる内側に、中央部に図示しない半導体素子
を取着する取着部13と、取着部13に先端部がそれぞ
れ隣接される内部リード14と、その内部リードよシ横
枠12方向に延長される外部リード15とを配置し、外
部リードの延長端を上記枠12に対して連結するように
構成している。そしてダム部16が外部リード15に対
して直交し且つ外部リード及び縦枠と連結し、リードを
機械的に保持すると共にモールド樹脂の流出防止するよ
うな構成となっている。すなわち、半導体素子を取着部
11に設置して、その素子の各電極を各内部リード14
にそれぞれ?ンディング接続した後、図に鎖線で示す樹
脂モールド部17に樹脂を充填し、半導体素子を樹脂モ
ールドす−るものである。
Conventionally, for example, a lead frame for a DIP type package and a SIP type package, as shown in FIG. 1 and FIG. A mounting part 13 for mounting a semiconductor element that is not attached to the mounting part 13, an inner lead 14 whose tip end is adjacent to the mounting part 13, and an outer lead 15 extending from the inner lead in the direction of the horizontal frame 12 are arranged. , the extended ends of the external leads are connected to the frame 12. The dam part 16 is perpendicular to the external lead 15 and connected to the external lead and the vertical frame, so as to mechanically hold the lead and prevent mold resin from flowing out. That is, a semiconductor element is installed in the mounting part 11, and each electrode of the element is connected to each internal lead 14.
Each? After bonding and connection, a resin mold portion 17 shown by chain lines in the figure is filled with resin, and the semiconductor element is resin-molded.

〔背景技術の問題点〕[Problems with background technology]

すなわち、実際にはダム部16と鎖線に示すモールド部
17との間に空間18が形成される構造となりている。
That is, the structure is such that a space 18 is actually formed between the dam part 16 and the mold part 17 shown by the chain line.

このため、空間18にモールド樹脂の流出による厚Δす
が発生する。しかもリードフレームの厚みのバラツキ、
モールド金型のクリアランスの精度、リードフレームを
挾むパーティング面の平坦度、樹脂の溶融粘度及び硬化
時間、成形圧力等の要因によシ、上記空間18から樹脂
が進展し、外部リード15およびダム部16.の表裏に
薄パリが発生付着することもある・ 〔発明の目的〕 この発明は上記欠点を改善して、モールド工程時に樹脂
の流出を阻止し、パリの発生の防止或い捻パリの発生を
充分に□低減できる半導体装置用リードフレームを提供
するものである。
Therefore, a thickness Δ is generated in the space 18 due to the outflow of the mold resin. Moreover, variations in the thickness of the lead frame,
Depending on factors such as the precision of the clearance of the mold, the flatness of the parting surfaces that sandwich the lead frame, the melt viscosity and curing time of the resin, and the molding pressure, the resin will develop from the space 18, and the outer lead 15 and Dam part 16. [Objective of the Invention] This invention improves the above-mentioned drawbacks, prevents the resin from flowing out during the molding process, and prevents the occurrence of flash or twisted flash. The object of the present invention is to provide a lead frame for a semiconductor device that can sufficiently reduce the square.

すなわち、この発明におけるリードフレームは、ダミー
リードを各外部リードの相互間に並置させ、しかもこの
ダミーリードの先端をモールド部に近接配置し、このダ
イ−リードとモールド部との間隙を極力小さくするもの
である。
That is, in the lead frame according to the present invention, dummy leads are placed side by side between the external leads, and the tips of the dummy leads are placed close to the mold part to minimize the gap between the die leads and the mold part. It is something.

〔発明の実施例〕[Embodiments of the invention]

以下、図面についてこの発明の一実施例を説明する。第
3図はDIPタイプパッケージ用の場合の構成を示すも
ので、7レームの縦枠11と横枠12とで囲む内側に、
中央部に図示しない半導体素子をのせる取着部13を配
置し、との取着部13は支持体19によって縦枠11と
連結して支持する。また、との取着部130周辺には先
端を近接するようにして多数の内部リード14が配設さ
れ、この各内部リード14の延長である外部リード15
によりて横枠12と連結する。このとき、鎖線の内部、
つまシ取着部13及び支持体19、がンディングされる
内部リード14の先端部及び図示しない半導体素子を包
む部分がモールド部17である。さらに、上記外部リー
ド15の相互間にはダミーリード20を配設するもので
、このダミーリード2゜はそれぞれ横枠12に連結する
。この場合、各ダミーリード20の先端は上記モールド
部17と平行にして且つ充分近接して設定するものであ
るが、少なくとも0.1 m11の間隙を設けるように
する。また、ダミーリードの両側は各外部リード15の
側部と充分近接設定するもので、その間隙は例えば0.
05〜0.50になるようにする。さらに、両端の外部
リード16の外側には樹脂流出防止の役割を兼ねた支持
片21を配設し、縦枠1ノと連結する。
An embodiment of the present invention will be described below with reference to the drawings. Figure 3 shows the configuration for a DIP type package.
A mounting part 13 on which a semiconductor element (not shown) is mounted is arranged in the center, and the mounting part 13 is connected to and supported by the vertical frame 11 by a support 19. Further, a large number of internal leads 14 are arranged around the attachment part 130 with their tips close to each other, and external leads 15 which are extensions of each internal lead 14 are arranged.
It is connected to the horizontal frame 12 by. At this time, inside the chain line,
The mold portion 17 includes the tab attachment portion 13, the support body 19, the tip of the internal lead 14 to be bonded, and a portion that encloses the semiconductor element (not shown). Furthermore, dummy leads 20 are arranged between the external leads 15, and these dummy leads 2° are connected to the horizontal frame 12, respectively. In this case, the tip of each dummy lead 20 is set parallel to and sufficiently close to the mold part 17, with a gap of at least 0.1 m11. Further, both sides of the dummy lead are set sufficiently close to the sides of each external lead 15, and the gap therebetween is, for example, 0.
05 to 0.50. Further, support pieces 21 are provided outside the external leads 16 at both ends and serve to prevent resin from flowing out, and are connected to the vertical frame 1.

また、SIPタイプパッケージ用のものも上記DIPタ
イプのものと同様に構成することのできるもので、第4
図に示すようになる。第4図で第3図と同一符号を付し
たものは同一部分を示す0 このようなダミーリード20を設けたリードフレームに
よると、モールド部170周辺に不要な空間がダミーリ
ード20によって封じられる状態となる。したがって、
樹脂モールド工程において、ダミーリード20の先端が
樹脂の流出を防止するように゛マシ、それゆえに厚Δり
の発生は確実に阻止される。また、ダt−V−ド20の
両側と各外部リード16の側部との間隙が充分に小さい
ために、この部分に樹脂が流出せず、したがって薄パリ
も発生しない。
In addition, the one for the SIP type package can be constructed in the same way as the DIP type mentioned above, and the fourth
The result will be as shown in the figure. In FIG. 4, the same reference numerals as in FIG. 3 indicate the same parts. According to the lead frame provided with such dummy leads 20, an unnecessary space around the mold part 170 is closed by the dummy leads 20. becomes. therefore,
In the resin molding process, the tips of the dummy leads 20 are designed to prevent the resin from flowing out, and therefore the occurrence of thickness Δ is reliably prevented. Further, since the gaps between both sides of the door 20 and the side portions of each external lead 16 are sufficiently small, resin does not flow into these portions, and therefore no thin flakes occur.

すなわち、モールドされたり−ド7レームの外部リード
15のカッティングと同時にダミーリード20を切υ離
した後に、メッキ或いは半田ディプ等の工程を行なう場
合、パリが存在していないため支障なく円滑に実行し得
る。
That is, when a process such as plating or solder dipping is performed after the dummy lead 20 is cut and separated at the same time as the external lead 15 of the molded or molded frame is cut, the process can be carried out smoothly without any problem because there is no parting. It is possible.

第5図、第6図はDIPタイプおよびSIPタイプのそ
れぞれ他の実施例を示す吃のであシ、第1図で示したと
同様のダム部16を設け、このダム部1−6に対してダ
ミーリード20を形成するようにしたものである。この
ようにすれば、ダム部16が各リードを直接的に支持す
るので強度的に強くな夛、モールド工程時の歪みの心配
がない。伺、第5図及び第6図において、第3図及び第
4図と同一構成部分は同一符号を付してその説明を省略
する。
FIGS. 5 and 6 show other embodiments of the DIP type and the SIP type, respectively. A dam part 16 similar to that shown in FIG. 1 is provided, and a dummy A lead 20 is formed therein. In this way, since the dam portion 16 directly supports each lead, the structure is strong and there is no worry of distortion during the molding process. 5 and 6, the same components as those in FIGS. 3 and 4 are given the same reference numerals, and the explanation thereof will be omitted.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、半導体素子の樹脂モー
ルド工程でモールド樹脂のモールド部からの流出はダi
 −IJ−ドの先端で防止されるので厚パリの発生はな
くなり、さらにダミーリードと各外部リードの両側に発
生する薄パリの発生も確実に防止できる。
As described above, according to the present invention, it is possible to prevent mold resin from flowing out from the mold part in the resin molding process of semiconductor elements.
Since this is prevented at the tip of the -IJ- lead, the occurrence of thick flash is eliminated, and furthermore, the occurrence of thin flash that occurs on both sides of the dummy lead and each external lead can be reliably prevented.

したがって、モールド工程時にリードフレームに対して
不要なパリが付着していないため、メッキ或いは半田デ
ィグ等の工程がスムーズに行なうことができる。
Therefore, since unnecessary particles are not attached to the lead frame during the molding process, processes such as plating or soldering digging can be performed smoothly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図はそれぞれ従来のリードフレームの構
成を示す平面図、第3図はこの発明の一実施例に係るD
IPタイプノ々ツケージ用リードフレームの構成を示す
平面図、第4図は同じ(SIPタイプ/々ツケージ用リ
ードフレームの構成を示す平面図、第5図及び第6図は
それぞれこの発明の他の実施例を示す平面図である。 11・・・縦枠、12・・・横枠、13・・・取着部、
14・・・内部リード、16・・・外部リード、16・
・・ダム部、17・・・モールド部、18・・・空間、
19・・・支持体、20・・・ダt−V−ド、21・・
・支持片。 出願人代理人  弁理士 鈴 江 武 彦第1B 2 第2図 第3vA 第4図
1 and 2 are plan views showing the structure of a conventional lead frame, respectively, and FIG. 3 is a D according to an embodiment of the present invention.
The plan view showing the structure of the lead frame for the IP type cage, FIG. 4, is the same (the plan view showing the structure of the lead frame for the SIP type cage, FIG. 5, and FIG. It is a plan view showing an example. 11... Vertical frame, 12... Horizontal frame, 13... Attachment part,
14...Internal lead, 16...External lead, 16.
...Dam part, 17...Mold part, 18...Space,
19... Support body, 20... Dat-V-do, 21...
・Support piece. Applicant's representative Patent attorney Takehiko Suzue No. 1B 2 Figure 2 Figure 3vA Figure 4

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を取シ付ける取着部と、との取着部の周囲に
まで近接延長され上記半導体素子の導出端子部に選択的
に接続される複数の内部リードと、この内部リードから
それぞれに延長形成される複数の外部リードと、この外
部リードそれぞれの相互間に配置された複数のダミーリ
ードを具備し、このダミーリードそれぞれの先端は、上
記内部リード部に対応した樹脂モールド部周辺に近接設
定するようにしたことを特徴とする半導体装置用リード
フレーム。
a mounting portion for mounting a semiconductor device; a plurality of internal leads that extend close to the periphery of the mounting portion of the semiconductor device and selectively connect to the lead-out terminal portion of the semiconductor device; and a plurality of internal leads extending from the internal leads respectively. A plurality of external leads are formed, and a plurality of dummy leads are arranged between each of the external leads, and the tip of each of the dummy leads is set close to the periphery of the resin molded part corresponding to the internal lead part. A lead frame for a semiconductor device, characterized in that:
JP10283682A 1982-06-15 1982-06-15 Lead frame for semiconductor device Pending JPS58219756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10283682A JPS58219756A (en) 1982-06-15 1982-06-15 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10283682A JPS58219756A (en) 1982-06-15 1982-06-15 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS58219756A true JPS58219756A (en) 1983-12-21

Family

ID=14338073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10283682A Pending JPS58219756A (en) 1982-06-15 1982-06-15 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS58219756A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6117750U (en) * 1984-07-04 1986-02-01 三菱電機株式会社 Frame for semiconductor devices
JPS6181154U (en) * 1984-10-31 1986-05-29
JPS61134048U (en) * 1985-02-09 1986-08-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6117750U (en) * 1984-07-04 1986-02-01 三菱電機株式会社 Frame for semiconductor devices
JPS6181154U (en) * 1984-10-31 1986-05-29
JPS61134048U (en) * 1985-02-09 1986-08-21

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