JPS58218866A - Snubber circuit for gate-turnoff thyristor for power - Google Patents
Snubber circuit for gate-turnoff thyristor for powerInfo
- Publication number
- JPS58218866A JPS58218866A JP8394982A JP8394982A JPS58218866A JP S58218866 A JPS58218866 A JP S58218866A JP 8394982 A JP8394982 A JP 8394982A JP 8394982 A JP8394982 A JP 8394982A JP S58218866 A JPS58218866 A JP S58218866A
- Authority
- JP
- Japan
- Prior art keywords
- snubber circuit
- snubber
- capacitor
- circuit
- auxiliary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Thyristor Switches And Gates (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電力用サイリスタ、特にゲート・ターン・オ
フサイリスタ(以下、GTOという)のスナバ回路の改
良に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a snubber circuit for a power thyristor, particularly a gate turn-off thyristor (hereinafter referred to as GTO).
第1図は、従来の電力用GTOのスナバ回路の一例を示
す。FIG. 1 shows an example of a conventional power GTO snubber circuit.
すなわち、GTOlのアノード、カソード間にダイオー
ド2(DB)とコンデンサ3(Cs)とを直列に接続し
たものをGTOlに並列接続し、さらにダイオード2に
抵抗3(Rs)を並列接続してスナバ回路4を構成して
いる。That is, a snubber circuit is created by connecting a diode 2 (DB) and a capacitor 3 (Cs) in series between the anode and cathode of the GTOl in parallel to the GTOl, and further connecting a resistor 3 (Rs) in parallel to the diode 2. 4.
ところで、GTOIのゲートに負バイアスを与えてター
ンオフさせようとすると、実際の電力スイッチンーグ回
路では必然的に有限のインダクタンスが存在し、GTO
Iのアノード電流下降期間程度の短かい時間、すなわち
、数マイクロ秒以下の時間、電流スイッチング回路は定
電流動作する。By the way, when trying to turn off the GTOI by applying a negative bias to the gate, there is inevitably a finite inductance in an actual power switching circuit, and the GTO
The current switching circuit operates at a constant current for a short period of time as long as the anode current falling period of I, that is, for a period of several microseconds or less.
そこで、上記のようにGTo、1にスナバ回路4を付加
して、動作させる。Therefore, as described above, the snubber circuit 4 is added to GTo,1 and it is operated.
すなわち、GTOIをゲート負バイアスすると、アノー
ド、カソード間のインピーダンスが急激に増加して第2
図に示すようにアノード電流iAが減少しようとする。In other words, when the gate of GTOI is negatively biased, the impedance between the anode and cathode increases rapidly and the second
As shown in the figure, the anode current iA tends to decrease.
この時、ダイオード2とコンデンサ3で構成される容量
性電流パスを付加することによって、回路電流は過渡的
にGTO1がらスナバ回路4へと移る(is)。かがる
作用によって、GTOIに加わるアノード電圧の電流上
昇率(di/dt)は、最大アノード電流ITとコンデ
ンサC8の容量の比、すなわち”/Csで決る値に押え
られる。At this time, by adding a capacitive current path composed of a diode 2 and a capacitor 3, the circuit current is transiently transferred from the GTO 1 to the snubber circuit 4 (is). Due to this effect, the current increase rate (di/dt) of the anode voltage applied to the GTOI is suppressed to a value determined by the ratio of the maximum anode current IT to the capacitance of the capacitor C8, that is, "/Cs."
このため、下降期間(tf)及びその後の期間で発生す
る電力損失を・妥当な値に押えることができ、大きなア
ノード電流−(iA)を遮断し得る。Therefore, the power loss occurring during the falling period (tf) and the subsequent period can be suppressed to a reasonable value, and a large anode current -(iA) can be cut off.
GTOIの可制御アノード電流ITは、スナバ回路4の
コンデンサCsの値に大きく依存し、例えば、第3図の
ような関係を示す。The controllable anode current IT of the GTOI largely depends on the value of the capacitor Cs of the snubber circuit 4, and shows a relationship as shown in FIG. 3, for example.
実際の装置、例えばモ〜り制御用インバータに・おいて
はモータ起動時に大きな電流が流れ、定速運転時には、
これよりもがなり大幅に低い電流が流れる。このような
場合にスナバ用コンデンサの容量は、最大負荷電流を遮
断するのに十分な値に選ぶ必要がある。In an actual device, such as an inverter for motor control, a large current flows when the motor starts, and during constant speed operation,
This results in a significantly lower current flow. In such a case, the capacitance of the snubber capacitor must be selected to a value sufficient to cut off the maximum load current.
例えば、第1図に示す従来のスナバ回路において直流6
00V、最大負荷時600Aの電流を遮断する必要があ
るとすれば、スナバ用コンデンサcsの容量は、第3図
から2μF必要であるこ゛”hが分る。For example, in the conventional snubber circuit shown in FIG.
If it is necessary to cut off a current of 600 A at 00 V and maximum load, it can be seen from FIG. 3 that the capacitance of the snubber capacitor cs needs to be 2 μF.
このスナバ用コンデンサC8に蓄積された電荷は、次の
オン期間中に主として、放電抵抗RS中で消費される。The charge accumulated in this snubber capacitor C8 is mainly consumed in the discharge resistor RS during the next on-period.
したがって、スナバ回路のスイッチング損失(8)は、
下記の式によって決る値となる。Therefore, the switching loss (8) of the snubber circuit is
The value is determined by the formula below.
E = 1 /2 Cs ・VDM2・f [W] −
・・’−−’・(1)上記(1)式において、C8・・
・スナバ用コンデンサ、VDM・・・最大負荷電流、f
・・GTOのスイッチング周波数とする。E = 1 /2 Cs ・VDM2・f [W] −
...'--' (1) In the above formula (1), C8...
・Snubber capacitor, VDM...Maximum load current, f
...Switching frequency of GTO.
しかるに、上記(1)弐K CB ”” 2 μF +
VDM−60OA、f=500Hzを代入す唇・
、9゜E” ’/2Cs−Vo
M2・f = 1/2X2XIO’x(6X10”)”
x ’5xlO−180C児、すなわち、第1
図に示すスナバ回路4を付加することによりisowの
スイッチング損失を生じ、このことがGTOを用いた装
置の効率を悪化させ、実用的な周波数の上限を低くして
いる。However, the above (1) 2K CB ”” 2 μF +
VDM-60OA, lips to substitute f=500Hz・
,9゜E'''/2Cs-Vo
M2・f = 1/2X2XIO'x (6X10")"
x'5xlO-180C infant, i.e. 1st
The addition of the snubber circuit 4 shown in the figure causes a switching loss of isow, which deteriorates the efficiency of the device using the GTO and lowers the upper limit of the practical frequency.
また、事故時の負荷電流を遮断する際にも同様−な問題
がある。A similar problem also occurs when interrupting load current in the event of an accident.
上nCのように装置起動時の短時間若しくはまれに発生
する事故時の大きな負荷電流を遮断するために従来では
容量の大きなスナバ用コンデンサをイボ加しなげればな
らず、そのためにスナバ回路中で大きなスイッチング電
力損失が発生している。Conventionally, a snubber capacitor with a large capacity had to be added in order to cut off a large load current during a short period of time when the device was started up or during an accident that rarely occurred, as shown in the above nC. Large switching power losses occur.
しかるに、定常運転時の負荷電流は、この半分程度の低
い値に゛なる場合が多い。例えば、直流600V回路で
、−起動時等の過渡時若しくは事故時の遮断電流が60
OAであるとすると、スナバ用コンデンサ(CS)は、
2μFであるのに対し、定常運転時の負荷電流が30O
Aの場合、C8は、第3図よt)O,SμFで良(・こ
ととなる。However, the load current during steady operation is often about half this low value. For example, in a 600V DC circuit, the breaking current during transients such as -starting or during an accident is 60V.
If it is OA, the snubber capacitor (CS) is
2μF, while the load current during steady operation is 30O
In the case of A, C8 is good (t) O, SμF as shown in Fig. 3.
本発明は、上記の考察の下になされたもので、従来のス
ナバ回路に過渡負荷時若しくは事故電流遮断時のみ動作
し、その電力損失を無視し得る補助スナバ回路を付加し
たことを特徴とする電力用サイリスタ、特にGTOのス
ナバ回路を提供することを目的とする。The present invention has been made based on the above consideration, and is characterized by adding an auxiliary snubber circuit to the conventional snubber circuit, which operates only during transient loads or interruption of fault current, and whose power loss can be ignored. The present invention aims to provide a snubber circuit for a power thyristor, particularly for a GTO.
以下に、本発明の一実施例を図面を参照して説明する。An embodiment of the present invention will be described below with reference to the drawings.
第4図において、GTO10のアノニド、カソード間に
、スナバ用コンデンサ11(C8D)ト、コノコンデン
サC8Dの充電時に容量性電流パスを形成するためのダ
イオード12(Da)とを直列接続したものを並列接続
し、またダイオードDSには、スナバ用コンデンサCS
aの蓄積電荷放電用抵抗13(R2O)を並列接続し、
スナバ回路14を形成する。このスナバ回路14に、本
発明に係る補助スナバ回路15を付加する。In Fig. 4, a snubber capacitor 11 (C8D) and a diode 12 (Da) for forming a capacitive current path when charging the condenser capacitor C8D are connected in series between the anonide and cathode of GTO10. A snubber capacitor CS is connected to the diode DS.
The accumulated charge discharge resistor 13 (R2O) of a is connected in parallel,
A snubber circuit 14 is formed. An auxiliary snubber circuit 15 according to the present invention is added to this snubber circuit 14.
すなわち、補助スナバ回路15ば、重負荷時に付加する
容量性電流パス制御用のサイリスタ、GTO等の同期ス
イッチング素子16 (、THYs )と補助スナバ用
コンデンサ17 (C3THY )とを直列接続し、前
記同期スイッチング素子16には、補助スナバ用コンデ
ンサC8THYの蓄積電荷放電用抵抗18(R8TII
Y)と、定常時に前記抵抗R81HYを通して補助スナ
ノ(コンデンサC3TIIYが充電されるのを防止する
ための逆並列のダイオード19(DTHY)とが並列接
続されている。That is, the auxiliary snubber circuit 15 connects in series a synchronous switching element 16 (,THYs) such as a thyristor or GTO for capacitive current path control added during heavy loads, and an auxiliary snubber capacitor 17 (C3THY). The switching element 16 includes a resistor 18 (R8TII) for discharging the accumulated charge of the auxiliary snubber capacitor C8THY.
Y) and an anti-parallel diode 19 (DTHY) for preventing the auxiliary sensor (capacitor C3TIIY) from being charged through the resistor R81HY during normal operation are connected in parallel.
上記の構成において、今、第5図に示すように負荷電流
が定常電流よりも大きくなるようにあらかじめ設定され
たレベルに達した時点(1+)を検出して、補助スナバ
回路15中の同期スイッチング素子16のゲートに電流
パルスを印加する。In the above configuration, as shown in FIG. A current pulse is applied to the gate of element 16.
また、装置の起動時等の正常運転時には所定の通電幅を
経過した後、あるいは事故時には、別の検出回路及びG
−TO10のゲート駆動の応答遅れ時間を経過した後、
−t”2時点でGTOIOのゲートを負バイアスして負
荷電流を遮断する。In addition, after a predetermined energization width has passed during normal operation such as when starting up the device, or in the event of an accident, another detection circuit and G
- After the TO10 gate drive response delay time elapses,
- At time point t''2, the gate of GTOIO is negatively biased to cut off the load current.
この場合、2つのスナバ用コンデンサ11及び17の容
量を前記の負荷条件に合せて例えばCs。In this case, the capacitances of the two snubber capacitors 11 and 17 are adjusted to the above-mentioned load conditions, for example, Cs.
=0.5μF + C3THY = 1.5μFに選牢
すれば、これらのスナバ用コンデンサが並列に接続され
ても・るので、それらを合計した容量は2μFとなり、
したカ1って第3図から60OAまでのアノード電流を
遮断し得ることが分る。If you choose = 0.5μF + C3THY = 1.5μF, these snubber capacitors can be connected in parallel, so their total capacitance will be 2μF,
It can be seen from FIG. 3 that the force 1 can interrupt an anode current of up to 60 OA.
定常運転時には、同期スイッチング素子のゲートに電流
パルスが印加されないので、補助スナバ回路は働かず、
一方のスナバ回路14のスナバ用コンデンサC3D−0
,5μFのみとなるので上記スナバ回路14でのスイッ
チング電力損失は以下の通りとなる。During steady operation, no current pulse is applied to the gate of the synchronous switching element, so the auxiliary snubber circuit does not work.
Snubber capacitor C3D-0 of one snubber circuit 14
, 5 μF, the switching power loss in the snubber circuit 14 is as follows.
E−1/2C8D−vDM2・f=1/2×0.5×1
0−6×6002×5XlO=45[W]
なお、GTOloが500Hzでスイッチングするもの
とする。E-1/2C8D-vDM2・f=1/2×0.5×1
0-6×6002×5XlO=45 [W] Note that it is assumed that GTOlo switches at 500 Hz.
しかして、本発明の補助スナバ回路を伺加することによ
り、そのスイッチング電力損失は従来に比較して45/
18o−1/4に押えることができる。また、スナバ用
コンデンサには、遮断時のGTOのアノード電流にほぼ
等しい充電電流が流れ、しかもこれがかなり高い周波数
で繰り返されるため、一般にこのコンデンサは高価でか
つかさばるもの 5となるが本発明に係る回路′
では、上記の条件が要求されるコンデンサは第4図のC
8Dのみで、補助スナバ用コンデンサC3THYは、充
電電流の流れる頻度が非常に少ないため小型かつ安価な
もので良い。However, by adding the auxiliary snubber circuit of the present invention, the switching power loss is reduced by 45% compared to the conventional one.
It can be reduced to 18o-1/4. In addition, a charging current approximately equal to the anode current of the GTO at the time of shutoff flows through the snubber capacitor, and this is repeated at a fairly high frequency, so this capacitor is generally expensive and bulky. circuit'
So, the capacitor that requires the above conditions is C in Figure 4.
8D only, the auxiliary snubber capacitor C3THY may be small and inexpensive because the charging current flows very infrequently.
したがって、本発明の回路に係るスナノ(用コンデンサ
は2つを合計しても、コスト、体積とも従来のそれに比
し、大幅に低減できる。Therefore, even if the two capacitors used in the circuit of the present invention are combined, both cost and volume can be significantly reduced compared to conventional capacitors.
また、新たに付加された同期スイッチング素子、ダイオ
ード、抵抗の費用とスペースとを考慮しても十分に補い
得るものである。Moreover, even if the cost and space of newly added synchronous switching elements, diodes, and resistors are considered, it can be sufficiently compensated for.
第6図は、本発明に係る他の実施例を示すもので、ブリ
ッジインバータ回路に補助スナノ(回路をイ」加したも
のである。FIG. 6 shows another embodiment of the present invention, in which an auxiliary sensor circuit is added to the bridge inverter circuit.
すなわち、GTO20,21等すべてのGTOに対して
補助スナバ回路22を付加するのではなく、直流のプラ
ス((−)若しくはマイナス(−)電位のいずれか一方
(図示では(+)電位側)のGTO20のみに付加し、
その他のGTO21等には、従来のスナバ回路23のみ
を付加したものである。In other words, instead of adding the auxiliary snubber circuit 22 to all GTOs such as GTOs 20 and 21, it is necessary to add the auxiliary snubber circuit 22 to either the DC plus ((-) or minus (-) potential (in the figure, the (+) potential side). Added only to GTO20,
Other GTOs 21 and the like have only a conventional snubber circuit 23 added thereto.
上記の実施例でも、前記の同様な作用により、スナバ回
路で発生するスイッチング電力損失を従来のそれに比較
して数分の1に低減でき、装置の効率も大幅に改良され
る。In the above embodiment as well, due to the same effect as described above, the switching power loss generated in the snubber circuit can be reduced to a fraction of that of the conventional snubber circuit, and the efficiency of the device is also significantly improved.
特に素子数の増加するに従って、′”費用、スペース等
の低減への寄与率が大きい。In particular, as the number of elements increases, the contribution to reductions in costs, space, etc. increases.
第1図は、電力用GTOのスナバ回路の一例を示し、第
2図は、その電圧、電流波形図、第3図は、可制御アノ
ード電流とスナバ用コンデンサ容量との関係を示す図、
第4図は、本発明に係るスナ・ぐ回路図、第5図は、重
負荷時の負荷電流、補助スナバ回路の同期スイッチング
素子のゲート電流及び主GTOのゲート電流波形図、第
6図は、本発明の他の実施例を示し、ブリッジインバー
タ回路に補助スナバ回路を付加した図である。
10・・・GTOl 11・・・スナバ用コンデンサ
、12・・°ダイオード、 13・・・抵 抗、14
・・・スナバ回路、 15・・・補助スナバ回路、
16・・・同期スイッチング素子、
17・・・補助スナバ用コンデンサ、18・・・抵 抗
、19・・・ダイオード
出願代理人 弁理士 菊 池 五 部
早 l 図
第 2 図
0 0.5 /、θ
/、5 2.0スナバ■コンデンサ C
s〔pF)
弗4 @
45 図
早 6 図
、23 、22FIG. 1 shows an example of a snubber circuit of a power GTO, FIG. 2 is a voltage and current waveform diagram thereof, and FIG. 3 is a diagram showing the relationship between controllable anode current and snubber capacitor capacity.
Fig. 4 is a snubber circuit diagram according to the present invention, Fig. 5 is a waveform diagram of the load current during heavy load, the gate current of the synchronous switching element of the auxiliary snubber circuit, and the gate current of the main GTO. , which shows another embodiment of the present invention, in which an auxiliary snubber circuit is added to the bridge inverter circuit. 10...GTOl 11...Snubber capacitor, 12...° diode, 13...Resistor, 14
... Snubber circuit, 15... Auxiliary snubber circuit,
16...Synchronous switching element, 17...Auxiliary snubber capacitor, 18...Resistor, 19...Diode application agent Patent attorney Kikuchi Gobe Haya l Figure 2 Figure 0 0.5 /, θ
/, 5 2.0 Snubber ■Capacitor C
s[pF] 弗4 @ 45 Figure Haya 6 Figure, 23, 22
Claims (1)
ード間にスナバ回路を接続したものにおいて、前記スナ
バ回路に過渡負荷時若しくは事故電流遮断時のみ動作し
、そのスイッチング電力損失を無視し得る補助スナバ回
路を接続したことを特徴とする電力用ゲート・ターン・
オフサイリスタのスナバ回路。 − 2、前記補助スナバ回路は、前記スナバ回路に並列接続
された同期スイッチング素子及びこの素子に直列接続さ
れた補助スナバ用コンデンサと、前″記スイッチング素
子に逆並列に接続され、かつ定常時に前記コンデンサの
充放電を防止するためのダイオードとから成ることを特
徴とする特許請求の範囲第1項の電力用ゲート・ターン
・オフサイリスクのスナバ回路。[Claims] 1. In a gate turn-off thyristor with a snubber circuit connected between the anode and cathode, the snubber circuit operates only when a transient load or fault current is cut off, ignoring the switching power loss. A power gate, turn,
Off-thyristor snubber circuit. -2. The auxiliary snubber circuit includes a synchronous switching element connected in parallel to the snubber circuit, an auxiliary snubber capacitor connected in series to this element, and an auxiliary snubber capacitor connected in antiparallel to the switching element, and in a steady state, A power gate turn-off risk snubber circuit according to claim 1, comprising a diode for preventing charging and discharging of a capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8394982A JPS58218866A (en) | 1982-05-20 | 1982-05-20 | Snubber circuit for gate-turnoff thyristor for power |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8394982A JPS58218866A (en) | 1982-05-20 | 1982-05-20 | Snubber circuit for gate-turnoff thyristor for power |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58218866A true JPS58218866A (en) | 1983-12-20 |
Family
ID=13816833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8394982A Pending JPS58218866A (en) | 1982-05-20 | 1982-05-20 | Snubber circuit for gate-turnoff thyristor for power |
Country Status (1)
Country | Link |
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JP (1) | JPS58218866A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855887A (en) * | 1987-09-30 | 1989-08-08 | Hitachi, Ltd. | Current and frequency converter having means to reduce switching losses |
KR100927090B1 (en) | 2008-02-05 | 2009-11-13 | 엘에스산전 주식회사 | Snubber Circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57151268A (en) * | 1981-03-14 | 1982-09-18 | Fuji Electric Co Ltd | Overvoltage protecting circuit for gto thyristor |
-
1982
- 1982-05-20 JP JP8394982A patent/JPS58218866A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57151268A (en) * | 1981-03-14 | 1982-09-18 | Fuji Electric Co Ltd | Overvoltage protecting circuit for gto thyristor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855887A (en) * | 1987-09-30 | 1989-08-08 | Hitachi, Ltd. | Current and frequency converter having means to reduce switching losses |
KR100927090B1 (en) | 2008-02-05 | 2009-11-13 | 엘에스산전 주식회사 | Snubber Circuit |
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