JPS5821867A - P-n-p-n type semiconductor switch - Google Patents
P-n-p-n type semiconductor switchInfo
- Publication number
- JPS5821867A JPS5821867A JP12064481A JP12064481A JPS5821867A JP S5821867 A JPS5821867 A JP S5821867A JP 12064481 A JP12064481 A JP 12064481A JP 12064481 A JP12064481 A JP 12064481A JP S5821867 A JPS5821867 A JP S5821867A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- type diffusion
- diffusion region
- type
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000003287 optical effect Effects 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims 2
- 239000006185 dispersion Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000001052 transient effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/111—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、高感度光駆動型ＰＮＰＮ半導体スイッチを
別の駆動用ＬＥＤ （発光ダイオード）によシ、オフさ
せる機能をもたせた半導体ＰＮＰＮスイッチに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-sensitivity optically driven type PNPN semiconductor switch having a function of turning off the switch by using another driving LED (light emitting diode).
従来の半導体ＰＮＰＮスイッチを第１図（４）、第１図
の）（第１図囚 の素子概念図）に示す。この第１図囚
、第１図ＣＢ）の両図において、■はＮ形基板であり、
２はアノード領域、３はＰ）ｆ−）領域、４はデート・
カソード間抵抗Ｒ６Ｋ１５はＰＮＰＮのカソード領域で
ある。A conventional semiconductor PNPN switch is shown in Fig. 1 (4) (Fig. 1) (conceptual diagram of the element in Fig. 1). In both figures (Figure 1) and Figure 1 (CB), ■ is an N-type board,
2 is the anode area, 3 is the P) f-) area, and 4 is the date area.
The inter-cathode resistance R6K15 is a PNPN cathode region.
アノード領域２にはアノード電極が接合され、このアノ
ード電極１２にアノード端子１２′が接続されている。An anode electrode is joined to the anode region 2, and an anode terminal 12' is connected to the anode electrode 12.
また、カソード領域５にはカソード電極１３が接合され
ておシ、このカソード電極１３、にはカソード端子１３
′が接続されている。Further, a cathode electrode 13 is connected to the cathode region 5, and a cathode terminal 13 is connected to the cathode electrode 13.
′ is connected.
通常のＰＮＰＮスイッチ駆動では、ＬＥＤなどのトリガ
によ、９Ｎ形基板１とＰ）ｌｋ−）領域３の境界のデー
ト接合部に光電流が発生し、このｐ）１′Ｎ−）領域３
とカソード領域５の境界のカソード接合とデート・カソ
ード間抵抗（ＲＧＫ） ４に渦状電流が流れ、’ｔ’
−１−・、／Ｊ ソー Ｆ間抵抗ＣＲＧＫ） ４ （７
１’−ト・カソード間クランプによりスイッチがオン状
態と々る。In normal PNPN switch driving, a photocurrent is generated at the date junction at the boundary between the 9N type substrate 1 and the P)lk-) region 3 by a trigger such as an LED, and this p)1'N-) region 3
An eddy current flows through the cathode junction at the boundary between the cathode region 5 and the date-cathode resistance (RGK) 4, and 't'
-1-・, /J So F resistance CRGK) 4 (7
The switch is turned on by clamping between the 1' and cathodes.
しかし、オフ機能がないため、ＰＮＰＮスイッチ外部で
制御する方法（外部でのバイアス電圧を断ち切るなど）
でしかオフ状態に切シ換えることができ々い欠点がある
。However, since there is no off function, there is a method of controlling the PNPN switch externally (cutting off the bias voltage externally, etc.)
It has the disadvantage that it can only be switched to the off state.
さらに、オン状態が必要以上に続くために、不要な電力
消費量を余義なくせざるを得ないなどの欠点もあった。Furthermore, since the on state continues longer than necessary, there is also a drawback that unnecessary power consumption is inevitable.
この発明は、上記従来の欠点を除去するためになされた
もので、従来の光駆動形ＰＮＰＨの同一基板上に第１０
ケゞ−ト電極と同時にプロセス的に形成可能なホトダイ
オード回路を付加し、光駆動によるオフ機能をもたせ、
外部回路でのオフ操作が不要になシ、空間的に分離され
た制御系の操作のみとすることができ、交換機用通話路
スイッチなどのスイッチの分野に広範囲に利用すること
のできるＰＮＰＮ半導体スイッチを提供することを目的
とする。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method.
By adding a photodiode circuit that can be formed simultaneously with the gate electrode through a process, it has a light-driven off function.
A PNPN semiconductor switch that does not require an external circuit to turn off and can only be operated by a spatially separated control system, and can be widely used in the field of switches such as communication path switches for exchanges. The purpose is to provide
以下、この発明のＰＮＰＮ半導体スイッチの実施例につ
いて図面に基づき説明する。第２図（４）はその一実施
例の構成を示す素子ＭＩＬ図、第２図の）はその素子概
念図である。この第２図囚、第２図ＣＢ）の両図におい
て、】はＮ形基板、２はアノード領域、３はＰデート領
域であシ、これらは第１図囚、第１図（Ｂ）の場合と同
様である。Embodiments of the PNPN semiconductor switch of the present invention will be described below with reference to the drawings. FIG. 2(4) is a device MIL diagram showing the configuration of one embodiment, and FIG. 2(4) is a conceptual diagram of the device. In both Figures 2 and CB), ] is the N-type substrate, 2 is the anode region, and 3 is the P date region. Same as in case.
また、図中のａ、ｂはこの実施例の場合、ポリシリコン
ＰＮ接合で４この場合はポリシリコンＰＮ接合の数（Ｎ
−１）個が２個の場合である。また、２１ ＊ ２３は
Ｎ形ポリシリコンに形成したＰＮ拡散領域、２２．２４
はＮ形ポリシリコンに形成したＮ＋拡散領域である。In addition, in this example, a and b in the figure are polysilicon PN junctions (4), and in this case, the number of polysilicon PN junctions (N
-1) This is a case where there are two pieces. In addition, 21*23 is a PN diffusion region formed in N-type polysilicon, and 22.24
is an N+ diffusion region formed in N-type polysilicon.
さらに、２５．２７はそれぞれポリシリコンＰＮ接合ａ
、ｂのＰ側電極、２６．２８はそれぞれ＝ｐ： ＋Ｊシ
リコンａ、ｂのＮ側電極であり、２９ｆｄＮ個のポリシ
リコンのうちＰＮ接合を形成しカい残シ１個を抵抗とし
て用いたものでアシ、さらに、３０は第１ｒ−ト電極と
コンタクトをとるための電極である。Furthermore, 25 and 27 are respectively polysilicon PN junctions a
, b are the P-side electrodes, and 26.28 are the N-side electrodes of =p: +J silicon a, b, respectively. Among the 29fdN polysilicon pieces, a PN junction was formed and one remaining piece was used as a resistor. Furthermore, 30 is an electrode for making contact with the first electrode.
以下の説明においては、ポリシリコンＰＮ接合ａ、ｂを
それぞれ第１０ＰＮ接合、第２のＰＮ接合と呼び、これ
らはフォトダイオードとして用いる。この第１のＰＮＮ
接合の電極２６と第２のＰＮ接合すの電極２７とを接続
し、第１のＰＮＮ接合の電極２５と第１’Ｆ’ −ト電
極３０とを接続し、第２のＰＮ接合の電極２８とＰＮＰ
Ｎ素子のカソード電極３２を接続している。In the following description, polysilicon PN junctions a and b will be referred to as a tenth PN junction and a second PN junction, respectively, and will be used as photodiodes. This first PNN
The junction electrode 26 and the second PN junction electrode 27 are connected, the first PNN junction electrode 25 and the first 'F'-to electrode 30 are connected, and the second PN junction electrode 28 is connected. and PNP
The cathode electrodes 32 of N elements are connected.
さらに、高抵抗として形成したポリシリコン抵抗２９の
一方の端子を第１のＰＮＮ接合の電極２５へ接続し、他
方の端子を第２のＰＮ接合すの電極２８へ接続する。Further, one terminal of a polysilicon resistor 29 formed as a high resistance is connected to the electrode 25 of the first PNN junction, and the other terminal is connected to the electrode 28 of the second PN junction.
なお、アノード領域２にアノード電極１２が接続され、
このアノード電極１２にアノード端子１２′が接続され
ている。また、ｐ）ｆ−）領域３に第１のＮ形拡散領域
３５、第２のＮ形拡散領域３６が形成されておシ、この
第１のＮ形拡散領域３５にカソード電極１３が接合され
、このカソード電極１３にカソード端子３３が接続され
ている。Note that an anode electrode 12 is connected to the anode region 2,
An anode terminal 12' is connected to this anode electrode 12. Furthermore, a first N-type diffusion region 35 and a second N-type diffusion region 36 are formed in the p)f-) region 3, and the cathode electrode 13 is bonded to the first N-type diffusion region 35. , a cathode terminal 33 is connected to this cathode electrode 13.
また、３４はゲート・カソード間抵抗を示し、３７はｐ
）ｆ−トとドレインとのコンタクト部を示しており、３
１は第１）ｆ−）電極である。Further, 34 indicates the resistance between the gate and cathode, and 37 indicates the p
) shows the contact part between f-t and drain, and 3
1 is the first) f-) electrode.
次に、以上のように構成されたこの発明のＰＮＰＮ半導
体スイッチにおいて、ＰＮＰＮスイッチをオンさせるた
めのＬＥＤとは別系統のＬＥＤによシ、前記（Ｎ−１）
個（第２図へ・、第２図（Ｂ）では２個）のポリシリコ
ンＰＮ接合に光を照射すればよい。Next, in the PNPN semiconductor switch of the present invention configured as described above, an LED of a different system from the LED for turning on the PNPN switch is used (N-1).
It is sufficient to irradiate light onto two polysilicon PN junctions (see FIG. 2, two in FIG. 2(B)).
このとき、（Ｎ−１）個（この実施例では２個）のＰＮ
接合に発生する光電流が放電用高抵抗であるポリシリコ
ン抵抗２９を流れることによシ、このポリシリコン抵抗
２９の両端の電圧降下がそのまま第１デート電極３１に
加わシ、第１のＮ形拡散領域３５をソース、第２のＮ形
拡散領域３６をドレインとするＮ−ＭＯＳが導通し、さ
らに、第１のＮ形拡散領域３５と第２のＮ形拡散領域３
６との間にチャンネルができる。At this time, (N-1) (two in this example) PN
When the photocurrent generated at the junction flows through the polysilicon resistor 29, which has a high resistance for discharging, the voltage drop across the polysilicon resistor 29 is directly applied to the first date electrode 31. The N-MOS having the diffusion region 35 as the source and the second N-type diffusion region 36 as the drain is electrically conductive, and further, the first N-type diffusion region 35 and the second N-type diffusion region 3
A channel will be created between 6 and 6.
とのため、第１’Ｆ’−）電極３１に電圧が加わる以前
にＰＮＰＮスイッチのカソード接合を流れていた電流が
Ｐｒ−）とドレインとのコンタクト部３７を介して、カ
ソード端子３２に抜は出る。したがって、デート・カソ
ード間抵抗３４による電圧降下は消滅してスイッチはオ
フする。Therefore, the current flowing through the cathode junction of the PNPN switch before the voltage is applied to the first 'F'-) electrode 31 is drawn out to the cathode terminal 32 via the contact portion 37 between Pr-) and the drain. Get out. Therefore, the voltage drop caused by the date-cathode resistor 34 disappears and the switch is turned off.
上記ポリシリコンＰＮ接合には、接合容量が介在するた
め、オフ回路には、この接合容量とポリシリコン抵抗２
９による時定数があり、オフ回路が十分な時間、第１デ
ート電極３１に電圧を印加し続けるには、このポリシリ
コン抵抗２９を十分大きく設定し々ければならない（数
Ω程度）。Since the polysilicon PN junction has a junction capacitance, the off-circuit includes this junction capacitance and the polysilicon resistance 2.
There is a time constant of 9, and in order for the off-circuit to continue applying voltage to the first date electrode 31 for a sufficient period of time, this polysilicon resistor 29 must be set sufficiently large (on the order of several ohms).
以上説明したように、上記第１の実施例では、従来のＰ
ＮＰＮ半導体スイッチにオン状態からオフ状態へ切シ換
える光駆動方式のオフ回路を一体化し、同一基板上に構
成しているため、第３図（５）（従来のＰＮＰＮ半導体
スイッチのオフ回路の機能を示す図）に示すように、オ
フ時に必要なスイッチ側（破線の左側）でのスイッチＳ
、の操作が第３図（功（この発明のＰＮＰＮ半導体スイ
ッチのオン、オフ回路の機能を示す図）のように、回路
のオン、オフはすべてこの回路とは空間的に分離された
制御系（第３図（Ｂ）の破線の右側）の操作のみとなシ
、回路全体のシステムの統一の面で大きな効果がある。As explained above, in the first embodiment, the conventional P
Since the NPN semiconductor switch is integrated with a light-driven off circuit that switches from the on state to the off state and is configured on the same substrate, it is possible to reduce The switch S on the switch side (to the left of the dashed line) required for turning off, as shown in
As shown in Figure 3 (a diagram showing the functions of the on/off circuit of the PNPN semiconductor switch of the present invention), the on/off of the circuit is controlled by a control system that is spatially separated from this circuit. This operation alone (to the right of the broken line in FIG. 3(B)) has a great effect on unifying the entire circuit system.
なお、第３図囚では、Ｌ Ｅ Ｄ ＬｌはＰＮＰＮス
イッチオン用のみでちゃ、第３図（６）では、ＬＥＤ
Ｌ。In addition, in Figure 3, L E D Ll is only for turning on the PNPN switch, and in Figure 3 (6), it is for LED.
L.
はＰＮＰＮスイッチオン用で、ＬＥＤ ＬｍはＩ）Ｎ
ＰＮスイッチオン用である。is for turning on the PNPN switch, and LED Lm is I)N
This is for turning on the PN switch.
また、オフ回路を構成するポリシリコン抵抗２９、フォ
トダイオードを第１ゲート電極３１と同時に形成するこ
とが可能で、スイッチの機能が余分に付加されたにもか
かわらず、製造工程での複雑化をきたすことなくできる
。In addition, it is possible to form the polysilicon resistor 29 and photodiode constituting the off-circuit at the same time as the first gate electrode 31, which reduces the complexity of the manufacturing process even though an extra switch function is added. It can be done without any harm.
以上のように、この発明のＰＮＰＮ半導体スイッチによ
れば、従来の光駆動形のＰＮＰＮ半導体スイッチの同一
基板上に第１ゲート電極と同時にプロセス的に形成する
ことができるホトダイオード回路を付加し、光駆動によ
るオン機能に加えて、オフ機能を有するようにしたので
、外部回路でのオフ操作が不要になシ、空間的に分離さ
れた制御系の操作のみとなる利点があシ、オン、オフの
集中操作ができるため、交換機用通話路スイッチをはじ
めとして、あらゆるスイッチの分野に利用することがで
きる。As described above, according to the PNPN semiconductor switch of the present invention, a photodiode circuit that can be formed simultaneously with the first gate electrode on the same substrate as the conventional optically driven PNPN semiconductor switch is added, and an optical In addition to the on function by driving, it also has an off function, so there is no need for off operation in an external circuit, and there is an advantage that only a spatially separated control system can be operated. Since it can be operated centrally, it can be used in all switch fields, including communication path switches for exchanges.
第１図囚は従来のＰＮＰＮ半導体スイッチの素子構造図
、第１図（Ｂ）は従来のＰＮＰＮ半導体スイッチの素子
概念図、第２図囚はこの発明のＰＮＰＮ半導体スイッチ
の一実施例の素子構造図、第２図（Ｂ）はこの発明のＩ
） Ｎ Ｐ Ｎ半導体スイッチの一実施例の素子概念図
、第３図（４）は従来のＰＮＰＮ半導体スイッチのオン
機能を示す図、第３図■）はこの発明のＰＮＰＮ半導体
スイッチのオン、オフ機能を示す図である。
ｌ・・・Ｎ形基板、２・・・アノード領域、３・・・Ｐ
ゲート領域、１２・・・アノード電極、１３・・・カソ
ード電極、２１，２３・・・Ｐ形拡散領域、２２．２４
・・・Ｎ＋拡散領域、２５，２７・・・Ｐ側電極、２６
．２８・・・Ｎ側電極、２９．ポリシリコン抵抗、３０
、３６・・・コンタクト部、３１・・・第１ケ９−ト
電極、３２・・・カソード端子、３３・・・アノード端
子、３４・・・デート・カソード間抵抗、３５・・・第
１のＮ形拡散領域、３６・・・第２のＮ形拡散領域。
特許出願人 沖電気工業株式会社
第３図
手続補正書
昭和５６年１２月１６０
特許庁長官 島田春樹殿
１、事件の表示
昭和５６年 特 許 願第１２０６４４ 号２、発明
の名称
ＰＮＰＮ半導体スイッチ
３、補正をする者
事件との関係 特 許 出願人（０２９）沖電
気工栗株式会社
４、代理人
５、補正命令の目付 昭和 年 月 口（自発
）６、補正の対象
明却１書の発明の詳細な説明の欄
７、補正の内容
別紙の通り
７、 補正の同容
１）明細書３頁１８行「過渡電流」を「過渡電流」と訂
正する。
２）同４頁７行「消費量」を「消費」と訂正する。
３）同８頁５行「数Ω」を「数ＭΩ」と訂正する。FIG. 1(B) is an element structure diagram of a conventional PNPN semiconductor switch, FIG. 1(B) is a conceptual diagram of an element of a conventional PNPN semiconductor switch, and FIG. Figure 2(B) shows I of this invention.
) A conceptual diagram of an element of an embodiment of an N P N semiconductor switch, FIG. 3 (4) is a diagram showing the on function of a conventional PNPN semiconductor switch, and FIG. It is a figure showing a function. l...N-type substrate, 2...anode region, 3...P
Gate region, 12... Anode electrode, 13... Cathode electrode, 21, 23... P-type diffusion region, 22.24
...N+ diffusion region, 25, 27...P side electrode, 26
．． 28...N side electrode, 29. Polysilicon resistor, 30
, 36... Contact portion, 31... First gate electrode, 32... Cathode terminal, 33... Anode terminal, 34... Date-cathode resistance, 35... First N-type diffusion region, 36... second N-type diffusion region. Patent Applicant Oki Electric Industry Co., Ltd. Figure 3 Procedural Amendment December 1980 160 Commissioner of the Patent Office Haruki Shimada 1, Indication of Case 1981 Patent Application No. 120644 2, Name of Invention PNPN Semiconductor Switch 3, Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Weight of amendment order Showa month, month, year 6 (self-motivated) 6, Invention of the subject of amendment 1 Detailed Explanation Column 7, Contents of Amendment As shown in Attachment 7, Same content as amendment 1) "Transient current" on page 3, line 18 of the specification is corrected to "transient current." 2) On page 4, line 7, "consumption amount" is corrected to "consumption." 3) On page 8, line 5, “several Ω” is corrected to “several MΩ”.
Claims (2)
１のＰ形拡散領域から所定の距離だけ離間して前記Ｎ形
半導体基板内に第２のＰ形拡散領域とを配置したＰＮＰ
Ｎ半導体スイッチにおいて、この第２のＰ形拡散領域内
に第１のＮ形拡散領域とこの第１のＮ形拡散領域から所
定の距離だけ離間して前記第２のＰ形拡散領域内に第２
のＮ形拡散領域とを配置し、この第２のＮ形拡散領域と
前記第１のＮ形拡散領域間の前記第２のＰ形拡散領域光
面に第１および第２のＮ形拡散領域上の一部に延存する
ように絶縁層を配置し、この絶縁層の部位に第１と第２
のＮ形拡散領域相互間上になるように少なくとも第１の
デート電極を配置、し、前記Ｎ形半導体基板上に前記第
１と第２のＰ形拡散領域と所定の距離だけ離間した別の
位置にも絶縁層を設け、この絶縁層の部位にポリシリコ
ンなどの高抵抗体を基板とした層をＮ個設け、このＮ個
のうちの（Ｎ−１）個はＰ形拡散領域とこのＰ形拡散領
域とは所定の距離だけ離間した位置に設けるＮ拡散領域
とを具備して形成させたホトダイオード部とし、この第
１番目から第（Ｎ−１）番目の（Ｎ−１）個の前記ホト
ダイオード部は電気的に同一方向に直列接続し、第１番
目のホトダイオード部のＰ形拡散領域と第Ｎ番目の前記
層の一端とを前記第１のデート電極に接続させ、第（Ｎ
−１）番目のホトダイオード部のＮ′″に散領域と第Ｎ
番目の前記層の他端とをカソード電極に電気的に接続さ
せるように形成したことを特徴とするＰＮＰＮ半導体ス
イッチ。(1) A first P-type diffusion region is arranged within the N-type semiconductor substrate, and a second P-type diffusion region is arranged within the N-type semiconductor substrate at a predetermined distance from the first P-type diffusion region. PNP
In the N semiconductor switch, a first N-type diffusion region is provided within the second P-type diffusion region, and a second P-type diffusion region is provided within the second P-type diffusion region spaced apart from the first N-type diffusion region by a predetermined distance. 2
an N-type diffusion region, and first and second N-type diffusion regions are disposed on the optical surface of the second P-type diffusion region between the second N-type diffusion region and the first N-type diffusion region. An insulating layer is placed so as to extend over a part of the top, and first and second insulating layers are placed on the insulating layer.
at least a first date electrode is disposed between the N-type diffusion regions of the semiconductor substrate, and another date electrode is arranged on the N-type semiconductor substrate and spaced apart from the first and second P-type diffusion regions by a predetermined distance. An insulating layer is also provided at this location, and N layers using a high-resistance material such as polysilicon as a substrate are provided at the location of this insulating layer, and (N-1) of these N layers are connected to the P-type diffusion region and this layer. The P-type diffusion region is a photodiode section formed with an N-diffusion region provided at a position separated by a predetermined distance, and the first to (N-1)th (N-1) The photodiode sections are electrically connected in series in the same direction, the P-type diffusion region of the first photodiode section and one end of the Nth layer are connected to the first date electrode, and the
−1) Dispersion area and N′″ of the photodiode section
A PNPN semiconductor switch characterized in that the other end of the second layer is electrically connected to a cathode electrode.
形のポリシリ′コンモ形成することを特徴とする特許請
求の範囲第１項記載のＰＮＰＮ半導体スイッチ。(2) The N substrate layers and the first date electrode are
2. A PNPN semiconductor switch as claimed in claim 1, characterized in that it is formed of a polysilicon material having a shape of polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12064481A JPS5821867A (en) | 1981-08-03 | 1981-08-03 | P-n-p-n type semiconductor switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12064481A JPS5821867A (en) | 1981-08-03 | 1981-08-03 | P-n-p-n type semiconductor switch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5821867A true JPS5821867A (en) | 1983-02-08 |
Family
ID=14791320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12064481A Pending JPS5821867A (en) | 1981-08-03 | 1981-08-03 | P-n-p-n type semiconductor switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821867A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5446295A (en) * | 1993-08-23 | 1995-08-29 | Siemens Components, Inc. | Silicon controlled rectifier with a variable base-shunt resistant |
-
1981
- 1981-08-03 JP JP12064481A patent/JPS5821867A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5446295A (en) * | 1993-08-23 | 1995-08-29 | Siemens Components, Inc. | Silicon controlled rectifier with a variable base-shunt resistant |
| US5506152A (en) * | 1993-08-23 | 1996-04-09 | Siemens Components, Inc. | Method of making silicon controlled rectifier with a variable base-shunt resistance |
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