JPS5821844A - Manufacture of wiring structure - Google Patents

Abstract

PURPOSE:To flatten the fluidized insulator layer by burying by a lift-off method air gaps among wiring conductors, and covering by heating flow the surface with flattened fluidized insulator as the interlayer insulating film, thereby preventing the accumulated stepwise difference. CONSTITUTION:A wiring conductor film 2 is formed on a substrate 1, and an etching mask 7 is formed by using a resist on the film 2. The layer 1 is etched with the mask 7, thereby forming the conductor 2. Subsequently, non-fluidized insulators 9, 9' are accumulated on the surface of the mask 7 on the conductor 2 and in the air gap between the conductors 2, and the mask 7 and the insulator 9' accumulated on the mask 7 are removed. Then, a fluidized insulating layer 11 is formed to cover the conductor 2 and the overall surface of the insulator 9 buried in the gap. Thereafter, the substrate is heated to flatten the layer 11'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a wiring structure for a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a wiring structure for a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a wiring structure for a semiconductor device, and more specifically, it relates to a method for manufacturing a wiring structure for a semiconductor device. The present invention relates to a method for manufacturing a structure.

In multilayer wiring technology, as the number of wiring layers increases, a planarization technology that alleviates steps caused by through holes in wiring conductors and interlayer insulating films is essential. Various flattening technologies have been proposed, such as surface flattening technology (GFP; Glas
s Flow Planarization).

However, in the conventional GFP technology, for example,
In the planarization technique as described in No. 6-57939 "Semiconductor Integrated Circuit Device", good flatness is achieved and there are no sharp steps, but gradual long-distance steps still exist.

That is, FIG. 1 is a diagram showing an outline of the flattening technology described in 1. 2 is a substrate, 2 is a wiring conductor, and 3 is a pbo-8i02
This is a low melting point oxide glass of the system, and this is a cross-sectional profile after it has been heated to produce viscous flow. 4 is a long-distance level difference in glass caused by the density of the wiring conductor. The maximum value of this long-distance step 4 corresponds to the step between the densest region of wiring conductors and the region where no wiring conductors are present. Such long-distance steps occur as wiring layers are stacked, and
As the thickness of the wiring conductor increases, the cumulative level difference increases, which limits the number of wiring layers that can be stacked.

In addition, other flattening techniques, such as Japanese Patent Application No. 56-55637
11 by the lift-off method of low melting point oxide glass as described in No. ``Method for Forming Wiring Structure''
In i1, although very desirable flatness was obtained, a slight step (7-shaped groove) still remained. That is, FIG. 2 is a diagram showing an outline of the planarization technique described above, in which 1 is a substrate and 2 is a wiring conductor.

5 is a low melting point oxide glass based on PbO-8i 02, and its cross-sectional profile is shown after it has been heated to produce viscous flow. 6 is a 7-shaped groove, which is determined by the affinity between the wiring conductor 2 and the low melting point oxide glass 5.

Although such figure-7 grooves can be significantly reduced by appropriately selecting the composition of the wiring conductor 2 and the low-melting point oxide glass 5 and the processing conditions for viscous flow, this does not limit the process conditions. Become.

・ 3 ・ Furthermore, as wiring becomes finer, these seven-shaped grooves become a limiting factor in the number of wiring layers and yield.

The present invention is characterized in that the gaps between wiring conductors are filled by a lift-off method, and the surface is covered with a fluid insulator that is flattened by heating and flowing, and this is used as an interlayer insulating film, and its purpose is to prevent the formation of cumulative steps. The objective is to realize a completely flat multilayer wiring structure.

The present invention will be explained in detail below using examples.

FIG. 3 is an embodiment of the present invention, and is a diagram showing the manufacturing process. The steps [(a) to V)] will be explained below.

A metal layer to be a wiring conductor, for example, a molybdenum (MO) thin film 2' (wiring conductor film) is formed by sputtering on the surface of the substrate 1 (thickness = 0.5 μm). An etching mask 7 is placed on the upper surface of the thin film 2' using, for example, a resin resist (AZ 135Q) for 5 hours.
(manufactured by ip'ley) [Figure 3 (a)]
. Next, the molybdenum thin film 2' is etched using the etching mask 7 to obtain the wiring conductor 2 (FIG. 3(b)). Here, as the substrate 1, a silicon substrate or the like on which an integrated circuit including active elements is formed can be applied.

・ 4 ・ Although not clearly shown in the figure, a portion of the wiring conductor 2 is connected to the substrate 1.
Needless to say, it is connected to an active element already formed in the. Furthermore, there may be cases where another wiring layer has already been formed prior to the process according to the present invention, and the wiring layer according to the present invention is connected to this. Furthermore, the substrate 1
may be the number of wires such as ceramic four-slopes on which integrated circuit chips are mounted and which provide connections between chips.

Next, the process moves to the step of embedding non-fluid insulator 9 into void 8 of wiring conductor 2 by a lift-off method. That is,
After going through the process shown in FIG. 3(a), the etching mask 7 used for etching the molybdenum thin film and the gap 8 are removed, and a non-fluid insulator g having approximately the same thickness as the wiring conductor 2 is formed. , 9' (
Si02 + thickness: Q, 51ttn) is deposited by RF sputtering [FIG. 3(C)]. At this time, it is important to take into account the heat resistance of the etching mask 7 and appropriately set the RF power to be applied and, if necessary, the substrate heating temperature.

Next, Si deposited on the surface of the etching mask 7, 0□9
In order to remove ', the etching mask 7 is dissolved and removed using an alkaline resist stripper (J-100; manufactured by TRCL) or plasma ashing. In this way, 5i029' on the surface of the etching mask 7 is completely removed, and the void 8 between the wiring conductors is replaced with a non-flowing insulator 9 by the lift-off method.
[Figure 3(d)]. In order to effectively dissolve and remove the etching mask 7, in order to melt the insulator 5i02 attached to the side wall of the mask 7,
It is preferable to perform slide etching for 30 seconds to 60 times in a hydrofluoric acid buffer. Since 5102 attached to the side wall has a fragile structure, it can be removed by slide etching.

At the end of the lift-off method, wiring conductor 2 (MO)
A V-shaped groove 10, which is a minute gap, is formed at the contact portion between the side wall of the insulator (SIO2) and the side wall of the embedded insulator (SIO2). The depth and gap of the V-shaped groove 10 are determined by the shape of the etching mask 7, the deposition method of the non-flowable insulator 9 (S102), and the slip-off method process such as the presence or absence of slide etching. The depth ranges from about the same level as the film thickness of the wiring conductor 2 to about half of it, and the gap on the surface of the figure 7 groove ranges from about the same size as the above film thickness to the 1 film thickness. mask 7
The range is up to the sum of the film thickness.

Next, cover the surfaces of the wiring conductor 2 (MO) and the non-fluid insulator 9 (Si 02 ) in FIG. Melting point oxide glass PbO5i02 type glass (composition ratio: 5Q w
t%-5Qwt%) target by RF sputtering using a gas containing Ne as the main component as an atmospheric gas [FIG. 3(e)]. The film thickness of the fluid insulator layer (low melting point oxide glass layer) 11' varies depending on the usage of the wiring structure, but generally ranges from about the same thickness as that of the wiring conductor 2 to 4 to 5 times the film thickness. is preferred. Regarding the formation method, the well-known ion beam sputtering method, CVD method, and vacuum evaporation method can be applied to the RF sputtering method described in 1. The surface of the fluid insulating layer 11' made of the low melting point oxide glass layer obtained in this way has V-shaped grooves 10 as indicated in "1".
As a result, unevenness appears.

Next, heat treatment at 800''C for 30 minutes is performed to generate flow due to viscous flow in the fluid insulating layer 11', thereby forming irregularities on the surface reflecting the V-shaped grooves 10.
・ disappears, and the surface 12 far from the substrate becomes flat [Fig. 3 (
f)].

The interlayer insulating film composed of the fluid insulating layer (low-melting point oxide glass layer) 11 and the non-fluid insulating material 9 obtained in this way is mostly The film thickness remains constant without being affected. Thus, a completely planarized wiring layer according to the present invention is obtained.

The heat treatment conditions (heating temperature, heating time, etc.) are mainly as follows:
It is determined by the flow characteristics of the flowable insulator layer (low melting point oxide glass layer) 11', and in order to obtain the required flatness,
Needless to say, it is necessary to make modifications depending on the composition and shape of the wiring conductor 2, the size of the V-shaped groove 10, etc.

Regarding the low minimum point oxide/compound glass that can be applied to the present invention,
In addition to the above examples, PbO-5in2-based glass 7, PbO- B203-5i02 series glass,
ZnO-PbO-B203-5i02 glass, Z
The composition can be appropriately selected and applied to any of the nO-B203-PbO.8.-based glass rZn OB203-based glass.

FIG. 4 shows an example using a lift-off process different from the above example. That is, instead of the lift-off method for forming the non-flowable insulator 9 in FIG. 3, the lift-off method is used for forming the wiring conductor. A non-fluid insulating film 9' (s, to, , ) is formed on the substrate 1'2 by sputtering or CVD, and an etching mask 7' for forming line grooves is placed on the upper surface. 3(a)] is formed by the inverted button of the etching mask 7 shown in FIG. 4(a).
)]. For this etching mask 7', the same (AZ-based resin resist) as in the embodiment shown in FIG. 3 is used.

Next, the non-flowable insulator 9'' is etched using a hydrofluoric acid buffer to obtain the non-flowable insulator 9 etched with the wiring i#13. It goes without saying that the method described above can be used [Figure 4(b)].

Next, using the etching mask 7', the wiring trench 13 is filled with the wiring conductor 2 by a lift-off method. Then, the wiring conductor 2 is formed by RF sputtering, DC sputtering, or vacuum evaporation, covering the etching mask 7' and the wiring groove 13.
．． As 2', molybdenum (MO) is deposited to the same thickness as the non-fluid insulator 9 [FIG. 4(C)].

Next, in order to remove the molybdenum film (wiring conductor 2'') attached to the upper surface of the etching mask 7', the etching mask 7' is removed.
Dissolve and remove using a remover solution or plasma ashing. In this way, the second molybdenum film (wiring layer 2") on the surface of the mask 7' is completely removed, and the wiring groove 13 is completely removed.
is buried by the wiring conductor 2 (MO) [FIG. 4(d)]. In order to effectively dissolve and remove the mask 7', it is preferable to perform slide etching for about 30 seconds by reactive ion etching (R process E) in order to dissolve molybdenum attached to the side walls of the mask 7'.

Similar to the embodiment shown in FIG. 3, when lift-off is completed, a V-shaped groove 10' is formed at the contact area between the side wall of the wiring conductor 2 (MO) and the side wall of the non-flowing insulator 9 (5i02). arise.

The following steps from the formation of the low melting point oxide glass layer to the heat treatment are exactly the same as the steps (e) and (b) in FIG. 3. Through this step, a completely planarized wiring layer can be obtained by a lift-off process different from the step shown in FIG.

In the embodiments shown in FIGS. 3 and 4 above, the wiring conductor 2 is made of other metals such as gold (Au) instead of molybdenum (MO) as long as the heat treatment conditions do not cause deterioration such as melting. ), tungsten (W), platinum (pt
), titanium (Ti), aluminum (Az) and its alloys, tantalum (Ta), phosphorus-doped polycrystalline silicon, various metal silicides, etc. are easily applicable.

Furthermore, as the non-fluid insulator 9, not only 5i02 but also other insulators such as silicon nitride (Si3N4) + alumina (Az203) can be used. Here, non-fluidity means that deformation such as viscous flow does not occur under the heat treatment conditions of the fluid insulating layer described in 1.

The completely flattened interconnect described in item 1 of "1. It is clear that it does not exist.

FIG. 5 shows an example of a four-layer wiring structure as an example of a multilayer wiring structure formed using the completely planarized wiring layers shown in FIGS. 3 and 4. FIG. 5(a) shows an example in which the completely planarized wiring layer shown in FIG. 3 is used, and FIG. 5(b) shows an example in which the completely planarized wiring layer shown in FIG. 4 is used.

The structure of FIG. 5 (, 17) will be explained in detail below. FIG. 5(b) can be inferred from FIG. 5(a).

Reference numeral 1 denotes a substrate, which may be a silicon substrate in which active elements and the like are built. In this case, there may be connection of active elements, etc., but this is omitted in this embodiment. Furthermore, the substrate 1 may be a wiring board made of ceramic or the like, and in either case, another wiring layer may be provided below the wiring layer of this embodiment.

Wiring conductor (MO) 2 + non-fluid insulator (sio□) 9 filled with void 8 and low melting point oxide glass (PbO50wt% sio2) whose surface far from the substrate is flattened
The fluid insulating layer 11 made of glass (50 wt% glass) is the third
A completely planarized wiring layer shown in FIG.

A desired through hole 14 is provided in the low melting point glass layer of this first wiring layer, and this is regarded as the substrate 1 in FIG. 3(a),
With completely flattened wiring formed through the exact same process,
A second wiring layer 17 is formed. Similarly, a third wiring layer 18 is formed and provided with desired through holes 14.
An aluminum (A/) metal wiring serving as a wiring conductor 2'' is provided as a fourth layer wiring layer 19 on its two surfaces.Thus,
A four-layer wiring structure according to the present invention is formed.

In the four-layer wiring structure shown in FIG.
The wiring layer 20 caused by the step difference in the through holes of No. 4 is unavoidable. FIG. 6 shows an embodiment in which the step of the through hole is filled with a wiring conductor 15 in order to prevent the wiring depression 20.

In FIG. 6, the process up to the formation of through holes in the first wiring layer is completely the same as the embodiment shown in FIG.

Thereafter, using the etching mask used to form the through holes, the through holes are filled with wiring conductors by a lift-off method. This corresponds to (σ) to (d) in FIG. The through hole corresponds to the wiring groove 13.

In this way, interlayer wiring connector 15 is formed.

In the subsequent wiring structure, the formation of the second layer wiring layer shown in FIG. 5 and the above-mentioned interlayer wiring connector 15 are repeated. On this occasion,
The third interlayer wiring connector 15' is formed of aluminum, which is the wiring conductor of the second 4-layer wiring layer.Thus, a minute 4-layer wiring structure with wiring recesses 20' is formed. be done.

It is clear that various changes can be made to the embodiments shown in FIGS. 5 and 6 without departing from the spirit of the present invention.

For example, instead of using the low melting point glass layers with the same composition or the same heat treatment conditions, it is also possible to change the above composition or the above treatment conditions for each wiring layer.

Furthermore, some of the wiring layers in this embodiment may be formed by a conventional wiring formation method, that is, non-perfectly planarized wiring, for example, the wiring layer shown in FIG. 1 or 2, or 5i02 is used as an interlayer film. It is obvious that the wiring and wiring layers can be replaced by known wiring formation methods.

Furthermore, by using the present invention, it is possible to realize not only the above-mentioned four-layer wiring structure but also a multi-layer wiring structure with a desired number of wiring layers, and it is clear that there are basically no factors that limit the number of wiring layers. It is.

The object of the present invention can also be achieved by using other materials as the fluid insulator layer instead of the low melting point oxide glass layer. For example, a thermoplastic resin can be used and heated to generate a flow such as viscous flow, thereby flattening the surface. Examples of such resin materials include polystyrene, polyethylene, polyamide, and polysenylene sulfide.

There are polyimides, etc., and the heat treatment temperature is 200°
It can be selected depending on the material in the range of C to 400C. In addition, paraffin hydrocarbons (OnH2n+
2) can also be used as the fluid insulating layer. When a resin or paraffin is used as the fluid insulating layer, it goes without saying that aluminum (AI and its alloys) can be used as the wiring conductor in the metal pond described above.

・15・ As explained above, according to the present invention, GFP (Gla
The ability to realize completely planarized wiring using the ss Flow Planarization technology has the following advantages. That is, there is no gradual long-distance step difference caused by the density of the wiring conductors, and the flatness of the wiring layer is not affected by the shape and arrangement of the wiring conductors. Therefore, there is no need for pseudo wiring to make the flatness uniform. Moreover, because of the perfect flatness, even if the number of wiring layers is stacked, no cumulative step difference will occur, and there is no restriction on the number of wiring layers, making it possible to perform extremely multilayer wiring.

In addition, the fine 7-shaped grooves present in completely flattened wiring using the conventional lift-off method also disappear, resulting in more perfect flatness.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of a conventional surface flattening technique, Figure 2 is an explanatory diagram of a conventional surface flattening technique using a lift-off method, Figures 3 (a) to V) and Figures 4 (a) to (d). 5(a) is an explanatory diagram of the process of forming a completely flat wiring layer according to the present invention.
, (b) and FIG. 6 are all according to the present invention.
. FIG. 2 is a structural explanatory diagram showing an example of a four-layer wiring structure. 1...Substrate 2,2///...Wiring conductor 2', 2''...Wiring conductor film 3.5...Low melting point oxide glass 4...Long distance step 6,10. 10'...
7-shaped groove 7.7'...Egraving mask 8...Gap 9
, 9', 9"... Non-flowable insulator 11.11'...
・Fluid insulator layer 12...Face far from the substrate 13...Wiring Ha 7#14...Through hole 15.
15'... Interlayer wiring connector 16... First layer wiring layer 17... Second layer wiring layer 1
8... Third wiring layer 19... Fourth wiring layer 20
．． 20'... Wiring recess patent applicant Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Public Corporation

Claims (2)

[Claims] (1) Method for manufacturing a wiring structure including the following steps: ■ Step of forming a wiring conductor film on a substrate. @ A step of forming an etching mask using a resist on the wiring conductor film. θ A step of etching the wiring conductor film using an etching mask to form a wiring conductor. ■ Depositing a non-flowing insulator on the surface of the etching mask on the wiring conductors and in the gaps between the wiring conductors. ■ Lift-off process to remove the etch mask and the non-flowing insulator deposited on its surface. θ A process of forming a fluid insulator layer to cover the entire surface of the wiring conductor and the non-fluid insulator embedded in the gap between them. (2) A step of flattening the fluid insulating layer by heating the substrate that has undergone the above steps. (2) A method for manufacturing a wiring HT structure including the following steps. ■ A process of forming a non-fluid insulating film on the substrate. @ Step of forming an etching mask on the non-flowable insulator 1 using a resist. Step 1: Forming wiring grooves in the non-fluid insulating film using a θ etching mask. ■ Non-flowing insulator film" Step of depositing wiring conductors on the surface of the second etching mask and in the wiring grooves. ■ Lift-off process to remove wiring conductors deposited on the etching mask and its surface. θ A process of forming a fluid insulating layer so as to cover the entire surface of the non-fluid insulating film and the wiring conductor embedded in the wiring groove in the gap between the non-fluid insulating film. (2) A step of heating the substrate that has undergone the above steps to planarize the fluid insulating layer described in (1) above.