JPS5821844A - Manufacture of wiring structure - Google Patents
Manufacture of wiring structureInfo
- Publication number
- JPS5821844A JPS5821844A JP11921681A JP11921681A JPS5821844A JP S5821844 A JPS5821844 A JP S5821844A JP 11921681 A JP11921681 A JP 11921681A JP 11921681 A JP11921681 A JP 11921681A JP S5821844 A JPS5821844 A JP S5821844A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulator
- layer
- etching mask
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000012212 insulator Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 239000012530 fluid Substances 0.000 claims description 28
- 230000009969 flowable effect Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 73
- 239000011229 interlayer Substances 0.000 abstract description 9
- 238000002844 melting Methods 0.000 description 17
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 16
- 239000010408 film Substances 0.000 description 16
- 229910052750 molybdenum Inorganic materials 0.000 description 16
- 239000011733 molybdenum Substances 0.000 description 16
- 230000008018 melting Effects 0.000 description 15
- 239000000075 oxide glass Substances 0.000 description 14
- 239000011521 glass Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000001552 radio frequency sputter deposition Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012188 paraffin wax Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の配線構造体の製造方法に関するも
ので、さらに詳しくは、配線層数に制限のないように各
配線層の表面を平坦にした多層配線用の配線構造体の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a wiring structure for a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a wiring structure for a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a wiring structure for a semiconductor device, and more specifically, it relates to a method for manufacturing a wiring structure for a semiconductor device. The present invention relates to a method for manufacturing a structure.
多層配線技術においては、配線層数が増大するにつれて
配線導体や層間絶縁膜のスルーホールによって生ずる段
差を緩和する平坦化技術が不可欠である。各種の平坦化
技術が提案されており、例えば、低融点酸化物ガラスの
粘性流動を用いた表面平坦化技術(GFP; Glas
s Flow Planarization)がある。In multilayer wiring technology, as the number of wiring layers increases, a planarization technology that alleviates steps caused by through holes in wiring conductors and interlayer insulating films is essential. Various flattening technologies have been proposed, such as surface flattening technology (GFP; Glas
s Flow Planarization).
しかし、従来のGFP技術においては、例えば特願昭5
6−57939号「半導体集積回路装置」に記載されて
いる如き平坦化技術においては、良好な平坦性が達成さ
れており、急激な段差は存在しないものの、ゆるやかな
遠距離段差は依然として存在する。However, in the conventional GFP technology, for example,
In the planarization technique as described in No. 6-57939 "Semiconductor Integrated Circuit Device", good flatness is achieved and there are no sharp steps, but gradual long-distance steps still exist.
即ち、第1図は」1記の平坦化技術の概要を示す図であ
り、■は基板、2は配線導体、3はpbo −8i02
系の低融点酸化物ガラスであり、加熱により粘性流動を
生ぜしめた後の断面プロファイルである。4は配線導体
の疎密によって生ずるガラス而の遠距離段差である。こ
の遠距離段差4の極大値は、配線導体の最密領域と配線
導体の存在しない領域との間の段差に相当する。このよ
うな遠距離段差は、配線層を積層するにつれて、また、
配線導体厚を厚くするにつれて、累積段差を増大せしめ
、積層可能な配線層数を制約している。That is, FIG. 1 is a diagram showing an outline of the flattening technology described in 1. 2 is a substrate, 2 is a wiring conductor, and 3 is a pbo-8i02
This is a low melting point oxide glass of the system, and this is a cross-sectional profile after it has been heated to produce viscous flow. 4 is a long-distance level difference in glass caused by the density of the wiring conductor. The maximum value of this long-distance step 4 corresponds to the step between the densest region of wiring conductors and the region where no wiring conductors are present. Such long-distance steps occur as wiring layers are stacked, and
As the thickness of the wiring conductor increases, the cumulative level difference increases, which limits the number of wiring layers that can be stacked.
また、他の平坦化技術、例えば特願昭56−55637
号「配線構造体の形成方法」に記載されている如き低融
点酸化物ガラスのリフトオフ法による平J1>化技11
i1においては、はゾ好ましい平坦性が得られているも
のの、依然として微ンnlな段差(7字溝)が残存して
いる。即ち、第2図は」−記平坦化技術の概要を示す図
であり、1は基板、2は配線導体。In addition, other flattening techniques, such as Japanese Patent Application No. 56-55637
11 by the lift-off method of low melting point oxide glass as described in No. ``Method for Forming Wiring Structure''
In i1, although very desirable flatness was obtained, a slight step (7-shaped groove) still remained. That is, FIG. 2 is a diagram showing an outline of the planarization technique described above, in which 1 is a substrate and 2 is a wiring conductor.
5はPbO−8i 02系の低融点酸化物カラスであり
、加熱により粘性流動を生ぜしめた後の断面プロファイ
ルである。6は7字溝であり、配線導体2と低融点酸化
物ガラス5との親和性によって決まる。5 is a low melting point oxide glass based on PbO-8i 02, and its cross-sectional profile is shown after it has been heated to produce viscous flow. 6 is a 7-shaped groove, which is determined by the affinity between the wiring conductor 2 and the low melting point oxide glass 5.
このような7字溝は、配線導体2と低融点酸化物ガラス
5の組成や粘性流動の処理条件を適切に選択することに
よって、著しく削減しつるものの、このことはプロセス
条件を制約することになる。Although such figure-7 grooves can be significantly reduced by appropriately selecting the composition of the wiring conductor 2 and the low-melting point oxide glass 5 and the processing conditions for viscous flow, this does not limit the process conditions. Become.
・ 3 ・
さらに、配線の微細化につれて、このような7字溝は配
線層数や歩留まりの制限要因となる。・ 3 ・ Furthermore, as wiring becomes finer, these seven-shaped grooves become a limiting factor in the number of wiring layers and yield.
本発明は、配線導体間の空隙をリフトオフ法によって埋
めこみ、表面を加熱流動により平坦化した流動性絶縁体
で覆い、これを層間絶縁膜とすることを特徴とし、その
目的は累積段差を生じない完全に平坦なる多層配線構造
体を実現するにある。The present invention is characterized in that the gaps between wiring conductors are filled by a lift-off method, and the surface is covered with a fluid insulator that is flattened by heating and flowing, and this is used as an interlayer insulating film, and its purpose is to prevent the formation of cumulative steps. The objective is to realize a completely flat multilayer wiring structure.
以下本発明を実施例によって詳細に説明する。The present invention will be explained in detail below using examples.
第3図は本発明の実施例であって、製造工程を示す図で
ある。以下工程〔(a)〜V))に従がって説明する。FIG. 3 is an embodiment of the present invention, and is a diagram showing the manufacturing process. The steps [(a) to V)] will be explained below.
基板1の表面に配線導体となるべき金属層、例えばモリ
ブデン(MO)薄膜2′(配線用導体膜)をスパッタ法
によって形成しく厚さ=0.5μm)、配線導体2を形
成するためにモリブデン薄膜2′の上面に食刻用マスク
7を、例えば樹脂系レジスト(AZ 135Qに 5h
ip’ley社製)を用いて形成する〔第3図(a)〕
。つぎに、この食刻用マスク7を用いてモリブデン薄膜
2′を食刻し、配線導体2を得る〔第3図(b)〕。こ
こで、基板1には、能動素子を含む集積回路が形成され
るシリコン基板等が適用できる。A metal layer to be a wiring conductor, for example, a molybdenum (MO) thin film 2' (wiring conductor film) is formed by sputtering on the surface of the substrate 1 (thickness = 0.5 μm). An etching mask 7 is placed on the upper surface of the thin film 2' using, for example, a resin resist (AZ 135Q) for 5 hours.
(manufactured by ip'ley) [Figure 3 (a)]
. Next, the molybdenum thin film 2' is etched using the etching mask 7 to obtain the wiring conductor 2 (FIG. 3(b)). Here, as the substrate 1, a silicon substrate or the like on which an integrated circuit including active elements is formed can be applied.
・ 4 ・
図には明示されていないが、配線導体2の1部は基板1
に既に形成されている能動素子に接続されることはいう
までもない。また、本発明による工程に先き立って、既
に別の配線層が形成されており、これに本発明による配
線層が接続される場合もありうる。またさらに、基板1
は集積回路チップを搭載し、チップ間の接続に供するセ
ラミック4坂などの配線数であってもよい。・ 4 ・ Although not clearly shown in the figure, a portion of the wiring conductor 2 is connected to the substrate 1.
Needless to say, it is connected to an active element already formed in the. Furthermore, there may be cases where another wiring layer has already been formed prior to the process according to the present invention, and the wiring layer according to the present invention is connected to this. Furthermore, the substrate 1
may be the number of wires such as ceramic four-slopes on which integrated circuit chips are mounted and which provide connections between chips.
さて、つぎに、リフトオフ法によって、配線導体2の空
隙8に非流動性絶縁体9を埋め込む工程に移る。即ち、
第3図(a)の工程を経たのち、モリブデン薄膜の食刻
に用いた食刻用マスク7と空隙8とをイ夏って、配線導
体2とほぼ同じ膜厚の非流動性絶縁体g 、 9’ (
Si02 +厚さ:Q、51ttn)をRF スパッタ
法によって堆積する〔第3図(C)〕。このとき、食刻
用マスク7の耐熱性を考慮して、投入すべきRFパワー
および必要な場合には基板加熱温度を適切に設定するこ
とが肝要である。Next, the process moves to the step of embedding non-fluid insulator 9 into void 8 of wiring conductor 2 by a lift-off method. That is,
After going through the process shown in FIG. 3(a), the etching mask 7 used for etching the molybdenum thin film and the gap 8 are removed, and a non-fluid insulator g having approximately the same thickness as the wiring conductor 2 is formed. , 9' (
Si02 + thickness: Q, 51ttn) is deposited by RF sputtering [FIG. 3(C)]. At this time, it is important to take into account the heat resistance of the etching mask 7 and appropriately set the RF power to be applied and, if necessary, the substrate heating temperature.
つぎに、食刻用マスク7の表面に堆積したSi、0□9
′を除去するために、食刻用マスク7をアルカリ系のレ
ジストはく離液(J−100; TRCL社製)あるい
はプラズマ灰化により溶解除去する。かくて、食刻用マ
スク7の表面上の5i029’は完全に除去され、リフ
トオフ法により配線導体間の空隙8は非流動性絶縁体9
によって埋め込まれたことになる〔第3図(d)〕。食
刻用マスク7の溶解除去を効果的に行なうために、マス
ク7の側壁部に付着せる絶縁体5i02を溶解すべく、
弗酸緩衝液にて30秒ないし60抄スライドエツチを行
なうことが好ましい。側壁部に付着せる5102は脆弱
構造であるため、スライドエッチによって除去できる。Next, Si deposited on the surface of the etching mask 7, 0□9
In order to remove ', the etching mask 7 is dissolved and removed using an alkaline resist stripper (J-100; manufactured by TRCL) or plasma ashing. In this way, 5i029' on the surface of the etching mask 7 is completely removed, and the void 8 between the wiring conductors is replaced with a non-flowing insulator 9 by the lift-off method.
[Figure 3(d)]. In order to effectively dissolve and remove the etching mask 7, in order to melt the insulator 5i02 attached to the side wall of the mask 7,
It is preferable to perform slide etching for 30 seconds to 60 times in a hydrofluoric acid buffer. Since 5102 attached to the side wall has a fragile structure, it can be removed by slide etching.
リフトオフ法が終了した時点では、配線導体2(MO)
の側壁部と埋め込まれた絶縁体(sio2)の側壁部の
接触部に微細な間隙であるV字溝10が生ずる。V字溝
10の深さ・間隙は、食刻用マスク7の形状、非流動性
絶縁体9(S102)の堆積手法、スライドエッチの有
無などのりフトオフ法のプロセスによって決まり、概ね
v字溝10の深さは配線導体2の膜厚と同程度から約そ
の半分程度の範囲にあり、7字溝の表面での間隙は上記
膜厚と同程度の大きさから」1記膜厚に食刻用マスク7
の膜厚を加えた大きさまでの範囲にある。At the end of the lift-off method, wiring conductor 2 (MO)
A V-shaped groove 10, which is a minute gap, is formed at the contact portion between the side wall of the insulator (SIO2) and the side wall of the embedded insulator (SIO2). The depth and gap of the V-shaped groove 10 are determined by the shape of the etching mask 7, the deposition method of the non-flowable insulator 9 (S102), and the slip-off method process such as the presence or absence of slide etching. The depth ranges from about the same level as the film thickness of the wiring conductor 2 to about half of it, and the gap on the surface of the figure 7 groove ranges from about the same size as the above film thickness to the 1 film thickness. mask 7
The range is up to the sum of the film thickness.
つぎCと、第3図(d)の配線導体2 (MO)と非流
動性絶縁体9 (Si 02 )との表面を覆って、流
動性絶縁体層月′(厚さ二05μm)として低融点酸化
物ガラスPbO5i02系ガラス(組成比: 5Q w
t%−5Qwt%)ターゲットを用いてRFスパッタ法
にて雰囲気ガスとしてNeを主成分とするガスを使用し
て形成する〔第3図(e)〕。流動性絶縁体層(低融点
酸化物ガラス層)11′の膜厚は、配線構造体の使用口
的によって異なるが、概ね配線導体2の;膜厚と同程度
から4〜5倍までの範囲が好ましい。また、形成法につ
いては、」1記のRFスパッタ法の池に、公知のイオン
ビームスパッタ法、 CVD法、真空蒸着法が適用で
きる。こうして得られた低融点酸化物ガラス層からなる
流動性絶縁体層11′の表面には、」1記のV字溝10
を反映して凹凸が出現する。Next, cover the surfaces of the wiring conductor 2 (MO) and the non-fluid insulator 9 (Si 02 ) in FIG. Melting point oxide glass PbO5i02 type glass (composition ratio: 5Q w
t%-5Qwt%) target by RF sputtering using a gas containing Ne as the main component as an atmospheric gas [FIG. 3(e)]. The film thickness of the fluid insulator layer (low melting point oxide glass layer) 11' varies depending on the usage of the wiring structure, but generally ranges from about the same thickness as that of the wiring conductor 2 to 4 to 5 times the film thickness. is preferred. Regarding the formation method, the well-known ion beam sputtering method, CVD method, and vacuum evaporation method can be applied to the RF sputtering method described in 1. The surface of the fluid insulating layer 11' made of the low melting point oxide glass layer obtained in this way has V-shaped grooves 10 as indicated in "1".
As a result, unevenness appears.
つぎに、800′’C,30分の加熱処理によって、流
動性絶縁体層11′に粘性流動による流動を生せしめる
ことにより、V字溝10を反映した表向の凹凸・ 7
・
は消失し、基板より遠い面12は平坦化する〔第3図(
f)〕。Next, heat treatment at 800''C for 30 minutes is performed to generate flow due to viscous flow in the fluid insulating layer 11', thereby forming irregularities on the surface reflecting the V-shaped grooves 10.
・ disappears, and the surface 12 far from the substrate becomes flat [Fig. 3 (
f)].
このようにして得られた流動性絶縁体層(低融点酸化物
ガラス層)11と非流動性絶縁体9とよりなる層間絶縁
膜は、配線導体2の形状、膜厚、疎密によって殆んど影
響されることなく一定膜厚となる。かくて、本発明によ
る完全平坦化配線層が得られる。The interlayer insulating film composed of the fluid insulating layer (low-melting point oxide glass layer) 11 and the non-fluid insulating material 9 obtained in this way is mostly The film thickness remains constant without being affected. Thus, a completely planarized wiring layer according to the present invention is obtained.
加熱処理条件(加熱温度、加熱時間等)は、主として、
流動性絶縁体層(低融点酸化物ガラス層)11′の流動
特性によって決まり、必要とする平坦度を得るために、
配線導体2の組成・形状、v字溝10の大きさ等に応じ
て修正する必要があることは云うまでもない。The heat treatment conditions (heating temperature, heating time, etc.) are mainly as follows:
It is determined by the flow characteristics of the flowable insulator layer (low melting point oxide glass layer) 11', and in order to obtain the required flatness,
Needless to say, it is necessary to make modifications depending on the composition and shape of the wiring conductor 2, the size of the V-shaped groove 10, etc.
本発明に適用しうる低最点酸・化物ガラスについては、
上記実施例の他に、概ね500°C〜1000°Cの範
囲の所望の加熱処理温度および概ね10分から60分の
範囲の所望の加熱時間に応じて、PbO−5in2系ガ
ラ7、 、 PbO−B203−5i02系ガラス、
ZnO−PbO−B203−5i02系ガラス、 Z
nO−B203− PbO・ 8 ・
系ガラスr Zn OB203系ガラスのいずれについ
ても、組成を適切に選択し適用できる。Regarding the low minimum point oxide/compound glass that can be applied to the present invention,
In addition to the above examples, PbO-5in2-based glass 7, PbO- B203-5i02 series glass,
ZnO-PbO-B203-5i02 glass, Z
The composition can be appropriately selected and applied to any of the nO-B203-PbO.8.-based glass rZn OB203-based glass.
上記実施例と異なるリフトオフプロセスを用いた実施例
を第4図に示す。即ち、第3図における非流動性絶縁体
9を形成するリフトオフ法の代りに、配線導体を形成す
るためにリフトオフ法を用いる。基板1」二に非流動性
絶縁体の膜9’ (s、to、、 )をスパッタ法ある
いはCVD法により形成し、その上面に配、線溝形成の
ための食刻用マスク7′〔第3図(a)に示す食刻用マ
スク7の反転バタンよりなる〕を形成する〔第4図(a
)〕。この食刻用マスク7′には、第3図の実施例と同
じ(AZ系の樹脂系レジストを用いる。FIG. 4 shows an example using a lift-off process different from the above example. That is, instead of the lift-off method for forming the non-flowable insulator 9 in FIG. 3, the lift-off method is used for forming the wiring conductor. A non-fluid insulating film 9' (s, to, , ) is formed on the substrate 1'2 by sputtering or CVD, and an etching mask 7' for forming line grooves is placed on the upper surface. 3(a)] is formed by the inverted button of the etching mask 7 shown in FIG. 4(a).
)]. For this etching mask 7', the same (AZ-based resin resist) as in the embodiment shown in FIG. 3 is used.
つぎに、非流動性絶縁体9″を弗酸緩衝液を用いて食刻
し、配線i#13と食刻された非流動性絶縁体9を得る
。食刻法については、プラズマエツチング等地の手法を
用いうることは云゛うまでもない〔第4図(b)〕。Next, the non-flowable insulator 9'' is etched using a hydrofluoric acid buffer to obtain the non-flowable insulator 9 etched with the wiring i#13. It goes without saying that the method described above can be used [Figure 4(b)].
つぎに、食刻用マスク7′を利用して、リフトオフ法に
より配線溝13を配線導体2で埋め込む。っまり、食刻
用マスク7′と配線溝13を覆って、RFスパッタ法あ
るいはDCスパッタ法、真空蒸着法により配線用導体2
.2’としてモリブデン(MO)を非流動性絶縁体9と
はゾ同じ膜厚で堆積する〔第4図(C)〕。Next, using the etching mask 7', the wiring trench 13 is filled with the wiring conductor 2 by a lift-off method. Then, the wiring conductor 2 is formed by RF sputtering, DC sputtering, or vacuum evaporation, covering the etching mask 7' and the wiring groove 13.
.. As 2', molybdenum (MO) is deposited to the same thickness as the non-fluid insulator 9 [FIG. 4(C)].
つぎに、食刻用マスク7′の上面に付着せるモリブデン
膜(配線用導体2“)を除去すべく、食刻用マスク7′
ヲレシストはく離液またはプラズマ灰化を用いて溶解除
去する。かくて、マスク7′の表面」二のモリブデン膜
(配線用尋体膜2“)は完全に除1去され、配線溝13
は配線導体2(MO)によって埋め込まれたことになる
〔第4図(d)〕。マスク7′の溶解除去を効果的に行
なうために、マスク7′の側壁に付着せるモリブデンを
溶解すべく、反応性イオンエツチング(R工E)によっ
て30秒程度スライドエッチを行なうことが好ましい。Next, in order to remove the molybdenum film (wiring conductor 2'') attached to the upper surface of the etching mask 7', the etching mask 7' is removed.
Dissolve and remove using a remover solution or plasma ashing. In this way, the second molybdenum film (wiring layer 2") on the surface of the mask 7' is completely removed, and the wiring groove 13 is completely removed.
is buried by the wiring conductor 2 (MO) [FIG. 4(d)]. In order to effectively dissolve and remove the mask 7', it is preferable to perform slide etching for about 30 seconds by reactive ion etching (R process E) in order to dissolve molybdenum attached to the side walls of the mask 7'.
第3図に示す実施例と同様に、リフトオフが終了した時
点では、配線導体2 (MO)の側壁部と非流動性絶縁
体9 (5i02)の側壁部の接触部にv字溝10′が
生ずる。Similar to the embodiment shown in FIG. 3, when lift-off is completed, a V-shaped groove 10' is formed at the contact area between the side wall of the wiring conductor 2 (MO) and the side wall of the non-flowing insulator 9 (5i02). arise.
以下の低融点酸化物ガラス層の形成から加熱処理の工程
は第3図の(e)、び)の工程と全く同じである。この
工程を経ることにより、第3図の工程と異なるリフトオ
フプロセスによる完全平坦化配線層が得られる。The following steps from the formation of the low melting point oxide glass layer to the heat treatment are exactly the same as the steps (e) and (b) in FIG. 3. Through this step, a completely planarized wiring layer can be obtained by a lift-off process different from the step shown in FIG.
上記の第3図、第4図に示す実施例において、配線導体
2には、加熱処理条件において溶解などの変質をもたら
さない限り、モリブデン(MO)金属に代えて、他の金
属例えば金(Au)、タングステン(W)、白金(pt
)、チタン(Ti)、アルミニウム(Az)およびその
合金、タンタル(Ta)、 リンドープ多結晶シリコン
、各種メタルシリサイド等が適用しうろことは容易に理
解できる。In the embodiments shown in FIGS. 3 and 4 above, the wiring conductor 2 is made of other metals such as gold (Au) instead of molybdenum (MO) as long as the heat treatment conditions do not cause deterioration such as melting. ), tungsten (W), platinum (pt
), titanium (Ti), aluminum (Az) and its alloys, tantalum (Ta), phosphorus-doped polycrystalline silicon, various metal silicides, etc. are easily applicable.
また、非流動性絶縁体9としては5i02のみでなく他
の絶縁体、例えば窒化シリコン(Si3N4 ) +ア
ルミナ(Az203)等が使用できる。ここで、非流動
性とは、」1記流動性絶縁体層の加熱処理条件において
、粘性流動等の変形を生じないことを意味する。Furthermore, as the non-fluid insulator 9, not only 5i02 but also other insulators such as silicon nitride (Si3N4) + alumina (Az203) can be used. Here, non-fluidity means that deformation such as viscous flow does not occur under the heat treatment conditions of the fluid insulating layer described in 1.
かくて得られた」1記の完全平坦化配線においては、従
来のGFP技術にあった緩やかな遠距離段差・ 11・
4(第1図)や微細なV字購6(第2図)が存在しない
ことは明白である。The completely flattened interconnect described in item 1 of "1. It is clear that it does not exist.
第3図、第4図に示す完全平坦化配線層を用いて形成し
た多層配線構造体の実施例として、4層配線構造体の実
施例を第5図に示す。第5図(a)は第3図の完全平坦
化配線層を、第5図(b)は第4図の完全平坦化配線層
をそれぞれ用いた実施例である。FIG. 5 shows an example of a four-layer wiring structure as an example of a multilayer wiring structure formed using the completely planarized wiring layers shown in FIGS. 3 and 4. FIG. 5(a) shows an example in which the completely planarized wiring layer shown in FIG. 3 is used, and FIG. 5(b) shows an example in which the completely planarized wiring layer shown in FIG. 4 is used.
以下第5図(,17)の構造を詳細に説明する。第5図
(b)は第5図(a)より類推できる。The structure of FIG. 5 (, 17) will be explained in detail below. FIG. 5(b) can be inferred from FIG. 5(a).
1は基板であり、能動素子等が作り込まれているシリコ
ン基板であってもよい。この場合、能動素子等の接続が
あり得るが、本実施例では省略されている。またさらに
、基板1はセラミック等の配線板であってもよく、いず
れの場合も、本実施例の配線層の下層に他の配線層があ
ってもよい。Reference numeral 1 denotes a substrate, which may be a silicon substrate in which active elements and the like are built. In this case, there may be connection of active elements, etc., but this is omitted in this embodiment. Furthermore, the substrate 1 may be a wiring board made of ceramic or the like, and in either case, another wiring layer may be provided below the wiring layer of this embodiment.
配線導体(MO) 2 +空隙8を埋め込んだ非流動性
絶縁体(sio□)9および基板より遠い面を平坦化し
た低融点酸化物ガラス(PbO50wt% sio2
50wt%ガラス)からなる流動性絶縁体層11は第3
図V)で示・12 ・
した完全平坦化配線層であり、第1層配線層]6を形成
する。Wiring conductor (MO) 2 + non-fluid insulator (sio□) 9 filled with void 8 and low melting point oxide glass (PbO50wt% sio2) whose surface far from the substrate is flattened
The fluid insulating layer 11 made of glass (50 wt% glass) is the third
A completely planarized wiring layer shown in FIG.
この第1層配線層の低融点ガラス層に所望のスルーホー
ル14を設け、これを第3図(a)の基板1とみなし、
全く同じ工程を経て形成された完全平坦化配線により、
第2層配線層17が形成される。同様にして、第3層配
線層18か形成され、所望のスルーホール14を備え、
その」二面に第4層配線層19として配線導体2″′な
るアルミニウム(A/)金属配線を具備する。かくて、
本発明による4層配線構造体が形成される。A desired through hole 14 is provided in the low melting point glass layer of this first wiring layer, and this is regarded as the substrate 1 in FIG. 3(a),
With completely flattened wiring formed through the exact same process,
A second wiring layer 17 is formed. Similarly, a third wiring layer 18 is formed and provided with desired through holes 14.
An aluminum (A/) metal wiring serving as a wiring conductor 2'' is provided as a fourth layer wiring layer 19 on its two surfaces.Thus,
A four-layer wiring structure according to the present invention is formed.
第5図に示す4層配線構造においては、スルーホール1
4のスルーホール段差によって生ずる配線層み20が避
けられない。この配線窪み20を防ぐために、スルーホ
ール段差を配線導体15で埋め込んだ実施例を第6図に
示す。In the four-layer wiring structure shown in FIG.
The wiring layer 20 caused by the step difference in the through holes of No. 4 is unavoidable. FIG. 6 shows an embodiment in which the step of the through hole is filled with a wiring conductor 15 in order to prevent the wiring depression 20.
第6図において、第1層配線層のスルーホール形成まで
は、第5図の実施例と全く同じである。In FIG. 6, the process up to the formation of through holes in the first wiring layer is completely the same as the embodiment shown in FIG.
このあと、スルーホール形成に用いた食刻用マスクを用
いて、リフトオフ法により配線導体でスル−ホールを埋
め込む。これは、第4図の(σ)から(d)に相当する
。スルーホールが配線溝13に対応する。Thereafter, using the etching mask used to form the through holes, the through holes are filled with wiring conductors by a lift-off method. This corresponds to (σ) to (d) in FIG. The through hole corresponds to the wiring groove 13.
こうして、層間配線接続子15が形成される。In this way, interlayer wiring connector 15 is formed.
このあとの配線構造は、第5図の第2層配線層と上記の
層間配線接続子15の形成がくりかえされる。この際、
第3番目の層間配線接続子15′は第2″′
4層配線層の配線導体であるアルミニウムによっ八
て形成される。かくて、配線窪み20′の微小なる4層
配線構造体が形成される。In the subsequent wiring structure, the formation of the second layer wiring layer shown in FIG. 5 and the above-mentioned interlayer wiring connector 15 are repeated. On this occasion,
The third interlayer wiring connector 15' is formed of aluminum, which is the wiring conductor of the second 4-layer wiring layer.Thus, a minute 4-layer wiring structure with wiring recesses 20' is formed. be done.
上記第5図、第6図の実施例において、本発明の主旨を
逸脱しない範囲で種々の変更を加えうることは明らかで
ある。It is clear that various changes can be made to the embodiments shown in FIGS. 5 and 6 without departing from the spirit of the present invention.
例えば、同一組成の低融点ガラス層あるいは同一の加熱
処理条件に代えて、各配線層毎に上記組成あるいは上記
処理条件を変更することも可能である。For example, instead of using the low melting point glass layers with the same composition or the same heat treatment conditions, it is also possible to change the above composition or the above treatment conditions for each wiring layer.
またさらに、本実施例の各配線層の幾つかを、従来の配
線形成法による配線層即ち非完全平坦化配線、例えば第
1図あるいは第2図に示す配線層、あるいは5i02を
層間膜とする公知の配線形成法による配、線層と置き換
えうろことは明白である。Furthermore, some of the wiring layers in this embodiment may be formed by a conventional wiring formation method, that is, non-perfectly planarized wiring, for example, the wiring layer shown in FIG. 1 or 2, or 5i02 is used as an interlayer film. It is obvious that the wiring and wiring layers can be replaced by known wiring formation methods.
またさらに、本発明を用いることにより、上記4層配線
構造体にとどまらず、所望の配線層数の多層配線構造体
が実現でき、基本的に配線層数を制限する要因は存在し
ないことは明らかである。Furthermore, by using the present invention, it is possible to realize not only the above-mentioned four-layer wiring structure but also a multi-layer wiring structure with a desired number of wiring layers, and it is clear that there are basically no factors that limit the number of wiring layers. It is.
流動性絶縁体層として、低融点酸化物ガラス層の代りに
、他の材質を用いることによっても本発明の目的を実現
できる。例えば、熱可塑性の樹脂を用い、これを加熱し
、粘性流動等の流動を生ぜしめ、表面を平坦化すること
ができる。このような樹脂の材質としては、ポリスチレ
ン、ポリエチレン、ポリアミド、ポリセニレンサアルフ
ァイド。The object of the present invention can also be achieved by using other materials as the fluid insulator layer instead of the low melting point oxide glass layer. For example, a thermoplastic resin can be used and heated to generate a flow such as viscous flow, thereby flattening the surface. Examples of such resin materials include polystyrene, polyethylene, polyamide, and polysenylene sulfide.
ポリイミドなどかあり、加熱処理温度としては200°
C〜400℃の範囲で、材質に応じて選択できる。サラ
に、パラフィン類のパラフィン炭化水素(OnH2n+
2)を上記流動性絶縁層として用いることもできる。流
動性絶縁層として樹脂あるいはパラフィン類を用いた場
合には、配線導体として上記記載の金属の池にアルミニ
ウム(AIりおよびその合金などが利用できることはい
うまでもない。There are polyimides, etc., and the heat treatment temperature is 200°
It can be selected depending on the material in the range of C to 400C. In addition, paraffin hydrocarbons (OnH2n+
2) can also be used as the fluid insulating layer. When a resin or paraffin is used as the fluid insulating layer, it goes without saying that aluminum (AI and its alloys) can be used as the wiring conductor in the metal pond described above.
・ 15 ・
以上説明したように、本発明によれば、GFP(Gla
ss Flow Planarization)技術に
より、完全平坦化配線が実現できることにより、以下の
ような利点がある。即ち、配線導体の疎密によって生ず
る緩やかな遠距離段差も生じることなく、配線層の平坦
性は配線導体の形状・配置によって影響をうけない。従
がって、平坦性を一様にするための擬似配線を必要とし
ない。また、完全平坦性なるか故に、配線層数を積み重
ねても、累積段差を生じることなく、配線層数に制約が
なく、超多層配線が可能である。・15・ As explained above, according to the present invention, GFP (Gla
The ability to realize completely planarized wiring using the ss Flow Planarization technology has the following advantages. That is, there is no gradual long-distance step difference caused by the density of the wiring conductors, and the flatness of the wiring layer is not affected by the shape and arrangement of the wiring conductors. Therefore, there is no need for pseudo wiring to make the flatness uniform. Moreover, because of the perfect flatness, even if the number of wiring layers is stacked, no cumulative step difference will occur, and there is no restriction on the number of wiring layers, making it possible to perform extremely multilayer wiring.
また、従来のリフトオフ法による完全平坦化配線にあっ
た微細な7字溝も消失し、より完全な平坦性が得られる
。In addition, the fine 7-shaped grooves present in completely flattened wiring using the conventional lift-off method also disappear, resulting in more perfect flatness.
第1図は従来の表面平坦化技術の説明図、第2図は従来
のリフトオフ法による表面平坦化技術の説明図、第3図
(a)〜V)及び第4図(a)〜(d)はそれぞれ本発
明による完全平坦配線層の形成工程説明図第5図(a)
、(b)及び第6図はいずれも本発明による・16・
。
4層配線構造体の実施例を示す構造説明図である。
1・・・基板 2,2///・・・配線導
体2′、2“・・・配線用導体膜
3.5・・・低融点酸化物ガラス
4・・・遠距離段差 6 、10.10’・・・
7字溝7.7′・・・食刻用マスク 8・・・空隙9
、9’、 9“・・・非流動性絶縁体11.11’・・
・流動性絶縁体層
12・・・基板より遠い面
13・・・配Ha 7#14・・・スルーホール15.
15’・・・層間配線接続子
16・・・第1層配線層 17・・・第2層配線層1
8・・・第3層配線層 19・・・第4層配線層20
.20’・・・配線窪み
特許出願人 日本電信電話公社
代理人弁理士 中村純之助Figure 1 is an explanatory diagram of a conventional surface flattening technique, Figure 2 is an explanatory diagram of a conventional surface flattening technique using a lift-off method, Figures 3 (a) to V) and Figures 4 (a) to (d). 5(a) is an explanatory diagram of the process of forming a completely flat wiring layer according to the present invention.
, (b) and FIG. 6 are all according to the present invention.
. FIG. 2 is a structural explanatory diagram showing an example of a four-layer wiring structure. 1...Substrate 2,2///...Wiring conductor 2', 2''...Wiring conductor film 3.5...Low melting point oxide glass 4...Long distance step 6,10. 10'...
7-shaped groove 7.7'...Egraving mask 8...Gap 9
, 9', 9"... Non-flowable insulator 11.11'...
・Fluid insulator layer 12...Face far from the substrate 13...Wiring Ha 7#14...Through hole 15.
15'... Interlayer wiring connector 16... First layer wiring layer 17... Second layer wiring layer 1
8... Third wiring layer 19... Fourth wiring layer 20
.. 20'... Wiring recess patent applicant Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Public Corporation
Claims (2)
を形成する工程。 θ 食刻用マスクを用い上記配線用導体膜をエツチング
して配線導体を形成する工程。 ■ 配線導体上の食刻用マスクの表面及び配線導体間空
隙に非流動性絶縁体を堆積する工程。 ■ 食刻用マスク及びその表面上に堆積した非流動性絶
縁体を除去するリフトオフ工程。 θ 配線導体とその間隙に埋め込まれた非流動性絶縁体
の表面全体を覆うように流動性絶縁体層を形成する工程
。 ■ 上記工程を経た基板を加熱し上記流動性絶縁体層の
平坦化を行なう工程。(1) Method for manufacturing a wiring structure including the following steps: ■ Step of forming a wiring conductor film on a substrate. @ A step of forming an etching mask using a resist on the wiring conductor film. θ A step of etching the wiring conductor film using an etching mask to form a wiring conductor. ■ Depositing a non-flowing insulator on the surface of the etching mask on the wiring conductors and in the gaps between the wiring conductors. ■ Lift-off process to remove the etch mask and the non-flowing insulator deposited on its surface. θ A process of forming a fluid insulator layer to cover the entire surface of the wiring conductor and the non-fluid insulator embedded in the gap between them. (2) A step of flattening the fluid insulating layer by heating the substrate that has undergone the above steps.
法。 ■ 基板」二に非流動性絶縁体膜を形成する工程。 @ 該非流動性絶縁体1摸上にレジストを用いて食刻用
マスクを形成する工程。 θ 食刻用マスクを用い」1記非流動性絶縁体膜に配線
溝を形成する工程。 ■ 非流動性絶縁体膜」二の食刻用マスクの表面及び配
線溝に配線用導体を堆積する工程。 ■ 食刻用マスク及びその表面」二に堆積した配線用導
体を除去するリフトオフ工程。 θ 非流動性絶縁体膜とその間隙の配線溝に埋め込まれ
た配線導体の表面全体をinうように流動性絶縁体層を
形成する工程。 ■ 上記工程を経た基板を加熱し」1記流動性絶縁体層
の平坦化を行なう工程。(2) A method for manufacturing a wiring HT structure including the following steps. ■ A process of forming a non-fluid insulating film on the substrate. @ Step of forming an etching mask on the non-flowable insulator 1 using a resist. Step 1: Forming wiring grooves in the non-fluid insulating film using a θ etching mask. ■ Non-flowing insulator film" Step of depositing wiring conductors on the surface of the second etching mask and in the wiring grooves. ■ Lift-off process to remove wiring conductors deposited on the etching mask and its surface. θ A process of forming a fluid insulating layer so as to cover the entire surface of the non-fluid insulating film and the wiring conductor embedded in the wiring groove in the gap between the non-fluid insulating film. (2) A step of heating the substrate that has undergone the above steps to planarize the fluid insulating layer described in (1) above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11921681A JPS5821844A (en) | 1981-07-31 | 1981-07-31 | Manufacture of wiring structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11921681A JPS5821844A (en) | 1981-07-31 | 1981-07-31 | Manufacture of wiring structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5821844A true JPS5821844A (en) | 1983-02-08 |
Family
ID=14755820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11921681A Pending JPS5821844A (en) | 1981-07-31 | 1981-07-31 | Manufacture of wiring structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5821844A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6179301A (en) * | 1984-09-27 | 1986-04-22 | Nec Corp | Band-pass filter of dielectric resonator |
JPH05343532A (en) * | 1992-02-26 | 1993-12-24 | Internatl Business Mach Corp <Ibm> | Conductor structure of low resistivity capped with heat-resisting metal |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5135290A (en) * | 1974-09-20 | 1976-03-25 | Hitachi Ltd | Handotaisochi no seizohoho |
JPS51128277A (en) * | 1975-04-30 | 1976-11-09 | Fujitsu Ltd | Semiconductor unit |
JPS54156488A (en) * | 1978-05-31 | 1979-12-10 | Hitachi Ltd | Manufacture for semiconductor device |
-
1981
- 1981-07-31 JP JP11921681A patent/JPS5821844A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5135290A (en) * | 1974-09-20 | 1976-03-25 | Hitachi Ltd | Handotaisochi no seizohoho |
JPS51128277A (en) * | 1975-04-30 | 1976-11-09 | Fujitsu Ltd | Semiconductor unit |
JPS54156488A (en) * | 1978-05-31 | 1979-12-10 | Hitachi Ltd | Manufacture for semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6179301A (en) * | 1984-09-27 | 1986-04-22 | Nec Corp | Band-pass filter of dielectric resonator |
JPH05343532A (en) * | 1992-02-26 | 1993-12-24 | Internatl Business Mach Corp <Ibm> | Conductor structure of low resistivity capped with heat-resisting metal |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0129476B1 (en) | Planar interconnection for integrated circuits | |
JP2593821B2 (en) | Integrated semiconductor circuit and its manufacturing method. | |
JPS595629A (en) | Double layer surface stabilizing method | |
KR100331906B1 (en) | Method for manufacturing a semiconductor device | |
JPH1074834A (en) | Semiconductor device and manufacture thereof | |
JPH0332215B2 (en) | ||
JPH04229618A (en) | Integrated circuit device contact and formation method thereof | |
JPH063804B2 (en) | Semiconductor device manufacturing method | |
KR100896159B1 (en) | Semiconductor device and method for manufacturing same | |
JPS5821844A (en) | Manufacture of wiring structure | |
KR100269926B1 (en) | Method of forming wirings | |
JPS61284937A (en) | Semiconductor device and manufacture thereof | |
JP2716156B2 (en) | Method for manufacturing semiconductor device | |
JP2606315B2 (en) | Method for manufacturing semiconductor device | |
JPH08139190A (en) | Manufacture of semiconductor device | |
JP3074841B2 (en) | Method for manufacturing semiconductor device | |
KR100352304B1 (en) | Semiconductor device and method of manufacturing the same | |
JPS5877247A (en) | Manufacture of wiring structural body | |
JPH0590203A (en) | Manufacture of semiconductor device | |
JPH07147281A (en) | Manufacture of semiconductor integrated circuit device | |
JP2000031278A (en) | Semiconductor device and manufacture thereof | |
JPH1079433A (en) | Manufacture of insulating layer acting as intermetal dielectric | |
JP2000133706A (en) | Semiconductor device and its manufacture | |
JPH06244180A (en) | Semiconductor device and its manufacture | |
JPS5966125A (en) | Manufacture of semiconductor device |