JPS58218160A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS58218160A JPS58218160A JP57101010A JP10101082A JPS58218160A JP S58218160 A JPS58218160 A JP S58218160A JP 57101010 A JP57101010 A JP 57101010A JP 10101082 A JP10101082 A JP 10101082A JP S58218160 A JPS58218160 A JP S58218160A
- Authority
- JP
- Japan
- Prior art keywords
- buried layer
- transistor
- under
- region
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Abstract
Description
【発明の詳細な説明】
この発明は、半導体集積回路、特に、相補型ＭＯＳ集積
回路（０ＭＯ５ＩＣ）の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor integrated circuits, particularly complementary MOS integrated circuits (0MO5IC).
ＣＭＵＳ ＩＣは同−基枚にＰチャネルＭＯＳトラン
ジスタ（Ｐ−ＭＯ８Ｔ）とＮチャネルＭＯＳトランジス
タ（Ｎ−ＭＯ８Ｔ）とが形成されるので、これらを構成
するＰ型拡散層とＮ型拡散層との間で寄生バイポーラト
ランジスタが形成され、ラッチアップと呼ばれる０ＭＯ
５ＩＣ独特の現象が生じ、この現象のために素子の破壊
が発生し、これが０ＭＯ８ＩＣの最大の欠点といわれて
いる。Since a CMUS IC has a P-channel MOS transistor (P-MO8T) and an N-channel MOS transistor (N-MO8T) formed on the same substrate, there is a gap between the P-type diffusion layer and the N-type diffusion layer that constitute these. A parasitic bipolar transistor is formed in 0 MO, which is called latch-up.
A phenomenon unique to 5IC occurs, and this phenomenon causes destruction of the element, which is said to be the biggest drawback of 0MO8IC.
第１図は、ＣＭＯ５回路の最小単位を示したものである
。ＡはＰ −Ｍ ＯＳ Ｔで、（１）はそのソース。FIG. 1 shows the minimum unit of the CMO5 circuit. A is P-MOST, and (1) is its source.
（２）はそのドレイン、ＢはＮｔＭＯ８Ｔで、（３）は
そのソース、（４）はそのドレインで、ｌ’ ＋ Ｍ
ＯＳ Ｔのソースは）は電源端子■ＤＤに、Ｎ −Ｍ
ＯＳ Ｔのソース（３）は電源端子■ｓｓに接続され、
両ＭＯ８Ｔ Ａ。(2) is its drain, B is NtMO8T, (3) is its source, (4) is its drain, l' + M
The source of OS T is the power supply terminal ■DD, N-M
The source (3) of the OS T is connected to the power supply terminal ■ss,
Both MO8T A.
Ｂのゲートは共通に入力端子ｉｎに接続され、Ｐ−ＭＯ
５ＴＯ）ドＬイア１２））とＮ−ＭＯ８’ＴＯ）ｌ’ｌ
ｚイ７（４）とは共通に出力端子ｏｕｔに接続される。The gates of B are commonly connected to the input terminal in, and the gates of P-MO
5TO) doLia12)) and N-MO8'TO)l'l
It is commonly connected to the output terminal OUT with ZI7(4).
第２図は第１図の回路を実際に構成した従来のＣＭＯ８
ＩＣの構造を示す新出１図で、（５）はＮ型基板、ｆ６
１ハＮ −Ｎ１０ Ｓ ７ｒＢ ヲＨ成ずルタメ（１）
Ｐ−型ウェル、（７）は絶縁層、（８）は金属電極、
（９）は電源端子ＶＳＳ形成用Ｐ型半峙体領域（Ｐアイ
ソレーション）、（ｌＯ）は電ｇ喘子ＶＤＤ形成用Ｎ型
半棉体領域（Ｎ＋アイソレーション）である。Figure 2 shows a conventional CMO8 that actually configures the circuit shown in Figure 1.
New figure 1 showing the structure of the IC, (5) is an N-type substrate, f6
1ha N -N10 S 7rB woH Nazurutame (1)
P-type well, (7) is an insulating layer, (8) is a metal electrode,
(9) is a P-type half-solid region (P isolation) for forming the power supply terminal VSS, and (lO) is an N-type half-diameter region (N+ isolation) for forming the electric current terminal VDD.
Ｃｋｌ ＯＳ Ｉ Ｃにおいて、ラッチアップに関係
するバイポーラトランジスタおよび抵抗が第２図に破線
で示すように寄生する。ｔｉｌｌはＰ −ｒＡ ＯＳ
’Ｉ”Ａのソース領域（１）とＮ型基板（５）とＰ−型
ウェル（６）との間で形成されるＰＮＰ：′トランジス
タ、（１２１はＰ＋ Ｍ ＯＳ ”ｒＡのドレイン領域
（２）とＮ型基板（５）とＰ−型ウェル（６）との間に
形成暴れるＰ Ｎ Ｐ トランジスタ、口ＪはＮ−ＭＯ
３Ｔ ’ｆｈのソース領域（３）とＰ−胃：：：
型ウェル（６）とＮ型基板（５）との間に形成されるＮ
ＰＮトランジスタ、（１４１ハＮ−Ｍ ｏ Ｓ Ｔ
Ｂ （７） ｌ’ Ｌ／ イン領域（４）とＰ−型ウェ
ル（６）とＮ型基板（５）との間に形成されるＮ ｌ’
Ｎ ）ランジスタ、（１９はＮ型基板１５）内の電源
端子ＶＤＤへ至るまでの抵抗、（１６）はＰ−ＭＯ５Ｔ
Ａのソース領域（１）内の抵抗、ＵカはＰ−型ウェ
ル（６）内の電源端子ＶＳＳへ至るまでの抵抗、αＱは
Ｎ−ＭＯＳ・Ｔ Ｂのソース領域（３）内の抵抗である
。In Ckl OS I C, bipolar transistors and resistors related to latch-up are parasitic as shown by the dashed lines in FIG. till is P-rA OS
PNP formed between the source region (1) of 'I'A, the N type substrate (5) and the P- type well (6): 'transistor, (121 is the drain region (2) of P+ MOS 'rA ) and a PNP transistor formed between the N-type substrate (5) and the P-type well (6), the opening J is an N-MO
3T'fh source region (3) and P-gastric:::N formed between the type well (6) and the N-type substrate (5)
PN transistor, (141HN-MoST
B (7) l' L/N l' formed between the in region (4), the P-type well (6), and the N-type substrate (5)
N) transistor, (19 is the resistance leading to the power supply terminal VDD in the N type board 15), (16) is P-MO5T
The resistance in the source region (1) of A, U is the resistance up to the power supply terminal VSS in the P-type well (6), and αQ is the resistance in the source region (3) of N-MOS/TB. be.
第３図は第２図で破線で示した寄生素子による寄生回路
の構成を示すものである。FIG. 3 shows the configuration of a parasitic circuit made up of parasitic elements indicated by broken lines in FIG.
ラッチアップと称する現象は、入力又は出力にインパル
スが加わると、電源端子■ＤＤとＶＳＳとの間に極めて
大きな′磁流が流れ、破壊に至るものである。従来の構
造は、ウェル下部の抵抗はきわめて大きく、寄生ＮＰＮ
）ランジスタのベース領域の不純物濃度が低いために
トランジスタはＯＮしやすい、つまり３ラツチアツプが
起こり易いという欠点があった。A phenomenon called latch-up occurs when an impulse is applied to the input or output, and an extremely large magnetic current flows between the power supply terminals DD and VSS, leading to destruction. In the conventional structure, the resistance at the bottom of the well is extremely large, and parasitic NPN
) Since the impurity concentration in the base region of the transistor is low, the transistor has the disadvantage that it is easy to turn on, that is, 3-latch up is likely to occur.
ハ
この発明は１総のような従来のものの欠点を除去するた
めにｑ′（諒れたもので、ラッチアップに関■。This invention was developed in order to eliminate the drawbacks of the conventional ones such as 1.
係するバイポーチトランジスタのＪ１幅重重１ＦＥを低
下させることにより、ラッチアップ耐１けの大きい
ＩＣＭＯ５ｉｃを提供することを目的としている。By lowering the J1 width, weight, and weight of the related bi-pouch transistor, the latch-up resistance can be increased by one order of magnitude.
The purpose is to provide ICMO5ic.
以下、回向を参照して本発明を説明する。第４図は本発
明の一実施例を示す断面図である。（５）はＮ型基板、
（６）はＮ ＋ Ｍ ＯＳ Ｔ Ｂを形成するための
ｌ′−型ウェル、（７）は絶縁ｊ１届、（８）は金属電
極、（９）は゛嘔源端子ＶＳＳ形成用ｌ）型半導体ｉ＋
ｒｉ域（Ｐアイソレーション）、Ｉ’＋Ｉｊは電’ｔｌ
も（端子ＶＤＩ）形成用Ｎ型半導体領域（Ｎアイソレー
ション）である。第２図と異なるところは、Ｐ−型ウェ
ル（６）の１１下に埋込層（１湧を形成し、Ｐアイソレ
ーション直下の埋込層部分（２０１の表面不純物濃度を
、他部、すなわちＮ １ｖｌ（ＪＳＴ Ｂのソース
（３）、ドレイン（４）領域直下の埋込層部分（１９の
表面不純物濃度よりも高くしておき、第４図で示すよう
に、Ｐアイソレーション（９）の直下の埋込層部分（２
■の浮き上がりが、他部の埋込層部分（１９）の浮き上
がりより大きくなるようにした点である。！２１１は１
′″Ｊ−型エピタキシャル層である。Hereinafter, the present invention will be explained with reference to Eko. FIG. 4 is a sectional view showing an embodiment of the present invention. (5) is an N-type substrate,
(6) is an l'-type well for forming N+MOS T B, (7) is an insulating layer, (8) is a metal electrode, and (9) is an l'-type semiconductor for forming a source terminal VSS. i+
ri region (P isolation), I'+Ij is electric 'tl
It is also an N-type semiconductor region (N isolation) for forming (terminal VDI). The difference from FIG. 2 is that a buried layer (1 well) is formed under 11 of the P-type well (6), and the surface impurity concentration of the buried layer portion (201) directly under the P-type well (6) is N 1vl (JST The buried layer portion directly under the source (3) and drain (4) regions (19) is made higher than the surface impurity concentration, and as shown in Figure 4, the P isolation (9) The buried layer part directly below (2
The raised part (2) is made larger than the raised part of the other buried layer portion (19). ! 211 is 1
'''J-type epitaxial layer.
このような構成にすることにより、ｙ５２図１こ破線で
示した寄生トランジスタのうち、Ｎ ＋ Ｍ ＯＳ’Ｉ
’ Ｂのソース領域（３）とＰ−型ウェル（６）とＮ
型基板（５）との間に形成されるＮＰＮ）ランジスタ！
１３＋及びＮ −Ｍ ＯＳ Ｔ Ｂのドレイン領域（
４）とＰ−型ウェル（６）とＮ型基板（５）との間に形
成されるＮＰＮ ｌ−ランジスタ（襖においてベース領
域の不純物濃度が高（なることにより、両寄生Ｎ）’Ｎ
）ランジスタ１１３１ 。By adopting such a configuration, among the parasitic transistors indicated by broken lines in Fig. 1, N + MOS'I
'B source region (3), P-type well (6) and N
NPN) transistor formed between the mold substrate (5)!
13+ and N-MOS T B drain regions (
4) and the NPN l-transistor formed between the P-type well (6) and the N-type substrate (5) (because the impurity concentration in the base region is high in the sliding door, both parasitic N)'N
) transistor 1131.
Ｉの電流増幅率（ｈｐＥ）を低下さぜることができる。The current amplification factor (hpE) of I can be reduced.
なお、上記実施例は、■嘴型基板のＣＩ−′ｉ０Ｓ １
１Ｃについて示したが、Ｐ型基板の場合でも同様の効果
を得ることができる。また第４図において、十
Ｐアイソレーション（９）とＰ＋アイソレーション直下
の埋込層（２０）に隙間があるが、両者を継ぐとさらに
よい効果が得られる。Note that the above embodiment is based on CI-'i0S 1 of beak-shaped substrate.
Although the case of 1C is shown, similar effects can be obtained even in the case of a P-type substrate. Further, in FIG. 4, there is a gap between the 10P isolation (9) and the buried layer (20) directly under the P+ isolation, but even better effects can be obtained by connecting both.
また上記実施例ではＰ−ウェル（６）を囲むＰ＋アイソ
レーション（９）直下の埋込層部分（至）の表面不純物
濃度を高くした場合について説明したが、本発明はＰ−
ウェル（６）内にＭ ＯＳ ’ｒを形成する部分とそう
でない部分とがあり、ＭＯ８Ｔを形成し／ｊい部分の直
下の埋込Ｊ−の表面不純物濃度を高くするようにしたも
のであってもよい。Furthermore, in the above embodiment, a case was explained in which the surface impurity concentration of the buried layer portion directly under the P+ isolation (9) surrounding the P-well (6) was increased.
There are parts in the well (6) where MOS'r is formed and parts where it is not, and the surface impurity concentration of the buried J- directly under the part where MO8T is formed is increased. It's okay.
以上のように、この発明によれば、ウェル領域内のＭ
Ｌ） Ｓ ’ｒが形成される部分の直下の埋込層の表面
濃度よりそれ以外の部分の直下の埋込層の表面濃度を高
くして寄生ＮＰＮ トランジスタのベース領域を濃度の
低い埋込層で形成することにより、寄生ＮＰＮＩ−ラン
ジスタのｈＦＥを下げ、ラッチアップを防止できる効果
がある。As described above, according to the present invention, M in the well region
L) The base region of the parasitic NPN transistor is made into a buried layer with a lower concentration by making the surface concentration of the buried layer directly under the other portions higher than the surface concentration of the buried layer directly under the portion where S'r is formed. By forming the transistor, hFE of the parasitic NPNI-transistor can be lowered and latch-up can be prevented.
第１図は、ＣＭＯ８回路の最小単位であるインバータの
回路図、第〉収１は第１図の回路を実際に構成した従来
のＣＭＯ５ＩＧの構造を示す断面図、第３図は第２図で
破線で示した寄生素子により構成される回路の回路図、
第４図は本発明の一実施例による半導体集積回路の断面
図である。
図において、（５）はＮ型基板、（６）はＰ−型ウェル
、（９）はＰアイソレーション、（１９はＰ−ウェル直
下の埋込層、（２０）はＰ−アイツレ−ジョイ直下の埋
込層、（２１１はＮ−エピタキシャル層である？。
なお図中、同一符号は同−文、は相当部分を示す。
代理人 葛 野 信 −第１図
ｓｓ
第２図
第３図
手続補正書（自発）
特許庁長官殿
１、事ｒ’ｉ ノ表示 特願昭 ５７−１０１０
１０ 号２、発明の名称 半導体集積回路
３、 補正をする者
事件との関係 持許出屑１人
４．１５．、 、 （’ｅ““、”″““°パ”６
、補正の内容
特許請求の範囲
（１）半漢体基板と、この半導体基板上に形成、されＭ
２Ｓ）ランジスタが形成されるウェル領塚を有するエピ
タキシャル層と、少なくとも上記２エル領域の直下に形
成された埋込層とを備え、上記エピタキシャル層は上記
ウェル領域内の￥ＯＳトランジスタが形成される部分の
直下の埋込層の表面濃度よりＭＯＳ）ランジスタが形成
されない部分の直下の埋込層の表面濃度を高くしてエピ
タキシャル成長により形成されていることを特徴とする
半導体集積回路。
（２）ＭＯＳ）ランジスタが形成されない部分が、上記
エピタキシャル層の表面に形成され左しイソレーション
の直下の領域であることを特徴とする特許請求の範囲第
１項記載の半導体集積回路。Figure 1 is a circuit diagram of an inverter, which is the smallest unit of the CMO8 circuit, Figure 1 is a cross-sectional view showing the structure of a conventional CMO5IG that actually constitutes the circuit in Figure 1, and Figure 3 is the same as Figure 2. A circuit diagram of a circuit composed of parasitic elements indicated by broken lines,
FIG. 4 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, (5) is an N-type substrate, (6) is a P-type well, (9) is a P-isolation, (19 is a buried layer directly below the P-well, and (20) is directly below the P-type well. Embedded layer, (211 is the N-epitaxial layer? In the figures, the same reference numerals and sentences indicate corresponding parts. Agent Makoto Kuzuno - Figure 1 SS Figure 2 Figure 3 Procedure Written amendment (spontaneous) Mr. Commissioner of the Patent Office 1, Indication of fact r'i Patent application No. 57-1010
10 No. 2, Title of the invention Semiconductor integrated circuit 3, Relationship to the case of the person making the amendment Licensed waste 1 person 4.15. , , ('e““,””“°pa”6
, Contents of the amendment Claims (1) A semi-Chinese board and a semiconductor board formed on this semiconductor board.
2S) An epitaxial layer having a well region in which a transistor is formed, and a buried layer formed at least directly under the 2L region, the epitaxial layer being a portion in the well region where an OS transistor is formed. 1. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is formed by epitaxial growth with the surface concentration of the buried layer directly under a portion where no MOS transistor is formed higher than the surface concentration of the buried layer directly under the MOS transistor. (2) The semiconductor integrated circuit according to claim 1, wherein the portion where no MOS transistor is formed is a region directly below an isolation formed on the surface of the epitaxial layer.
Claims (1)
ＭＯＳ）ランジスタが形成されるウェル領域を有するエ
ピタキシャル層と、少なくとも上記ウェル領域の直下に
形成された埋込層とを備え、上記エピタキシャル層は上
記ウェル領域内のＭＯＳトランジスタが形成される部分
の直下の埋込層の表面濃度よりＭＯＳ）ランジスタが形
成されない部分の直下の埋込層の表向濃度を篩くしでエ
ピタキシャル成長により形成されていることを特徴とす
る半導体集積回路。 ＋２１Ｍ０Ｓトランジスタが形成されない部分が、上記
エピタキシャル層の表向に形成された電源端子形成用ア
イソレーションの直下の領域であることを特徴とする特
許請求の範囲第１項記載の半導体集積回路。(1) A semiconductor device comprising a semi-rod substrate, an epitaxial layer formed on the semiconductor substrate and having a well region in which a MOS transistor is formed, and a buried layer formed at least directly under the well region; The layer is formed by epitaxial growth using a sieve to reduce the surface concentration of the buried layer immediately below the portion where the MOS transistor is formed in the well region. A semiconductor integrated circuit characterized by: 2. The semiconductor integrated circuit according to claim 1, wherein the portion where the +21M0S transistor is not formed is a region immediately below an isolation for forming a power supply terminal formed on the surface of the epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57101010A JPS58218160A (en) | 1982-06-11 | 1982-06-11 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57101010A JPS58218160A (en) | 1982-06-11 | 1982-06-11 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58218160A true JPS58218160A (en) | 1983-12-19 |
Family
ID=14289261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57101010A Pending JPS58218160A (en) | 1982-06-11 | 1982-06-11 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58218160A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5160996A (en) * | 1987-10-08 | 1992-11-03 | Matsushita Electric Industrial Co., Inc. | Structure and method of manufacture for semiconductor device |
| US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
| US5406513A (en) * | 1993-02-05 | 1995-04-11 | The University Of New Mexico | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits |
-
1982
- 1982-06-11 JP JP57101010A patent/JPS58218160A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5160996A (en) * | 1987-10-08 | 1992-11-03 | Matsushita Electric Industrial Co., Inc. | Structure and method of manufacture for semiconductor device |
| US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
| US5406513A (en) * | 1993-02-05 | 1995-04-11 | The University Of New Mexico | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits |
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