JPS58218146A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPS58218146A JPS58218146A JP57088413A JP8841382A JPS58218146A JP S58218146 A JPS58218146 A JP S58218146A JP 57088413 A JP57088413 A JP 57088413A JP 8841382 A JP8841382 A JP 8841382A JP S58218146 A JPS58218146 A JP S58218146A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor device
- pellet
- polyimide resin
- material layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、母材である基板−＼被取付体である半導体
ペレットを半田等のろう材で固着して組立、樹脂封止を
行わせる半導体装置のろう材層表面の酸化ｐ１正を図る
ことを主な目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to the soldering material layer surface of a semiconductor device in which a substrate as a base material and a semiconductor pellet as an attached object are fixed with a brazing material such as solder and then assembled and resin-sealed. The main purpose is to make the oxidation p1 positive.
現在例えばトランジスタ等の半導体装りを製造するため
には、ペレットマウント工程を経ている。Currently, in order to manufacture semiconductor devices such as transistors, a pellet mounting process is used.
このペレットマウント工程は、一般に放熱板を兼ねる基
板上にペレットを半田付けして固着する工程であって、
次のような作業を行っている場合が多い。すなわち１．
まず第１図に示すように、基板ｌの半田付は予定位置ａ
上に半田片２を載置しておき、つぎに、これらを加熱炉
中へ導き半田片２を溶融させるとともに、溶融した半田
２′上に、なじみ易くするために微摺動させながらペレ
ット３を供給して半田付けを行っている。ところでこの
ペレットヤウントに関しては、固着して製造完了した半
導体装置の寿命を劣化させないために、半田の熱酸化防
止を図る必要がある。したがって従来より第２図に示す
ように、加熱炉４は、基板ｌ及び半田片２を低温（約２
５０°Ｃ以下）のブリヒータ５で予熱してから、高滓２
５０°Ｃ〜３５０″Ｃのビータ６で半田片２を溶融して
、半田２′・とじている。この時に周囲をカバー７にて
覆って、カバー７内に不活性ガスとしてのＮ２ガスを充
満させて半田２′の熱酸化防止を行っている。This pellet mounting process is a process in which pellets are generally soldered and fixed onto a board that also serves as a heat sink, and
They often perform tasks such as the following: That is, 1.
First, as shown in FIG.
The solder pieces 2 are placed on top of the solder pieces 2, and then they are introduced into a heating furnace to melt the solder pieces 2, and the pellets 3 are placed on top of the molten solder 2' while being slightly slid to make it easier to fit. soldering. However, regarding this pellet yarn, it is necessary to prevent thermal oxidation of the solder in order to prevent the pellet from sticking and deteriorating the life of the manufactured semiconductor device. Therefore, conventionally, as shown in FIG.
50°C or less), then preheat with the high temperature slag 2.
The solder piece 2 is melted in a beater 6 at 50°C to 350"C and soldered 2'. At this time, the surrounding area is covered with a cover 7, and N2 gas as an inert gas is introduced into the cover 7. This prevents the solder 2' from being thermally oxidized.
しかしカバー７内にＮ２ガスを常に完全に充満させる技
術は、現実には極めて困難であった。しかもペレットマ
ウント工程を自ｇａ＋、を化しようとする場合には、外
気と遮断する機構を採用せねばならず、半田の熱酸化防
止がより一層し・１鍾とがる欠点があった。However, in reality, the technique of completely filling the cover 7 with N2 gas is extremely difficult. Moreover, when attempting to make the pellet mounting process self-contained, it is necessary to adopt a mechanism to isolate it from the outside air, which has the disadvantage of further preventing thermal oxidation of the solder.
上記欠点を解消しようとすれ幻、半田２゛の固化し始め
た表面を酸化防止保設膜でｔイうことが考えられ、この
発明の発明者は、先に特開昭５５−１０３２７３号公報
にて、少くとも半１ｑ層表ｔｏｉ′＼、不活性かつ動粘
度が１０〜１０００００Ｃ８ｔの絶縁油被櫨恥を形成さ
せる半田状構体を提案した。しかしながら、更に釉々の
検討を重ねるにつれて、上述の提案にも、より一層改善
すべき点が見い出された。すなわち、上述め提案は、実
施例として、鎖状ジメチルボリシロキ讐ン等のシリコー
ンオイルを設定したように、゛半晶表面を外気と遮断し
酸化防止が行え、半田中の気泡やカス泡を残す危険が安
い点では完全な彼櫨が得餠く、またペレットの少くとも
側面をも被覆する必要がある場合、加熱によって、不都
合にもペレットの特性変′＊！１を招いてしまう間顧点
が生じていた。In order to solve the above-mentioned drawbacks, it was thought to cover the surface of the solder that had begun to solidify with an oxidation-preventing preservation film, and the inventor of this invention previously published Japanese Patent Application Laid-Open No. 55-103273. proposed a solder-like structure in which at least half of the surface layer is coated with insulating oil, which is inert and has a kinematic viscosity of 10 to 100,000 C8t. However, as we continued to study the glazes further, we discovered that there were still points that needed to be improved in the above proposal. In other words, the above-mentioned proposal uses a silicone oil such as chain dimethylbolysiloxane as an example, which ``can prevent oxidation by blocking the semi-crystalline surface from the outside air, and can prevent air bubbles and scum bubbles in the solder. Complete coverage is advantageous in terms of the low risk of leaving residue, and if it is necessary to coat at least the sides of the pellets, heating may disadvantageously change the properties of the pellets'*! There was an issue that resulted in 1.
そこで、この発明は、以上の訃点を考慮して探究した結
果提案するもので、基板へ半導体ペレットをろう付固着
し、ペレット及びその近傍を樹脂封止するものにおいて
、少くともろう材層表面へ低温硬化性で粘度が１０〜２
００ポアズのポリイミド系樹脂を被覆させて樹脂封止し
たことを特徴としている。次にこの発明の具体的一実施
例を説明する。Therefore, this invention was proposed as a result of research in consideration of the above-mentioned disadvantages.In a method in which a semiconductor pellet is brazed and fixed to a substrate and the pellet and its vicinity are sealed with resin, at least the surface of the brazing material layer is Low temperature curing and viscosity of 10-2
It is characterized by being coated with a 00 poise polyimide resin and sealed with the resin. Next, a specific embodiment of the present invention will be described.
第３図は、この発明の具体的一実施例を示す半導体装置
のベレットマウントエ稈完了時のペレットマウント構体
を示し、８は、素地を銅とし表面にニッケルメッキ、を
施した放熱板兼用のステム基板・ °は鉛・轡・銀を主
組成とする固着半田層・ｌＯけ半田層祠の表面よりペレ
ツ）１１の上面端縁へかけて保護、被覆したポリイミド
系樹脂である。FIG. 3 shows the pellet mount structure of a semiconductor device according to a specific embodiment of the present invention when the pellet mount structure is completed, and 8 shows a pellet mount structure made of copper and plated with nickel on the surface, which also serves as a heat dissipation plate. The stem board 11 is a polyimide resin which is protected and coated from the surface of the adhesive solder layer/lO solder layer whose main composition is lead, slag, and silver to the edge of the upper surface of the pellet (11).
このボリイミ）果樹＝の具体的な相判としては、次の第
１表にか・すよつな緒特性を有し芳香族四塩基酸例えば
ピロ）リット酸と芳香族ジアミン例え １ハ４，４
’ジアミンジフエニルエーテルとを縮重合反応させて得
られ、化学式は
第 １ 表
つぎに第４図は、第３図に示したホ゛リイミド系樹脂ｌ
Ｏを被覆したベレットマウント構体に、内部金属細線１
２．１２をペレットｌｌ上の電棒と外部導出リード１３
．１３との間に架設配線接紗し、ざらにトランスファー
成形法によって、外皮樹脂１４としてのエポキシ樹脂を
モールド成形して完成させた半導体装置の断面図である
。この第４図に示した半導体装置は、その円Ａ部を拡大
して示す第５図より明らかなように、外皮樹脂１４が、
トランスファ成形時の加熱溶融され低い圧力で加圧され
て、常温でかろうじて働化ししたがって伸び率がかなり
大きいポリイミド系樹脂１０にかかると、両者の接合境
界面は、エポキシ樹脂の粘性とポリイミド系樹脂１０表
面との貼着性の作用と考えられるが、波形状となってい
る。The specific relationship between this fruit tree and fruit tree is shown in Table 1 below. 4
The chemical formula is shown in Table 1 and Figure 4 shows the polyimide resin l shown in Figure 3.
The internal thin metal wire 1 is attached to the O coated bullet mount structure.
2.12 Connect the electric rod on the pellet ll and the external lead 13
．． 13 is a cross-sectional view of a semiconductor device completed by gluing wiring between the semiconductor device 13 and molding an epoxy resin as the outer skin resin 14 using a rough transfer molding method. In the semiconductor device shown in FIG. 4, as is clear from FIG. 5, which is an enlarged view of circle A, the outer resin 14 is
When the polyimide resin 10, which is heated and melted during transfer molding and pressurized at a low pressure, is applied to the polyimide resin 10, which is barely activated at room temperature and therefore has a considerably high elongation rate, the bonding interface between the two is the viscosity of the epoxy resin and the polyimide resin 10. This is thought to be due to the adhesion to the surface, but it has a wavy shape.
上記の半導体装Ｍは、第１にペレットマウント時に、ペ
レットマウント前の溶融半田上にポリイミド系樹脂を彫
に溶剤に溶して塗布するたけで、ペレットマウント徒に
被覆硬化させることができる。これは半田層９の融点が
１８０−２００°Ｃ稈度に対して、硬化性が第１表のよ
うに１５０°Ｃで３０分経過すると指触テストでも、指
につかない表面硬化を示すことから明白である。第２に
ポリイミド系樹脂１０が著しく絶縁性良好であり、しか
もエポキシ樹脂１４と断面波形境界面を形成し、好適な
接着性を示すので、半導体装置として著しく良好耐湿性
が期待できる。そして、物面この半導体装置は、半田表
面を被覆するので、ペレットマウント時の半田酸化防止
が図れる。ざらに、この半導体装置は、一般に保睦被瞑
形成処理が施されないペレットの側面へは、外皮樹脂１
４中に微量ながら含捷れる中性子線発生物質よりの中性
子線が放射されても、ペレットの特性を劣化させる場合
があるが、ポリイミド系椿脂ｌＯは申付子線を遮蔽する
機能があるので、前述した低温硬化上ともにペレットの
動作特性劣化を阻止できる優れた長所がある。First, the semiconductor device M described above can be coated and hardened during pellet mounting by simply applying a polyimide resin dissolved in a solvent onto the molten solder before pellet mounting. This is because the melting point of the solder layer 9 is 180-200°C, and the hardening property is as shown in Table 1. After 30 minutes at 150°C, the surface hardens so that it does not stick to the fingers even in the finger touch test. It's obvious. Secondly, the polyimide resin 10 has extremely good insulation properties, forms a cross-sectionally corrugated boundary surface with the epoxy resin 14, and exhibits suitable adhesion, so that extremely good moisture resistance can be expected as a semiconductor device. Furthermore, since the surface of this semiconductor device is coated with solder, it is possible to prevent solder oxidation during pellet mounting. In general, in this semiconductor device, the outer skin resin 1 is applied to the side surface of the pellet which is not generally subjected to the protective coating treatment.
Even if a small amount of neutron radiation is emitted from the neutron radiation generating substance contained in 4, it may deteriorate the properties of the pellet, but polyimide-based camellia lO has the function of shielding the neutron radiation. It has the excellent advantage of being able to prevent deterioration of the operating characteristics of pellets, as well as the aforementioned low temperature curing.
尚、上記実ｒ！１）・例では、ペレットマウント時の溶
融半田上にポリイミド系樹脂全室イ汀したが、この発明
はこの他にペレット表面を含めて基板全面に塗布するよ
うにしてもよく、実施例と同様な効果この発明を２実施
すれば、ペレット固着半田の酸があるものである。In addition, the above actual r! 1) In the example, the polyimide resin was entirely coated on the molten solder during pellet mounting, but this invention may also be applied to the entire surface of the board, including the pellet surface. If this invention is carried out twice, the acidity of the pellet-fixed solder will be obtained.
イ、（、、□、□、。ヵ、やカフ聰、７８１．１６．６
半導体装置の動作特性劣化を阻止し得る点で他の半田保
護膜を設けるものより優れていて、さらにポリイミド系
樹脂が低温硬化性なので、塗布作業性も向上する等の効
果を奏する。I, (,,□,□,.Ka, Ya Kafu So, 781.16.6
It is superior to other solder protection films in that it can prevent deterioration in the operating characteristics of semiconductor devices, and furthermore, since the polyimide resin is curable at low temperatures, it also improves coating workability.
第１図は、従来のペレットマウント構体のマウント工程
を示す半田戦渦基板の断面図、第２図は従来の加熱炉の
略断面図、第３図はこの発明の一実施例に関するペレッ
トマウント構体の断面図、第４図はこの発明の一実施例
を示す半導体装置の断面図、第５図はその円Ａ部の拡大
１ｆ面図である。
８・・・・・基板、 ９・・・・ 半田側、
ｌＯ・・ ポリイミド系樹脂 １１ ・・ ペレット。
第１図
第２図
第３図
第４図
第５図FIG. 1 is a sectional view of a solder warp board showing the mounting process of a conventional pellet mount structure, FIG. 2 is a schematic sectional view of a conventional heating furnace, and FIG. 3 is a schematic sectional view of a pellet mount structure according to an embodiment of the present invention. 4 is a sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 5 is an enlarged 1f view of the circle A section thereof. 8... Board, 9... Solder side,
lO... Polyimide resin 11... Pellets. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
その近傍を樹脂封止したものにおいて、少くともろう材
層表面へ低温硬化性で粘度かｌＯ〜２００ポアズのポリ
イミド糸ｔｆｔｉ Ｂａを被覆させて樹脂封止したこと
を特徴とする樹脂封止半導体装置。In the case where a semiconductor pellet is fixed to a substrate with a solder and the pellet and its vicinity are sealed with a resin, at least the surface of the brazing material layer is coated with polyimide thread tfti Ba, which is a low-temperature hardening material and has a viscosity of 10 to 200 poise. A resin-sealed semiconductor device characterized by being sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57088413A JPS58218146A (en) | 1982-05-24 | 1982-05-24 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57088413A JPS58218146A (en) | 1982-05-24 | 1982-05-24 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58218146A true JPS58218146A (en) | 1983-12-19 |
Family
ID=13942104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57088413A Pending JPS58218146A (en) | 1982-05-24 | 1982-05-24 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58218146A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4893171A (en) * | 1988-03-30 | 1990-01-09 | Director General, Agenty Of Industrial Science And Technology | Semiconductor device with resin bonding to support structure |
| JP2013041870A (en) * | 2011-08-11 | 2013-02-28 | Furukawa Electric Co Ltd:The | Semiconductor device |
-
1982
- 1982-05-24 JP JP57088413A patent/JPS58218146A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4893171A (en) * | 1988-03-30 | 1990-01-09 | Director General, Agenty Of Industrial Science And Technology | Semiconductor device with resin bonding to support structure |
| JP2013041870A (en) * | 2011-08-11 | 2013-02-28 | Furukawa Electric Co Ltd:The | Semiconductor device |
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