JPS58218089A - Memory addressing system - Google Patents

Abstract

PURPOSE:To attain a memory addressing system where common data are written in lots of elements in the lump in addition to normal addressing with high speed, inexpensive, flexible, miniaturized and simple constitution, by assigning multiply addresses and using the addresses in common between plural elements. CONSTITUTION:In block diagram, 5 is a CPU8085, 6a, 6b, 6c, 6d are four IC memories in which 8-chip of 2114 are used as 1 byte memory each, and each of 3FF addresses of addresses of 2000-23FF, 2400-27FF, 2800-2BFF, 2C00-2FFF are assigned. Further, 7 is an address decoder to which 8 address buses is allocated among 16 buses 8, and five chip select lines 9a, 9b, 9c, 9d, 9e of 2000- 23FF, 2400-27FF, 2800-2BFF, 2C00-2FFF, 3000-33FF are outputted. This invention exemplifies the time for clearing 4096 bytes of 2000-2FFF is 9msec in comparison with the conventional 36msec.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory addressing method for a microcomputer system, in which a RAM memory connected to a microprocessor has a plurality of addresses, and the addresses are shared by n RAM memory cards. It is. In a system using a microprocessor as a controller arithmetic unit, memory areas are frequently cleared. Especially in systems that need to operate in real time, the time it takes to clear the memory @castle becomes a heavy burden on the program.

Figure 51-1 shows an example of a conventionally known process monitoring system, in which 1 is a process, 2 is a sensor, 5 is a measurement and control system using a microcomputer, and 4 is an actuator. In this way, 4000 bytes of data are sampled every second, that is, 1c40t feet every 10m5ec, and predictions are made based on the accumulated data and processes are controlled every second. You must clear the memory of the light and set it to all 0s. Therefore, as shown in Figure 2a, the program is set to 0 and set to 1), but this loads 2000 into the H register and loads =B[FFF. First write () to address 2000, then 2
001 address KO is included in the bottle 0006. Repeat this 4000 times to be exact F F F or 4096
If you don't turn it over, it won't finish, so if you clear it like that, this program will be 56mθ until it's all finished.
10
I want to do it every m6θC, so during sampling jnLt56
mθθC□.

You won't have to wait longer. Actually, by sampling every 910 mθec, -s 7. It becomes. A system that processes large amounts of data in real time by clearing the MET one byte at a time, such as this, takes time.
One drawback is that it has to be done quickly. Also, when writing common data to each RAM, there is a problem that it takes two hours to write one byte at a time.

In consideration of these points, the present invention provides a memory addressing system that is faster, less expensive, more flexible, smaller, and has a simple configuration.

That is, this invention allocates addresses in multiple ways and shares the addresses among the multiplexers.

In addition to normal addressing, it is configured to write common data to many elements at once.

By taking advantage of this fact, we configured it so that when a command is read, writing occurs at a specific element and address.'b17)
T-ah. , i Fig. 5 is a pull diagram of this embodiment, and 5 is an OP
U 8085.6a, 6b, 6c, 6d is 4 i
A memory uses 8 chips of 2114 each to provide 1 byte of memory, and each has 2000 to 257F.

2400~27FB', 28u"o~2 BI:l"
k', 20 D' Addresses of 3'FF of 0 to 2FIPF are assigned.

7 is an address decoder, to which 8 out of 16 address buses are assigned, and 2000 to 25Fb
', 2400~27FF, 2800~2Bli'll'
, 2000~2FPF, 3000~35II□F 5
Book chip select lines 9a, 9b, 9c, 9a, 9
e is output.

The select lines are the four memories 6a, 6b, 6c, '1. The chip select lines 9a and 9e, 9b and 98.98 and 9e, 96 and 98 are connected to the OR circuits 10a, 10b, 10c, 1 so that the chip select line and the chip select line to d are connected to each other.
0d to each output chip select line 11
a, 11b.

+ '1''''c, 11 dL are connected to the aforementioned four memories 6at 6b, 6c6d. Also 12
This is a data bus that connects the four GPUs 5 and each of the ten memories 6a to 6d.

In this circuit, 1liiK2oo'o~2 F 11'
2000 to 2111'll''F in memory at address F
can read and write addresses. Actually, the memory has 4K (4096) bytes from 2000 to 2FFF, but the addresses are from 2000 to 27FF, so the address decoders for these memories are different from each other for the normal addresses from 2000 to 2FFF. A memory chip somewhere is selected.

For chip selection after 3000, use chip select line 9
6 is input to all of the OR circuits 10a to 10'' (l) and is OR, so % 3000 and after □
If you select it, it will be selected.

For example, if you write data 0 to 3000 Honchi from OP U'5, it will be 2000.2400.2800.2000.
0 is written to all addresses. In the end 2
000.2QGj... If you clear address 0 and up to address 2FFF in order, it becomes address 4096, but 3000
From now on, each address has 4 addresses, so it is 300.
If you write 0 after 0, you will actually write 4 0's at a time, so in the previous example, you wrote 4 0's one by one, so it took 36m8ea, but in this example, it took 4 1pen. If it can be cleared within 10 seconds, the number of times it has to be cleared will be 1/4, so it can be cleared all in 9msθC.

Therefore, just change the constants in Figure 2 (a) mentioned earlier to Figure 2 (b), that is, load the H register &C2000 to 3000, and load FF F to B.
(4096) was loaded to 5FF (1024).
2000 to 2FFF with T program loaded into )
The time required to clear 4096 bytes of
In the practical example of this invention, it cost 9rnsea, whereas it used to cost 0c.
becomes.

Figures 3 and 4 are examples of the advanced version of Figure 3, which are the same as in Figure 3, using one 2716 chip in addition to the AM memory 6aAb66 to create an IK byte (as one RAM). 3
The memory 15e4 is assigned addresses 000 to 37FF, and the memory write line 14 of the RAM memories 6a' to 6d is controlled by the chip select line 9θ of numbers 6000 to 65'::+. The M memory 13 is connected at the address 3000 to 55FF, and the OR circuit 10e, 54 takes the OR of the chip select line 9θ and the memory write line 14 at addresses 3000 to 55FF.
Chip select 111 of 00-57F'F!9f and 50
00-55? 'H's Chip Select II! An OR circuit 10f that takes the OR of 9e is added to each OR circuit 1.
0θ.

10f output chip select lines 11a, 11f
are provided to the memories 6a to 6cL and 15, and the other connections can be considered to be the same as in Figure J'3.

Here, in the 0PU5 of Intel's 8085, the return instruction sets the code C9, and the ROM memory 13
eo from address 3000 to address 35FF assigned by
oKm is determined, and this 00 is set as a NoP command. Figure 4: In case ROM memory 13 is moved from address 3000 to 37FF11
3311 from 600011 assigned to gon, □-,,t
h:・v,) T6, 3rd. . ,.

and rtfl m all are selected z. Mataga 3
Figure and a) 61 ROM yt,”-J 13.l!
l(1 ah 7. yum. At the same time as reading the byte to 1 from 3ooo @ ground of 15, it is selected and a write signal is output. In other words, the read contents are written at the same time as reading.

That is, when data at address 3000 is read, that data is written to RAM memories 6a to 6dK at addresses 2000, 2400, 2800, and 2000. Rc1M
To read memory addresses 1605400 to 3711'iF, RAM memories 6a to 6d do not receive 1 so. ,IF3
In the case of the figure, it was just a matter of sending it. Thus, when reading the byte to 1 from 3ooo11, all this is written, and this 8
All the minutes are transferred to content 1 of the 6M memory 15.

There are 0 entries in 1K from 5000 to 55 FTP of this R6M memory 15, and 00 is deleted and cleared. The apU5 side receives the read content, but since it treats 00 as a NOP command, it doesn't do anything and just fires one after the other.I finished reading 3400.
If there is a return command at the address ahead, 1
After staring at 024 and writing 1024, I got 0PUS&C.
Control comes back.

If you put 4-6 and OALL 5000 in that way, you will get 4K)-Tal with 00 for all of them. In other words, 0PU5 intertwines the data 00 from address 6000 to address 53FF, and
All memory from address 2FFF is cleared.

Note that there are specific instruction data ★ other than the /tub instruction with data 00 in the above explanation that do not perform any operation even if the CPU is corrupted. By storing it in the 86M memory 15, it can also be initialized in each RAM.

In the case of Figure 3, the program must go through a loop as shown in Figure 2 (b), and in the case of Figure 314, returns and NOPs are executed regardless of these program instructions. Just by being connected, four addresses can be cleared with one instruction, so in the case of Figure 314, the time is approximately 1.7 msθC.

As described above, in this invention, the RAM memory connected to the microprocessor has a decimal number of addresses, and the addresses are shared by n EAM memories, so the memory is shared in 1/n time. data could be written.

Further, the circuit required for this purpose is almost only the addition of an OH gate, and since the gate elements on the printed circuit board are often left over, the cost increase due to adopting this method is small.

Also, by using the fact that the NδP instruction is 00, and considering the reading of Kinteki as data reading, we can exchange RAM reading and writing only at a specific address.
．． By executing the p instruction, common data can be written into the memory in a shorter time. In this case, R.O.
Although the M area becomes @-characterized, its load is much smaller than the multiple allocation of addresses. , In the example shown in the 1/4 figure, the time it takes to clear 1 byte of memory is 4ooμ
It is about UUa, which is + due to pure hardware.
O1'TJ8"-)v ′"t,""(-IJ "',
jp,, 776';& E A l has 1. In the case of narrow frame bars, hardware costs increase significantly, such as by creating a counter circuit, creating and connecting a clock generation circuit suitable for memory response, and creating an address bus switching circuit. Furthermore, there are many problems such as how to deal with software and hardware when an interrupt occurs while KOPU is being held. On the other hand, the main method can be controlled flexibly by software, so it can be used flexibly to handle difficult situations.

Although a specific element is specified in this example of the invention, it can be applied to any RAM or RδM.

Many microprocessors have a hop life of 4゛t-uO.
Therefore, the CPU is not limited to a specific one.
This method applies to devices that need to write common data in a large amount of RAMK in a short time, such as inspection equipment and data locators using microprocessors.

Process monitoring device 1. Widely applicable to RδM writers, etc.
71

[Brief explanation of the drawing]

Wear. 11:11□ Figure 3.1 is a diagram of the conventional process monitoring system of □, Figure J'2 faJI (bj is the program configuration diagram of the first embodiment, Figures 3 and 4 are different diagrams of this invention. It is a block diagram of an example process monitoring system. In the figure, 5: OPU, 6a, 6b, 6c, 6n
: RAM memory, 9a-9e : Chip select 1
lkA * 10a ~ 10: OR circuit, 7: Address decoder, 12: Data path, 137 ROM memory, 14: Memory write line.

Claims (1)

[Scope of Claims] +t+b Lower address portions are assigned to several RAMs to share the addresses, each EAM is selected by the upper address, and the upper address and lower address are shared.
In a device that allows memory addressing to be performed by the user, a valley 1 address (a predetermined upper address that can commonly select AM) is set, and the upper address and each RA
By performing addressing using addresses consisting of low-order addresses that are frequently assigned to M, several l
(Memory addressing method described in Section 1 tc. is stored in a ROM, and the address of the ROM is set to an address consisting of the predetermined upper address and a lower address assigned to each RA memory light 16
A memory addressing system characterized in that common data within the 10M is stored in each of the RAMs K@.