JPS58217045A - Code digit converting circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution, by changing output sides of memory elements of an RAM through a switching circuit according to the kind of code. CONSTITUTION:Bit outputs indicating positive/negative signs which are read out of memory sections A, C, E, and G among sections A-H of RAMs 1 and 2 are applied to sides A, C, E, and G of the switching circuit 3. Further, bit outputs indicating whether sign digits are improper or not which are read out of the sections B, D, F, and H are applied to sides B, D, F, and H of the circuit 3. The circuit 3 selects inputs by a control signal wherein the kind of a necessary code is specified; one bit indicating whether the code is positive or negative is outputted to an FF4 and the other bit indicating whether the code is the improper sign digit or not is outputted to an FF5. Thus, the positive/negative sign bit is set in the FF4 and used for specifying decimal operation mode and the bit indicating whether the code is the improper sign digit or not is set in the FF5 for improper sign digit processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides ten examples of arithmetic devices used in data processing devices.
This invention relates to a hex data code digit conversion circuit.

[Prior art]

Currently, in arithmetic devices that handle decimal data, a code digit conversion circuit is applied to the given decimal data in order to speed up the calculation and perform rational processing. ASCII, EBC
A method is adopted in which a code such as D4C is converted into a code representing either positive or negative and a code representing whether or not it is an illegal code. This type of conventional code digit conversion circuit has a circuit that determines the sign according to the input code digit, and a circuit that determines whether or not it is an invalid code digit as the main elements, and also specifies the calculation mode. The circuit includes a circuit for setting a code for the output code and the result, a circuit for generating an output code, a dinot correction circuit for overlapping codes, etc. However, since all of these circuits are complicated by cables, the number of circuits is large, and when the types of codes to be applied and the functions of QIJ Tichenok are included, the circuit The disadvantage is that the complexity of the system increases, leading to an increase in the price of hardware.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to create an economical code that can reduce the number of manufacturing steps with a simple configuration by converting the code digits of given IO base data using a memory element. To provide a digit conversion circuit.

[Structure of the invention]

The code digit conversion circuit according to the present invention converts the address corresponding to the code digit represented by multiple bits in the decimal operation data (5) into an incorrect bit representing either positive or negative corresponding to multiple codes. A memory means in which a bit indicating whether or not it is a code digit is stored, and a bit stored in the memory means.

Or, from among the bits read out from the memory means, the bit representing either positive or negative corresponds to the designated code of the plurality of codes, and the invalid code digit corresponds to the corresponding code. The present invention is characterized by comprising a selection means for separately extracting bits representing whether or not the present invention is true.

[Embodiments of the invention]

Next, embodiments of the code digit conversion circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. In fig.

The code digit is used as the input address. Then, in RAMs 1 and 2 such as (6), a bit representing positive or negative and a bit representing whether or not the code digit is an invalid code digit are written in correspondence in advance in the address corresponding to the code digit. Therefore, the bits representing positive or negative and the bits representing whether or not it is an invalid code digit are written in correspondence to each type of code.

3 is an input selection switching circuit that operates in conjunction with 2; 1, for example, A is used for the type of code required;
SCI1. O,AS(JT,],EBCDIC,O
Corresponding control signals of the codes ``O'' and EBCDTC1] are applied via two control lines C to control the switching circuit. 4 and 5 are frisonoflots zero which set a positive or negative bit and a bit indicating whether or not it is an invalid sign digit, respectively.

In the code digit conversion circuit configured as above, R
As shown in Figure 2, in memory sections A and B of AM 1, via 1' representing the positive or negative output of the code ASCII (I, O) and a bit representing whether or not it is an invalid code digit are stored in correspondence, respectively. , memory section C': and D have the code ASCII1. ] A bit representing whether the digit is positive or negative and a bit representing whether the digit is an invalid code digit are stored in correspondence with each other. Furthermore, the memory sections E and F of RAM 2 have the corresponding pins of the code EBCDIC,O, and the memory sections G and H have the codes EBCDIC,I.
The corresponding bits of are stored in the same way as in RAM 1. Then, the bit output representing positive or negative read from A, C, E, and G of these mea-niri divisions A-H is applied to the A, C, E, and G side of the switching circuit 3. The bit output representing whether or not it is an invalid code digit read from B, D, F, and H is B, D, 'F,
Added to H side. In the switching circuit 3, the above input is selected by a control signal specifying the type of code required.

One outputs a bit representing whether the corresponding code is positive or negative and is applied to the FrisonoFronograph 4, and the other outputs a bit representing whether the corresponding code is an invalid code digit or not and is applied to the FrisonoFronograph 5. Gakushi, Friso f70f4
A positive or negative bit is set in , and is used to specify the operation mode of decimal arithmetic, etc., and a bit indicating whether or not it is an invalid code digit is set in flip-flop 5, and is used for processing an invalid code digit. It will be done.

According to this embodiment, since the output side of the RAM memory element is switched according to the type of code in the switching circuit 3, the number of input address pins of the RAM is at least equal to the number of code digits of decimal data. This is a good thing, and the circuit configuration can be greatly simplified compared to the conventional technology.

FIG. 2 is a block diagram showing the configuration of a second embodiment according to the present invention. In this figure, numeral 11 indicates a RAM (or ROM) in which bits representing positive or negative are stored in advance at addresses corresponding to input code digits, and memory sections A, C, E, and GK are respectively , f'
L: +- AS (Jl, O, ASCI1.1.

Bits representing positive and negative corresponding to EBCDIC, 0 and EBCDIC, 1 are stored. 12 is a RAM (or ROM) in which a bit indicating whether or not there is an invalid code digit is stored in advance at the address corresponding to the input code digit (
9) Shows its memory divisions B, D, F and HKU SO, L" ASCI 1.0. ASCI 1.1
, EBC] MC,0 and FBCDIC,1. A bit indicating whether or not the code digit is an invalid code digit is stored. These RAM II and 12 each have 10 input address pins and 1 output pin, and 8 bits of the sign digit of decimal 10 data are input to 8 of the 10 input pins. , the other two have the code AS
CI1. Two selection signals corresponding to 0, ASCI1.1, EBCDI1, O1, and EBCDI1,1 are given. 4 and 5, as in the first embodiment, are flip-flops that respectively set a bit indicating that positive is negative and a bit indicating whether or not there is an invalid code digit;
It is. In such a configuration, each of RAMs 11 and 12 is addressed by a given 8-bit decimal data code digit, and a code type is specified by a 2-bit selection signal.
Outputs representing positive or negative bits from i1 and 12, respectively, and outputs representing whether or not there is an incorrect sign digit are selectively read out.

(10) FIG. 3 is a block diagram showing the configuration of a third embodiment of the present invention. In this figure, 13.
Except for the fact that it has a memory for storing and checking the security bit and 14 checking circuits for checking the security.

It is constructed in the same way as the embodiment shown in FIG. According to this, the spear bit storage memory 13 has:
/F properties for RAMs 11 and 12 are stored in advance, and when read, RAM], l, and 12 are stored in advance.
Upon receiving the same input address as , the corresponding yariity is read out and given to the ity check circuit 14 .・e I
In the J tee check circuit 14.

A bit selected from the RAMs 11 and 12 representing whether the code is positive or negative and a bit representing whether or not the code is an invalid code are checked.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, 1
By configuring code digit conversion of 0-decimal data using a memory element and a selection function using code commands, the configuration is simpler than conventional logic circuits, and it goes without saying that it is easier to add a check circuit. , the effect obtained is significant in terms of improved economic efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment according to the present invention, FIG. 2 is a block diagram showing the configuration of a second embodiment according to the present invention, and FIG. 3 is a block diagram showing the configuration of a second embodiment according to the present invention. It is a professional diagram showing the configuration of. In the figure, 1, 2, 11.12 are RAM (or R
OM), 3 is a switching circuit, 4 and 5 are flip-flops, 13' is a bit storage memory, and 14 is a parity check circuit. Agent (71:l;) f1 Yosuke Ridogoto Figure 1 Figure 2

Claims (1)

[Claims] In the address corresponding to the code digit represented by a plurality of bits in the 11decimal calculation data, bits representing either positive or negative and whether or not the code digit is an invalid code digit correspond to the plurality of codes. a memory means in which a bit representing a value is stored; and a bit stored in the memory means or corresponding to a specified code of the plurality of codes from among the bits read from the memory means; and selection means for separately extracting a bit representing either pressure or negative and a bit representing whether or not the code digit is an invalid code digit corresponding to the corresponding code. conversion circuit. 2. In the code digit conversion circuit according to claim 1, the memory means is constituted by at least one memory that stores in advance the code digits in correspondence with the code digits, and the selection means is configured to A bit representing either positive or negative read from one memory and a bit representing whether or not it is an invalid code digit are respectively distinguished and received, and a code command is received from among the plurality of codes to select the corresponding one. It is comprised of means for selecting a bit representing either positive or negative and a bit representing whether or not it is an invalid code digit, and further receives a bit representing either positive or negative from the selection means. , a first flip-flop that outputs a code representing whether the corresponding code digit is positive or negative, and receives from the selection means a bit representing whether or not it is an incorrect code digit. A code digit conversion circuit comprising: a second flip-flop that outputs a code indicating whether or not a corresponding code digit is an invalid code digit. 3. In the code digit conversion circuit according to claim 1, the memory means stores in advance bits representing either positive or negative in correspondence with a plurality of codes at addresses corresponding to code digits. It is constituted by a first memory and a second memory that stores in advance a bit indicating whether or not the code digit is an invalid code digit corresponding to a plurality of codes at an address corresponding to the code digit, and the selection means includes: Said 1st o':
and a second memory, which receives a code command from among the plurality of codes and selects a bit representing either positive or negative from the first memory in response to the corresponding code. , comprising means for selecting a bit representing whether or not the code digit is an invalid code digit from the second memory,
Furthermore, a first block 7f receives a bit indicating either positive or negative selected from the first memory by the selection means and outputs a code indicating whether the corresponding code digit is positive or negative. and a second bit receiving the bit indicating whether the corresponding code digit is an invalid code digit selected from the second memory by the selection means and outputting a code indicating whether the corresponding code digit is an invalid code digit. A code digit conversion circuit characterized in that it is equipped with a 7f floating block. 4. In the code digit conversion circuit according to claims 2 and 3, the bit representing either positive or negative and the bit representing whether or not the code digit is an invalid code digit, Bi, 1, for Bi, 1. is pre-stored at an address corresponding to said code digit. Characteristic code digit conversion circuit.