JPS58215135A - Ternary input circuit - Google Patents

Abstract

PURPOSE:To attain low cost, by constituting an inverter having a high circuit threshold voltage with the same channel type MOS transistors(TRs) for extending a manufacturing margin (range) of the threshold voltage of the MOS TRs, and reducing the pattern area of an integrated circuit. CONSTITUTION:The inverter 13 having a high circuit threshold voltage comprising P channel MOS TRs 11, 12 and the inverter 16 having a low circuit threshold voltage comprising N channel MOS TRs 14, 15 are used. That is, in the inverter 13 the P channel TRs 11, 12 are connected in series between a power supply VDD (1st potential supply terminal) and ground (2nd potential supply terminal), a gate of the TR11 is connected to a common input terminal 9, and a gate of the TR12 is grounded. In the inverter 16, N channel TRs 14, 15 are connected in series be tween the power supply VDD and ground, a gate of the TR15 is connected to the input terminal 9 and a gate of the TR14 is connected to the power supply VDD. Thus, the change in the circuit threshold voltage due to the dispersion in the threshold voltage VTH of the MOS TRs is prevented by constituting the inverters 13, 16 with the MOS TRs of the same channel type in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a three-value input circuit suitable for use in an integrated circuit having a complementary MO8 structure.

[Technical background of the invention and its problems]

A conventional three-value input circuit 1 is shown in FIG. This circuit is 1. A voltage/voltage dividing circuit based on resistors R and R, and two inverters with different circuit threshold voltages, namely transistor 1.
, 2, an inverter 6 including transistors 4 and 6, a complementary MOS type NAND circuit 7 and a NOR circuit 8, and a common input terminal 90''H.
It detects three states: ``(A) level, ``L'' (low) level, and open, and transmits the level status of input terminal 9 to the internal circuit through outputs OUT, , OUT. For example, when the power supply voltage vDn is 0.5V, the circuit threshold voltage of the inverter 6 is set to 2. In a three-value input circuit designed with OV, inverter 30 circuit threshold, and lead voltage of 3.0, a 'L' of 0 to 2 Ov or less is applied to input terminal 9.
When the level is input, the output points e and d of inverter 6.3 both become @H'' level, and the outputs 0UT1 and OUT
, Fi becomes “L” level. Next, input 3 to common input terminal 9.
．． When the level is ``H#H#'' between 0 and 5.0■, the output points d and e of inverter 3.6 both become ``L'' level, and the output OUT becomes H'tz-. Next, when the input terminal 9 becomes open, the power supply vn.

2.5V is input to the inverters 3 and 6 by resistors R and R connected in series between the voltage and the ground.

At this time, the inverter 6 to which a voltage of 2.5V higher than the circuit threshold and shoulder voltage was input outputs "L" level, and the inverter 3 to which 285V, which is lower than the circuit threshold and shoulder voltage, was inputted. Outputs H'' level, output OUT, 1l-i
"H", output OUT becomes "L".

However, in the circuit shown in FIG. 1, voltages V, ri, and voltages V? When manufacturing FI with 1.0 to 1.6 V (absolute #), the circuit thread, lead and lead voltages are 2.0 to 1.6 V (absolute #). 6 inverters of Ov, thread of P channel type and N channel type transistor, worst condition of γ1 field voltage VTII VTH
P = 1.0'V, Vtyrs'' 1.6V must be taken into consideration when designing.For example, P-channel type MO
If W/I of S transistor (W is channel width, L channel length) is I O/l O, input type, voltage 2.0
The on-resistance ROM in case (2) is where tOX is the thickness of the oxide film (135, OX), and ξ is the dielectric constant of the oxide film (34, 5X).
10 ”F/Crn) r μ-mobility (μP=20
0ffl/V-seclμN=400calV degree)=
97.81dl Tear, circuit threshold, lead voltage to 2. In order to make it Ov, the N-channel type MO8) transistor is vos 2.
At OV, the on-resistance must be 97.8Ω. At this time, the channel width W of the N-channel type MO8) transistor is calculated from equation (1) = 125X10'CCm3 Similarly, the circuit threshold voltage is 3. OV in/part 3 is the worst condition VTR? of the thread, shield, and shield voltages VTIt of P-channel type and N-channel type transistors. =1.
6V e VTHN=IIOV t Consideration 8. L, Tee installation tf file is required. In this case, if W/Lt to/lo of the N-channel type MO8) transistor is used, then from equation (1), the on-resistance R6N when the input voltage EE is 3°Ov is 48.
9 is set to Ω, and the circuit thread, shield, and shield voltage are set to 3. To make it Ov, change the P-channel type MO8) transistor to Vi!
! At 2.0 V, the on-resistance must be 48.9 Ω. At this time, the W of the P Bouyanel type MO8) transistor
From formula (1), = 500X 10 [m] As mentioned above, WAt of the P-channel transistor of the inverter 6 is 10/10, and W and /'L of the N-channel transistor of the inverter 6 are 125/10. WAf of the P-channel transistor of inverter 3 must be 500/10 + W/L1r of the N-channel transistor: lO/10, and the manufacturing range of the transistor's thread and shoulder voltage is 0.6'/(1, 6V -1,0V = 0.6
v), the channel width W of the P-channel and N-channel type MO8) Lanzostar in the inverter with the higher circuit threshold voltage (inverter 3 side in this case)
Since the ratio of CMO must be increased to 50 times,
This increases the turn area of the 8 integrated circuit, which causes costs and problems.

[Purpose of the invention]

The present invention has been made in view of the above circumstances.
The present invention aims to provide a three-value input circuit that can widen the manufacturing margin (range) of transistor thread, shield, and shield voltages, and reduce the flat turn area of an integrated circuit to reduce costs.

[Summary of the invention]

In order to achieve the above object of the invention, an inverter with a circuit threshold voltage is constructed of two P-channel type MO8) transistors, and one transistor's
Reduce the dimension ratio by using the Tobias effect. In addition, by configuring the inverter with low circuit voltage, shield voltage, and two N-channel type MO8) transistors, and using the pack-tart bias effect of one of the transistors to reduce the dimension ratio, integrated circuits can be Reduce early turn area.

A small inverter is constructed of Mos transistors of the same channel, so that even if the voltage of the transistors changes, the voltage of the transistors does not affect the circuit voltage.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a circuit diagram showing the same embodiment, but since it is an example in which it corresponds to the one in the hzi figure, please refer to the corresponding part.
- The characteristic points will be explained with reference numerals and the explanation will be omitted. %mh in FIG. 2, a circuit formed by p-channel type MO8) transistors 11 and 12, a high threshold voltage inverter 13, and a circuit formed by N-channel type MO8) transistors 14 and 15.

The advantage is that an inverter 16 with low pressure is used. That is, inverter I3, power supply VDD (first potential supply terminal)
P-channel transistors 11 and 12 are connected in series between the terminal and ground (second potential supply terminal), the midpoint d' between them is the output terminal, and the dirt pole of transistor 1 is connected to the common input terminal 9. Then, the gate voltage wLt of transistor I2
Well, ground it. Inverter 16Fi, 'N source VflD and ground are connected in series with KN channel type transistors 14 and 1.5, their intermediate point C' is used as the output terminal, and the gate electrode of transistor 15 is connected to input terminal 9 L7, transistor 14 (Goo) Connect the III pole to the power supply VoDK.

In the circuit of FIG. 2, for example, the power supply vn, ) is -5V, the circuit threshold voltage of the battery 16 is set to 2OV, and the circuit thread, shield voltage of the battery 13 is set to 3°0. Then, since the signal inversion operation of inverters II and 16 corresponds to that of inverter 3.6 in FIG. 1, the circuit operation is exactly the same as that of the circuit in FIG.

The feature of the circuit shown in FIG. 2 is that the inverters 13 and 16' are configured with MOS transistors of the same channel type.

Since the purpose is to prevent the circuit threshold voltage from changing due to variations in the shoulder voltage VTR, the above-mentioned isiper will be explained.

In other words, an inverter? ,? 3. to input terminal 9 at When QV is input, 12 P-channel type transistors and 2.5
V's Pa, Kugut no Iasu (5-2,5=2.5V)
l) Since what is being done is the effective thread,
The field voltage is expressed by the following equation (2).

...(2) However, φM8 is the work function, QllI+ is the surface loading density, and φ
f is the Fermi level, S1 is the linearity rate of silicon, Co t
d 8.85 x 10” '[F/Em], qi,
Cofi is the capacity per unit area, and ND is the substrate concentration. On the other hand, the V when the pack is not biased is...(3), so the IVT when the pack is biased is
FII tD increment AViFi, (2) Equation (3)
The formula 'c difference j, subtracted ru, and O...(4) becomes. Now tox = 13soL ND of N-type substrate: l X I Q"(M', then s V
Most of the Δ on the P channel side of sa = 2.5 V = 0.72 [V] At this time, the thread of the P channel type MO8) transistor.

The field voltage is set to 1. OV, P-channel type MO8) If W/l of the range metal 1 is set to lO/10, the on-resistance of the transformer/resistor 11 is Ω according to equation (1), and the circuit thread and shoulder voltage are set to 3 ．． In order to make it OV, W of transistor 12 is = 16 from formula (1)
．． 4 X 10 Cr] Similarly, inverter 16
In the case of tox = 1350XIP type Zazu Straight concentration NO = 1
= 2.5i/ (D N channel side ΔVTN is (
4) According to formula, it is 0.72V. At this time, N-channel type MO
3) Runnostar Thresh, Ludo car pressure i1. If the W/I of the Ovl transistor 15 is 10/lo, then the on-resistance of the transistor 150 (from the formula 0 is 195.6 Ω, and in order to make the threshold voltage of one circuit 'i 2.OV), the W of the transistor 14 is 16 It becomes ゜4μ.

As mentioned above, compared to the conventional circuit shown in FIG. 1, the W/1. In addition to being able to significantly reduce the voltage, the circuit threshold voltage is not affected even if the voltage of the MOS (MOS) transistor changes (the difference in voltage between the voltage of the same channel on the same chip is This makes it possible to increase the manufacturing margin for thread, shield, and shield voltages (extremely small).

In the above J invention, the N-type substrate and the P-type substrate were explained as having the same concentration, but since a general CMO8 integrated circuit is manufactured by forming a TiN-type substrate (tiN-type substrate) and a KP well (P-well), the P-type substrate is The concentration on the side increases. Therefore, as can be seen from equation (2), the size of the 47 N-channel transistors becomes large.

FIG. 3 shows an inverter section according to another embodiment of the present invention. That is, in the inverter section node 6', transistors 14'+''c are connected in series between the power supply VDD and the ground, the power supply VDD is connected to the gate of the transistor 14', and the gate of the transistor 15' is connected to the gate of the transistor 15'. Connect common input terminal 9 to
The substrate voltage Th of the transistor 14' is connected to the output terminal C.
', and the substrate electrode of the transistor 15' is connected to ground.

The inverter shown in FIG. 3 is constructed by connecting the substrate electrode of the transistor 14' to its own source. −)
N-channel transistor 14 that eliminates bias effects
The inverter 16' is operated at a ratio of ', IS' to eliminate malfunctions caused by an increase in ΔVT due to the pack f-) bias.

The fourth example shows still another embodiment of the present invention. That is, the inverter 1 has transistors Z/', 15'' connected in series between the power supply VDD and ground, the power supply VDD fc connected to the case of the transistor 14, and an inverter 21 interposed between the substrate electrode and the input terminal. The dart of the transistor 11' is connected to the input terminal 9, and the substrate straight electrode is grounded.

In the inverter shown in FIG. 4, when the "H" level is input to the input terminal 9, the P
The type sag straight electrode is brought to the "L" level, and the transistors 14" are biased to each other. When the signal L' is input to the input terminal 9, the N-channel transistor 15'' is turned off, while the P-type substrate electrode of the N-channel transistor 1'' is set to the 1H# level, and the substrate electrode and source 01 points through 1H”
Make it 4. When K is like this, transistor 17'
Since the bias effect increases the shield voltage, the current consumption through transistor 1/ can be reduced, and the W/I of transistor 14 can be reduced due to the
, which can be made smaller than the transistor 14' shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, by configuring the inverter with the same channel type, the circuit voltage and the threshold voltage can be made independent of the changes in the voltage and the voltage of the MOS transistor, thereby increasing the margin of the threshold voltage. be able to. Also, the FET is
When the effective threshold and lead voltage increase, K
Therefore, a large fky□L5 can be realized without increasing the dimension of the transistor, and therefore a three-level long circuit with reduced cost can be provided.

[Brief explanation of the drawing]

Fig. 1 is a conventional three-value input circuit diagram, Fig. 2 is a schematic diagram of one embodiment of the present invention, and Figs. 3 and 4 are circuit diagrams illustrating other embodiments of the present invention. be. 7...NAND circuit, 8...NOR circuit, 9...Common input terminal, 11.12...P channel type MO8) range nut, 13.16...Inverter, 14.16...
・N-channel type MO8) transistor, R...resistance. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4

Claims (4)

[Claims] (1) A circuit threshold formed by the first and second P-channel type MO8) transistors, a first inverter with a high shoulder voltage, and a circuit threshold formed by the first and second N-channel type MO8) transistors. , a second inverter with a low field voltage, and the first inverter. A voltage divider circuit whose intermediate point is connected to the common input terminal of the second inverter, and a complementary MO8 logic circuit that inputs the outputs of each of the inverters and obtains an output according to the three-value input to the common input terminal. A three-value input circuit comprising: (2) The first inverter includes the first inverter between the first potential supply terminal and the second potential supply terminal. A second P-channel type MO8) transistor is connected in series, and the first . 20th page
r-1 of the first P-channel MO8) transistor connected between the first output terminal and the first potential supply terminal with the midpoint of the channel MO8) transistor as the first output terminal;
a second P-channel type M connected between the first output terminal and the second potential supply terminal;
O8) The y-to electrode of the transistor is connected to a second potential supply terminal; the second input is connected between the first potential supply terminal and the second potential supply terminal. ．． A second N-channel type MO8) transistor is connected in series, and the first... Second
The gate electrode of the N-channel type MO8) transistor of the f41, which is connected between the second output terminal and the first potential supply terminal, with the intermediate point of the ON channel type MO8) transistor as the second output terminal. A first potential supply end is connected to the second potential supply end.
The common input terminal is connected to the gate electrode of an N-channel type MO8 transistor connected between the output terminal of the first . The three-value input circuit according to claim 1, characterized in that the substrate electrode of a second N-channel type MO8) Lanzoster is connected to the second potential supply end. (3) The first inverter connects the first and rz P-channel MOS transistors in series between the first potential supply terminal and the second potential supply terminal;
The middle point 1 of the P-channel type MO8 transistor of the first output terminal is connected as the first output terminal between the first output terminal and the potential supply terminal of @l. and connect the gate electrode of a second P-channel type 10S transistor connected between the first output terminal and a potential supply terminal of V,2 to the second potential supply terminal. The second inverter is connected to the first inverter.
potential supply end and a second potential supply end. Between the ends, the first. A second ON channel type MO8) transistor is connected in series, and the first ON channel type MO8) transistor is connected in series. 2nd N-channel # type MO8)
A first potential supply terminal is connected to the date electrode of the first N-channel type MO8) transistor, which is connected between the second output terminal and the first potential supply terminal, with the midpoint of the transistor as the second output terminal. A substrate electrode of the first N-channel type MO8) transistor is connected to the second output terminal, and a second transistor connected between the second output terminal and the second potential (i+; 2ON channel type MO8) transistor case-1
The common input terminal is connected to the m-pole, and the substrate electrode of the second N-channel MO8 transistor is connected to the second potential supply end. Three-value input circuit described in Section 1. (4) The first input terminal has the first potential supply terminal and the second potential supply terminal between the first potential supply terminal and the second potential supply terminal. @2 P-channel type MO8) transistors are connected in series, and the first. The f-
of a second P-channel type MO8) transistor connected between the first output terminal and the second potential supply terminal; -) the electrode is connected to a second potential supply terminal; the second inverter is connected between the first potential supply terminal and the second potential supply terminal; A second ON channel type MO8) transistor is connected in series, and the first ON channel type MO8) transistor is connected in series. The f- ) a first potential supply end is connected to the electrode; a signal inversion means is connected between the substrate electrode of the transistor and the common input terminal; The common input terminal is connected to the f-) electrode of the second N-channel type MO8) transistor connected between the first supply terminals of the second N-channel type MO8) transistor, and the substrate electrode of the second N-channel type MO8) transistor is 2. The three-value input circuit according to claim 1, wherein the three-value input circuit is connected to the potential supply terminal of No. 2.