JPS58215046A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a substrate to be exposed by chipping off at the dicing process by a method wherein the outermost circumferential parts of the four sides of one main surface of a semiconductor chip are made to have structure lowered much more in relation to the main surface of the semiconductor chip. CONSTITUTION:The outermost circumferential parts 11 of the semiconductor chip 7 are lowered much more than the main surface of the chip 7, and clearances 12 generated thereby between a lead frame 8 bonded on a protruding electrode 10 are held in the condition enlarged as much. By forming in structure like this, chipping inferiority is not generated at the dicing process to divide a semiconductor wafer into the respective semiconductor chips, dicing can be attained easily, while etching inferiority of the lead frame 8 connected to the electrode 10 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, particularly a semiconductor integrated circuit manufactured by connecting a lead frame for external electrical connection to a semiconductor chip having protruding electrodes. It is related to the device.

Conventionally, the dicing method used to separate individual semiconductor chips with protruding electrodes for connecting lead frames using thermocompression bonding from a semiconductor substrate has the disadvantage of chipping, in which the periphery of the semiconductor chip is chipped. It has been known for a long time.

In conventional semiconductor integrated circuit devices, the lead frame connected to the protruding electrodes sometimes comes into contact with exposed silicon around the semiconductor chip due to chipping (edge touch failure), causing instability in quality. This defective phenomenon is fatal to semiconductor integrated circuit devices having a large number of protruding electrodes, and is often the cause of significantly lowering the reliability of the device.

The present invention provides a highly reliable semiconductor integrated circuit device in which the above defects are effectively eliminated through simple steps.

The semiconductor integrated circuit device of the present invention prevents the periphery of the semiconductor chip from being chipped during the dicing process and exposes the silicon that is the semiconductor substrate, and also prevents the lead frame connected to the protruding electrodes of the semiconductor chip from making edge contact with the semiconductor substrate. In order to prevent defects from occurring, the semiconductor chip is characterized in that the outermost peripheral portions on the four sides of one main surface of the semiconductor chip have a structure that is lower than the main surface of the semiconductor chip.

The present invention will be explained below using examples.

As shown in Figure 1, it has a dicing line 1 and an insulating film 2.
A semiconductor wafer 3 covered with is prepared.

Next, the active area of the semiconductor chip on this semiconductor wafer (
(not shown) and the surrounding area 5 including the dicing line width 4 are selectively coated with a photoresist film 6 as shown in FIG.

Next, using this photoresist film as a mask, the insulating film 1 and silicon 3 corresponding to the dicing line width 4 and the surrounding area 5 are etched using, for example, a mixed solution of hydrochloric acid and nitric acid, and the photoresist film is etched. After removing the wafer, the surface of the semiconductor wafer is oxidized in an oxidation furnace to obtain a semiconductor strip having the structure shown in FIG. Next, a semiconductor wafer (not shown) for manufacturing purpose is obtained through a diffusion process, an electrode wiring process, and a protruding electrode process.

The wafer marked 1ji formed in this way is pasted onto an epoxy resin using a low heat-melting wax, for example.
Then, each semiconductor chip 7 is diced using a dicer along the dicing line. Thereafter, when the lead frame 8 is attached to the protruding electrode 10 formed on the insulating film 2 via the barrier metal 9 by, for example, thermocompression bonding, the cross section thereof becomes as shown in FIG. As seen in FIG. 4, the outermost peripheral portion 11 of the semiconductor chip 7 is lower than the main surface of the semiconductor chip, thereby lowering the lead e-frame 8 bonded to the protruding electrical finish.
The 12-degree clearance between the two is maintained that much larger.

As explained in detail above, the present invention has a structure in which the inactive region including the dicing line region is thinner than the silicon thickness of the main surface of the semiconductor chip. Dicing can be easily performed without causing chipping defects in the dicing process for separating into chips, and edge touch defects of the lead frame connected to one protruding electrode can be prevented. Thereby, the manufacturing yield and quality of the semiconductor integrated circuit device can be improved and at the same time, the manufacturing cost can be reduced.

[Brief explanation of the drawing]

FIGS. 1 to 4 are cross-sectional views sequentially explaining the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. In the diagram, ■... river dicing line, 2...
...Insulating film, 3...Semiconductor wafer, 4
・Old...Dicing line width, 5...River dicing line and its surrounding area, 6...Photoresist film, 7...Semiconductor chip, 8...-
Node frame, 9...Barrier metal, 1o
. . . mark: protruding electrode; 11: outermost periphery of the semiconductor chip; 12: clearance between the semiconductor chip and the lead-frame. 7.'Rui・Representative Patent Attorney Shinji Uchihara':':””
')'+2 1st flash Z diagram

Claims (1)

[Claims] A semiconductor chip, a protruding electrode formed on its main surface,
A semiconductor integrated circuit device includes a lead frame for external electrical connection whose connection ends are aligned in accordance with the electrode arrangement, and the lead frame is connected to the protruding electrode. A semiconductor integrated circuit device characterized in that the outermost peripheral portions of the four sides of the semiconductor chip have a structure that is lower than the main surface of the semiconductor chip.