JPS5821432B2 - Hand tie souchi - Google Patents
Hand tie souchiInfo
- Publication number
- JPS5821432B2 JPS5821432B2 JP50093407A JP9340775A JPS5821432B2 JP S5821432 B2 JPS5821432 B2 JP S5821432B2 JP 50093407 A JP50093407 A JP 50093407A JP 9340775 A JP9340775 A JP 9340775A JP S5821432 B2 JPS5821432 B2 JP S5821432B2
- Authority
- JP
- Japan
- Prior art keywords
- protrusion
- conductor wiring
- insulating
- insulating substrate
- protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Description
【発明の詳細な説明】
本発明は半導体装置詳しくは半導体素子の電極と外部電
極の接続に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a connection between an electrode of a semiconductor element and an external electrode.
半導体素子と外部電極端子の接続は従来Au線あるいは
AA線を用いたワイヤボンディング法が主流であった。Conventionally, wire bonding methods using Au wires or AA wires have been the mainstream for connecting semiconductor elements and external electrode terminals.
この方法は仲々自動化が困難であり殆んど手作業に頼っ
ていたため、工数が犬であり半導体素子たとえばICの
コスト高の主たる原因の一つであった。This method is difficult to automate and relies mostly on manual work, which requires a significant amount of man-hours and is one of the main causes of high costs for semiconductor devices such as ICs.
ワイヤボンディングを用いない方法としてフリップチッ
プ法がある。There is a flip-chip method as a method that does not use wire bonding.
このフリップチップ法は主として半導体素子側に金属バ
ンブを形成しそれを外部端子と接続する構成を取ってい
た。This flip-chip method mainly involves forming metal bumps on the semiconductor element side and connecting them to external terminals.
従来のフリップチップ法の難点は半導体素子上で種々の
金属を蒸着メッキ、あるいはエツチングなどの処理を行
なっているだめ、工数が多く複雑になり、半導体素子に
損傷を与えるケースがしばしばあシ、また金属バンブの
高さを多く得ることは困難であった。The disadvantage of the conventional flip-chip method is that various metals are vapor-deposited, plated, etched, etc. on the semiconductor device, which requires a large number of steps and is complicated, and often damages the semiconductor device. It was difficult to obtain a large height of metal bumps.
本発明は、半導体素子上の電極と基板上の導体配線の接
続を容易でかつ信頼性の高いものとする半導体装置を提
供するもので、以上本発明の実施例にかかる半導体装置
を提供するもので、以上本発明の実施例にかかる半導体
装置を図面とともに詳細に説明する。The present invention provides a semiconductor device that allows easy and reliable connection between electrodes on a semiconductor element and conductor wiring on a substrate, and provides semiconductor devices according to embodiments of the present invention. Now, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.
第1図において、1は半導体集積回路素子、2は酸化膜
、3はAA,Coなどよりなり高さ10μ、直径50〜
150μ程度の金属突起物、4は導体配線、5はガラス
および樹脂フィルムなどよりなる耐熱性絶縁基板を示す
ものである。In FIG. 1, 1 is a semiconductor integrated circuit element, 2 is an oxide film, and 3 is made of AA, Co, etc., with a height of 10 μm and a diameter of 50 μm.
A metal protrusion of about 150 μm is shown, 4 is a conductor wiring, and 5 is a heat-resistant insulating substrate made of glass, resin film, or the like.
この構造の装置の製造方法を説明すると、耐熱性基板5
の一生面には化学的エツチング、プラズマエッチラグあ
るいは機械的加工法などによ勺、絶縁基板5本体よシな
る高さ10μ〜50μ、直径50〜150μ程度の突起
6を形成する。To explain the manufacturing method of the device with this structure, the heat-resistant substrate 5
A protrusion 6 having a height of about 10 to 50 microns and a diameter of about 50 to 150 microns, which is the same as the main body of the insulating substrate 5, is formed on the entire surface of the insulating substrate 5 by chemical etching, plasma etching, or mechanical processing.
なお絶縁基板5および突起物6の材料としては、アルミ
ナ、ポリイミド樹脂などの耐熱性樹脂、ガラスなどを用
いる。Note that as materials for the insulating substrate 5 and the protrusions 6, heat-resistant resin such as alumina and polyimide resin, glass, etc. are used.
次に基板5上の突起6を有する亀にAA、Cu、Auな
どの蒸着を行ない突起6c上面を含むように導体配線4
の形成を行なう。Next, AA, Cu, Au, etc. are vapor-deposited on the surface of the substrate 5 having the protrusion 6, and the conductor wiring 4 is deposited so as to include the upper surface of the protrusion 6c.
formation.
次に絶縁基板5の本体で形成した突起6の上面の導体配
線4上のみに選択的にAA、Cuなどでメッキを行ない
高さ10μで直径50〜150μ程度の突起物3を形成
する。Next, only the conductor wiring 4 on the upper surface of the protrusion 6 formed on the main body of the insulating substrate 5 is selectively plated with AA, Cu, etc. to form a protrusion 3 having a height of 10 .mu.m and a diameter of about 50 to 150 .mu.m.
ここで選択的にメッキを形成する方法としては配線全体
にメッキを流こし、その後選択エッチを行なう方法、あ
るいは無電界メッキを選択的にあらかじめ蒸着した部分
にのみ行なう方法などがある。Here, methods for selectively forming plating include a method in which plating is spread over the entire wiring and then selective etching is performed, or a method in which electroless plating is selectively performed only on previously vapor-deposited portions.
次に素子1の電極を有する面を導体配線4に面して設置
し、素子1の電極と金属突起物3を超音波あるいは熱圧
着などにより電気的に接続する。Next, the surface of the element 1 having the electrodes is placed facing the conductor wiring 4, and the electrodes of the element 1 and the metal protrusions 3 are electrically connected by ultrasonic waves, thermocompression bonding, or the like.
こうして第1図の構造の素子が完成する。In this way, the element having the structure shown in FIG. 1 is completed.
なお、突起物3はボンディングの方法によっては必ずし
も必要とせず、直接突起6上の導体配線と素子上の電極
とを接続してもよい。Note that the protrusion 3 is not necessarily required depending on the bonding method, and the conductor wiring on the protrusion 6 and the electrode on the element may be directly connected.
以上の装置によれば、金属突起を用いる場合に比べ突起
6と基板5が一体化されているため、強度的に安定でか
つ突起6の製作工程も比較的簡単となシ、突起6間の間
隔をいくら小さくしても突起6間の絶縁を保つことがで
き、ショートの恐れが全くなく、突起物3および突起6
上の導体配線をきわめて小さくでき高密度な組立が可能
となるとともに、素子1の表面の損傷、基板5と素子1
の接触をなくすことができる。According to the above device, since the protrusions 6 and the substrate 5 are integrated compared to the case where metal protrusions are used, the strength is stable and the manufacturing process of the protrusions 6 is relatively simple. No matter how small the distance between the protrusions 6 is, insulation between the protrusions 6 can be maintained, there is no risk of short-circuiting, and the protrusions 3 and 6
The upper conductor wiring can be made extremely small and high-density assembly is possible.
contact can be eliminated.
つぎに本発明の他の実施例の半導体装置を第2図ととも
に説明する。Next, a semiconductor device according to another embodiment of the present invention will be explained with reference to FIG.
第2図において、第1図と同様のものには同一番号を付
している。In FIG. 2, parts similar to those in FIG. 1 are given the same numbers.
10は絶縁被膜であシ突起物6の一部および導体配線4
を被覆している。10 is an insulating coating that covers a part of the protrusion 6 and the conductor wiring 4.
is covered.
この絶縁被膜10はフッ素系の樹脂あるいはポリイミド
樹脂、CVD法によるS r o2膜などが用いられる
。This insulating coating 10 is made of fluorine-based resin, polyimide resin, S r o 2 film produced by CVD method, or the like.
この被膜10を形成する工程は導体配線4を形成した後
に行なうがあるいは金属突起3を形成したる後に行なう
。The step of forming this film 10 is performed after the conductor wiring 4 is formed, or after the metal protrusion 3 is formed.
前者の場合は特に被膜10が電気メッキの突起3の形成
時マスク効果の働らきを行なうので有利である。The former case is particularly advantageous since the coating 10 acts as a mask during the formation of the electroplated projections 3.
この実施例の装置によれば、導体が配線4、絶縁被膜1
0で被覆されているため、導体配線4間どうしの短絡あ
るいはリーク現象が起りにくい。According to the device of this embodiment, the conductor is the wiring 4 and the insulating coating 1.
Since the conductor wirings 4 are coated with zero, short circuits or leakage phenomena between the conductor wirings 4 are less likely to occur.
また、工程で取扱う際、ピンセットなどの工具により導
体配線4に機械的に傷をつける事が著るしく減少する。Furthermore, during handling in the process, mechanical damage to the conductor wiring 4 by tools such as tweezers is significantly reduced.
さらにこの構造によれば絶縁被膜10上に更に第2の導
体配線を施こして多層配線構造を得ることが可能となる
。Furthermore, according to this structure, it is possible to further provide a second conductor wiring on the insulating coating 10 to obtain a multilayer wiring structure.
デ さらに、本発明のさらに他の実施例の半導体装置
を第3図とともに説明する。Furthermore, a semiconductor device according to another embodiment of the present invention will be described with reference to FIG.
第3図において、第1,2図と同一のものには同一番号
を付している。In FIG. 3, the same parts as in FIGS. 1 and 2 are given the same numbers.
20はガラス及び樹脂フィルムなどの耐熱性絶縁基板5
と膨張係数及び化学的、物理的エッチ0ングレートなど
の異なる高さ10〜50μ、直径50〜150μ程度の
絶縁突起物を示すものである。20 is a heat-resistant insulating substrate 5 made of glass, resin film, etc.
It shows insulating protrusions with a height of 10 to 50 μm and a diameter of 50 to 150 μm, which have different expansion coefficients and chemical and physical etching rates.
この装置の製造方法を説明すると、まず最初に耐熱性絶
縁基板5の一生面に、絶縁基板5と膨張5係数及び化学
的、物理的エツチングレートなどの異なる絶縁物を塗布
し、不要部分を化学的エツチングなどを行いこの絶縁物
で高さ10〜50μ及び直径50〜150μ程度の上記
突起物20を形成する。To explain the manufacturing method of this device, first, an insulator having a different expansion coefficient and chemical and physical etching rate from the insulating substrate 5 is coated on the whole surface of the heat-resistant insulating substrate 5, and unnecessary parts are removed by chemical etching. Targeted etching or the like is performed to form the protrusion 20 with a height of 10 to 50 .mu.m and a diameter of 50 to 150 .mu.m using this insulating material.
ここで絶縁基板5上に膨張係数及び化学9的、物理的エ
ツチングレートの異なる絶縁物を塗布するのに3つの主
たる理由がある。There are three main reasons why insulators having different expansion coefficients and chemical and physical etching rates are coated on the insulating substrate 5.
第1に化学的、物理的エツチングレートの違いから、絶
縁物で形成した突起物20の高さを一定にすることがで
きるためである。First, because of the difference in chemical and physical etching rates, the height of the protrusion 20 formed of an insulating material can be made constant.
5 第2に、例えば絶縁基板5をガラスとし突起物20
をガラスとシリコンの中間的な膨張係数をもつ軟らかく
て可とり件のある材料ポリイシド樹脂、テフロン樹脂、
あるいはシリコーン樹脂などを用いれば多少の温度変化
が生じても、絶縁基板5とノ突起物20が緩衝しガラス
のクラック及び損傷などを防ぎ信頼性を高めるためであ
る。5 Second, for example, if the insulating substrate 5 is made of glass, the protrusions 20
Soft and flexible materials with an expansion coefficient intermediate between glass and silicone such as polyide resin, Teflon resin,
Alternatively, if silicone resin or the like is used, even if a slight temperature change occurs, the insulating substrate 5 and the protrusions 20 will buffer the glass, preventing cracks and damage to the glass, and increasing reliability.
第3に、化学的、物理的エツチングレートが異なること
により、絶縁物で形成した突起物20の高さを最初に塗
布する絶縁物の層の厚さによって1容易にきめることが
できるためである。Thirdly, due to the difference in chemical and physical etching rates, the height of the protrusions 20 formed of an insulating material can be easily determined by the thickness of the first layer of insulating material applied. .
さて、次に絶縁基板5上の突起物20を有する面にAA
、Cuなどで蒸着を行い突起物20上面を含み導体配線
4を形成する。Now, next, AA is applied to the surface of the insulating substrate 5 having the protrusion 20.
, Cu, etc. are deposited to form the conductor wiring 4 including the upper surface of the protrusion 20.
次に突起物20上面の導体配線4上のみに、シAA、C
uなどでメッキを行い高さ10μ、直径50〜150μ
程度の金属突起物3を形成する。Next, apply wires AA and C only on the conductor wiring 4 on the top surface of the protrusion 20.
Plated with u etc. to a height of 10μ and a diameter of 50 to 150μ.
A metal protrusion 3 of about 100 mL is formed.
この突起物3はボンディング方法によっては必らずしも
必要としない。This protrusion 3 is not necessarily required depending on the bonding method.
最後に、素子1の電極を有する面を導体配線4に面して
設置し、素子1の電極と金属突起物3を超音波あるいは
熱圧着などによシミ気的に接続する。Finally, the surface of the element 1 having the electrodes is placed facing the conductor wiring 4, and the electrodes of the element 1 and the metal protrusions 3 are connected airtightly by ultrasonic waves, thermocompression bonding, or the like.
この第3図の装置は耐熱性絶縁基板5上に形成が容易な
絶縁突起物20で必要な高さを形成しているため、金属
突起物3の高さはわずかでよい。In the device shown in FIG. 3, the required height is formed by the easily formed insulating projections 20 on the heat-resistant insulating substrate 5, so the height of the metal projections 3 may be small.
また、耐熱性絶縁基板5と絶縁突起物20との膨張係数
及び化学的、物理的エツチングレート等が異なることに
よシ、前述したごとく絶縁突起物20の高さを最初に塗
布する絶縁物の層の厚さによってきめることができ一定
にすることができるとともに、突起物20の緩衝作用に
よシ温度変化による損傷を防ぎ信頼性を高めることがで
きる。Furthermore, since the heat-resistant insulating substrate 5 and the insulating protrusions 20 have different expansion coefficients, chemical and physical etching rates, etc., the height of the insulating protrusions 20 may be different from that of the insulating material to be applied first, as described above. The thickness of the layer can be determined and kept constant, and the buffering effect of the projections 20 can prevent damage due to temperature changes and improve reliability.
以上のような本発明の半導体装置は、半導体素子と基板
上の相互配線とを信頼性良く、容易に高密度に行うこと
ができ、半導体装置組立工程においてすぐれた効果を奏
するものである。The semiconductor device of the present invention as described above enables interconnections between the semiconductor element and the substrate to be easily and reliably formed at high density, and exhibits excellent effects in the semiconductor device assembly process.
第し2,3図はそれぞれ本発明の実施例にかかる半導体
装置の構造断面図である。
1・・・・・・半導体集積回路素子、2・・・・・・酸
化膜、3・・・・・・金属突起物、4・・・・・・導体
配線、5・・・・・・耐熱性絶縁基板、6・・・・・・
突起、10・・・・・・絶縁被膜、20・・・・・・絶
縁突起物。2 and 3 are structural sectional views of semiconductor devices according to embodiments of the present invention, respectively. DESCRIPTION OF SYMBOLS 1... Semiconductor integrated circuit element, 2... Oxide film, 3... Metal protrusion, 4... Conductor wiring, 5... Heat-resistant insulating substrate, 6...
Projection, 10... Insulating coating, 20... Insulating protrusion.
Claims (1)
なる突起と導体配線を形成し、さらに該絶縁上記突起上
に設置された金属層により、上記導体配線と上記導体配
線に面して設置された半導体素子電極とを電気的に接続
したことを特徴とする半導体装置。 2 上記導体配線を絶縁性被膜で覆ったことを特徴とす
る特許 体装置。 3 耐熱性絶縁基板上にこの絶縁基板とは異なる絶縁性
突起物を形成し、上記絶縁基板上に形成された導体配線
の一部を前記突起物の頂上部にまで延設し、かつ上記絶
縁性突起物の頂上部の導体配線上に被着形成された金属
層と上記絶縁基板に面して設置された半導体素子上の電
極を接続したことを特徴とする半導体装置。[Scope of Claims] 1. A protrusion and a conductor wiring are formed on one main surface of a heat-resistant insulating substrate, and the conductor wiring is further formed by a metal layer placed on the insulating protrusion. and a semiconductor element electrode placed facing the conductor wiring, which are electrically connected to each other. 2. A patented device characterized in that the conductor wiring described above is covered with an insulating film. 3. An insulating protrusion different from the insulating substrate is formed on a heat-resistant insulating substrate, a part of the conductor wiring formed on the insulating substrate is extended to the top of the protrusion, and the insulating 1. A semiconductor device, characterized in that a metal layer formed on a conductor wiring at the top of a sexual protrusion is connected to an electrode on a semiconductor element placed facing the insulating substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50093407A JPS5821432B2 (en) | 1975-07-30 | 1975-07-30 | Hand tie souchi |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50093407A JPS5821432B2 (en) | 1975-07-30 | 1975-07-30 | Hand tie souchi |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5216978A JPS5216978A (en) | 1977-02-08 |
JPS5821432B2 true JPS5821432B2 (en) | 1983-04-30 |
Family
ID=14081433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50093407A Expired JPS5821432B2 (en) | 1975-07-30 | 1975-07-30 | Hand tie souchi |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5821432B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6448437A (en) * | 1987-08-19 | 1989-02-22 | Oki Electric Ind Co Ltd | Electrode structure |
JP2008039629A (en) * | 2006-08-08 | 2008-02-21 | Kawasaki Heavy Ind Ltd | Ultrasonic flaw detector and ultrasonic flaw detection method using it |
-
1975
- 1975-07-30 JP JP50093407A patent/JPS5821432B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5216978A (en) | 1977-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3952404A (en) | Beam lead formation method | |
US4784972A (en) | Method of joining beam leads with projections to device electrodes | |
US4486945A (en) | Method of manufacturing semiconductor device with plated bump | |
US4182781A (en) | Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating | |
JP2526007B2 (en) | Structures and methods for forming electrical interconnections to semiconductor chips | |
US6307261B1 (en) | Method for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device | |
JP2002134658A (en) | Semiconductor device and its manufacturing method | |
JPH0357618B2 (en) | ||
JPH05251455A (en) | Semiconductor device | |
JP2622156B2 (en) | Contact method and structure for integrated circuit pads | |
JPS60134442A (en) | Semiconductor device | |
JPS5821432B2 (en) | Hand tie souchi | |
JPS61214444A (en) | Semiconductor device | |
JPS59229850A (en) | Semiconductor device | |
JPH0714028B2 (en) | Method for manufacturing three-dimensional semiconductor device | |
JPH0555228A (en) | Semiconductor device | |
JPH07183304A (en) | Manufacture of semiconductor device | |
JPH0697663B2 (en) | Method for manufacturing semiconductor device | |
JP2721580B2 (en) | Method for manufacturing semiconductor device | |
GB2074793A (en) | Thin film circuit assembly | |
JPS6149452A (en) | Semiconductor element | |
JPH02168640A (en) | Connection structure between different substrates | |
JPH07240434A (en) | Bump electrode and its manufacture | |
JPH03190240A (en) | Manufacture of semiconductor device | |
JPS61272941A (en) | Bonding process of semiconductor substrate |