JPS58212129A - Manufacture of amorphous semiconductor film - Google Patents

Manufacture of amorphous semiconductor film

Info

Publication number
JPS58212129A
JPS58212129A JP57095543A JP9554382A JPS58212129A JP S58212129 A JPS58212129 A JP S58212129A JP 57095543 A JP57095543 A JP 57095543A JP 9554382 A JP9554382 A JP 9554382A JP S58212129 A JPS58212129 A JP S58212129A
Authority
JP
Japan
Prior art keywords
cylindrical
plasma
electrode
metal mesh
cylindrical metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57095543A
Other languages
Japanese (ja)
Inventor
Shigeru Minomura
箕村 茂
Kazuhiko Tsuji
和彦 辻
Takashi Hiraga
隆 平賀
Michio Nagasaka
道雄 長阪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Anelva Corp
Original Assignee
Canon Anelva Corp
Anelva Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Anelva Corp, Anelva Corp filed Critical Canon Anelva Corp
Priority to JP57095543A priority Critical patent/JPS58212129A/en
Publication of JPS58212129A publication Critical patent/JPS58212129A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02425Conductive materials, e.g. metallic silicides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To obtain the amorphous semiconductor films without exposing directly substrates to plasma by a method wherein a space to generate glow discharge plasma is limited in the space between a cylindrical high-frequency applying electrode and a cylindrical metal mesh using the cylindrical metal mesh. CONSTITUTION:The device consists of the cylindrical high-frequency applying electrode 14, a cylindrical substrate setting electrode 17, the cylindrical metal mesh 20, etc. At this case, electrons and ions in plasma do not reach the substrates 8 being shielded, and the films are stacked mainly by neutral radicals, molecules and atoms passed through the mesh. Therefore even when making electric power is enlarged for increase of the film stacking speed or for increase of doping yield, generation of structural defects according to the collision of charged particles can be suppressed low, and a favorable result for improvement of film quality can be obtained. The effect thereof can be attained by holding the cylindrical metal mesh 20 at ground potential. The cylindrical substrate setting electrode 17 is in the electrically floating condition, while the same effect can be obtained even when it is held at ground potential, and moreover, even when a shielding plate is not used, discharge is not generated between the cylindrical high-frequency applying electrode 14 and the upper and lower wall faces of a vacuum chamber 1, and plasma being in the extremely uniform condition can be generated.

Description

【発明の詳細な説明】 本発明はグロー放電分解法によるアモルファス半導体膜
の製造方法の改良に−するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to an improvement in a method for manufacturing an amorphous semiconductor film using a glow discharge decomposition method.

第1図は、従来のアモルファス半導体膜の一般的製造方
法を説明するための図で、平行平板容量結合型グロー放
電装置の模式図である。図において、lは真空室、2は
真空排気系、3は反応ガス供給系、4は高周波印加電極
、5はシールド板、6は絶縁材、7は基板設置電極、8
は基板、9は高周波電源を示している◎通常、高周波印
加11極4には反応ガスを真空室l内に均等に導入する
ため多数の細孔が芽けられておル、対向する基板設置電
極7には基板加熱機構が具備され、接地電位となってい
る。従来のアモルファス半導体膜の製造は、高周波印加
電極と基板設置電極の間で発生したグロー放電プラズマ
によシ基板8上に膜を堆積するのが一般的な方法であっ
た0上記のような従来の製造方法は簡便ではあるが、次
のような問題点がある。
FIG. 1 is a diagram for explaining a conventional general manufacturing method of an amorphous semiconductor film, and is a schematic diagram of a parallel plate capacitively coupled glow discharge device. In the figure, l is a vacuum chamber, 2 is an evacuation system, 3 is a reaction gas supply system, 4 is a high frequency application electrode, 5 is a shield plate, 6 is an insulating material, 7 is an electrode installed on the substrate, 8
9 indicates the substrate, and 9 indicates the high frequency power supply. ◎Usually, the high frequency application 11 pole 4 has many pores in order to introduce the reaction gas evenly into the vacuum chamber l, and the opposing substrate is installed. The electrode 7 is equipped with a substrate heating mechanism and is at ground potential. The conventional method for producing an amorphous semiconductor film was to deposit the film on the substrate 8 using glow discharge plasma generated between a high frequency application electrode and a substrate mounting electrode. Although the manufacturing method is simple, it has the following problems.

(1)基板は@接プラズマに曝されるためアモルファス
半導体膜はその堆積過程においてプラズマ中の電子やイ
オンの衝61kf受け、ダングリングボンド、ボイドt
siH1結合などアモルファス半導体に好ましくない構
造欠陥の密匿を大きくシ、その結果、半導体緒特性を低
下させる原因のひとつとなっている・ (2)通常、真空室はステンレス等の金属材料より構成
されているが、真空室内面と高周波印加1極の間で不必
要な放電を防止するため接地電位とされたシールド板が
設置される。
(1) Since the substrate is exposed to plasma, the amorphous semiconductor film is exposed to 61 kf of electrons and ions in the plasma during the deposition process, causing dangling bonds and voids.
It largely hides structural defects that are undesirable for amorphous semiconductors, such as siH1 bonds, and is one of the causes of deterioration of semiconductor properties. (2) Normally, vacuum chambers are made of metal materials such as stainless steel. However, a shield plate at ground potential is installed between the inside of the vacuum chamber and one high-frequency application pole to prevent unnecessary discharge.

しかしながら、ガス圧力や投入された高周波電力等の条
件によシシールド板と高周波印加1極の間で放電が発生
しプラズマの中心部分と外周部分とでプラズマの性質に
差異が生じる。これが、基板設置電極の位置により膜堆
積速度や膜の性質が不均一となる原因となっている。
However, depending on conditions such as the gas pressure and the applied high-frequency power, discharge occurs between the shield plate and one high-frequency application pole, resulting in a difference in plasma properties between the central part and the outer peripheral part of the plasma. This causes the film deposition rate and film properties to be non-uniform depending on the position of the electrode placed on the substrate.

(3)第1図によるような製造方法では、グロー放電プ
ラズマは平行平板状二極の間で発生されるので膜堆積面
は単一の平面に限定され、@置の占有面積が処理能力の
点で有効に利用されていない。
(3) In the manufacturing method shown in Fig. 1, the glow discharge plasma is generated between two parallel plate-like poles, so the film deposition surface is limited to a single plane, and the area occupied by the @ position exceeds the processing capacity. It is not used effectively in many ways.

本発明は以上のような問題点に鑑みて行なわれたもので
あ′す、本発明によればグロー放電分解法、i(1 によ石アモルファス半導体膜の製造において、円筒状基
板設置電極内壁面に基板を設置するとともに、この円筒
状基板設置電極の内部に同軸状に円筒状の金属メツシュ
と高周波印加電極を配置し、グロー放電空間と基板が位
置する膜堆積空間を分離するアモルファス半導体膜の製
造方法が得られる。
The present invention has been made in view of the above-mentioned problems.According to the present invention, a glow discharge decomposition method, i (1), is used in the production of an amorphous semiconductor film using a cylindrical substrate installed in an electrode. A substrate is installed on the wall surface, and a cylindrical metal mesh and a high frequency application electrode are coaxially arranged inside this cylindrical substrate-installed electrode, and an amorphous semiconductor film is formed to separate the glow discharge space and the film deposition space where the substrate is located. A manufacturing method is obtained.

以下に実施例を図面により説明する。Examples will be described below with reference to the drawings.

第2図は本発明による方法f:笑施するための装置の一
例である0図において、14は円筒状高周波印加’ll
t&、17は円筒状基板設置電極、20は円筒状金属メ
ツシュである。他の符号は!1図において説明したもの
と同一あるいは同一機能部分を示す。以下、第2図を用
いて本発明による製造方法の%敵を説明する。
FIG. 2 shows an example of a device for applying method f according to the present invention. In FIG.
t&, 17 is a cylindrical substrate installed electrode, and 20 is a cylindrical metal mesh. Other signs! 1 shows the same or identical functional parts as those explained in FIG. Hereinafter, the efficiency of the manufacturing method according to the present invention will be explained using FIG.

本発明の特徴は円筒状金属メツシュ20を用いて、グロ
ー放電プラズマの発生する空間を円筒状高周波印加電極
14と円筒状金属メツシュ20の間に制限し、基板8を
プラズマに直接曝すことなくアモルファス半導き声を製
造する仁とにある。
The feature of the present invention is to use the cylindrical metal mesh 20 to limit the space in which glow discharge plasma is generated between the cylindrical high-frequency application electrode 14 and the cylindrical metal mesh 20, thereby eliminating the need to directly expose the substrate 8 to plasma. It is with Jin who produces a semi-guiding voice.

この方法によれば、プラズマ中の電子およびイオンは遮
蔽されて基板8に達せず、主としてメ、シェを通過した
中性のラジカル、分子および原子により膜が堆積される
。このため膜堆積速度の増大あるいはドーピング収率増
大のために投入高周波電力を大きくしても荷電粒子の衝
突による構造欠陥の発生を低くおさえることができ膜質
改善に好ましい結果となる。この効果は円筒状金属メツ
シュ20を接地電位に保つことによシ達成できる。
According to this method, electrons and ions in the plasma are blocked and do not reach the substrate 8, and the film is deposited mainly by neutral radicals, molecules, and atoms that have passed through the plasma. Therefore, even if the input high-frequency power is increased in order to increase the film deposition rate or increase the doping yield, the occurrence of structural defects due to collisions of charged particles can be suppressed to a low level, resulting in a favorable result for improving film quality. This effect can be achieved by keeping the cylindrical metal mesh 20 at ground potential.

また、第2図においては円筒状基板設置電極17は電気
的に70−ティング状態になっているが、接地電位とし
ても同僚の効果が得られ、プラズマ発生空間と膜堆積空
間を分離する本発明め基本的特徴に関わるものではない
In addition, although the cylindrical substrate installed electrode 17 is electrically in a 70° state in FIG. 2, the same effect can be obtained even if it is at ground potential, and the present invention separates the plasma generation space and the film deposition space. It is not related to basic characteristics.

また、本発明によれば、シールド板を用いずとも円筒状
高周波印加電極14と真空室lの上下壁面との間で放電
は発生せず、きわめて均一な状態のプラズマを発生せし
めることができる。その結果、円筒状基板接地電極17
の広い範囲にわたって膜堆積速度や膜質の均一性の向上
を図ることができる。
Furthermore, according to the present invention, even without using a shield plate, no discharge occurs between the cylindrical high-frequency application electrode 14 and the upper and lower wall surfaces of the vacuum chamber 1, and extremely uniform plasma can be generated. As a result, the cylindrical substrate ground electrode 17
It is possible to improve the film deposition rate and the uniformity of film quality over a wide range.

さらに、上記の特徴に加えて本発明による方法でアモル
ファス半導体を製造する場合、発生するプラズマの状態
が第1図に示し九通常の平行平板容量結合型グ四−放i
i、 t: sによるものよりアモルファス半導体を製
造するものに好ましいものであり、これが本発明の大き
な特徴となりていること    ゛具体的結果をもって
説明する。
Furthermore, in addition to the above features, when manufacturing an amorphous semiconductor by the method according to the present invention, the state of the generated plasma is as shown in FIG.
i, t: These are more preferable for manufacturing amorphous semiconductors than those based on s, and this is a major feature of the present invention. This will be explained with specific results.

プラズマの状態を知るのに最も有効かつW8便な手段は
プラズマ発光分析である。第3図は第1図で説明した従
来の方法によりアモルファスシリコン膜t−製造する場
合に観測される発行スペクトルの一例である0第3図は
原料ガスをシラン(SiH,)。
The most effective and convenient means for determining the state of plasma is plasma emission analysis. FIG. 3 shows an example of the emission spectrum observed when producing an amorphous silicon film by the conventional method explained in FIG.

高周波印加1.極4および基板設置rI電極7をφ20
0朋。
High frequency application 1. The pole 4 and the substrate installed rI electrode 7 are φ20
0 friends.

電極間隔を30朋、高周波1.源9の周波数’ik 1
3.56MHzs他のパラメータは図中に示した条件で
得られたものであシ、平行平板容量結合型グロー放電で
観測されるシランプラズマの発光スペクトルの典型的な
例である。第4図は第2図で説明した本発明によってア
モルファスシリコン膜t−a造する場合に観測されたシ
ランプラズマの発光スペクトルの一例である。
The electrode spacing was 30 mm, and the high frequency was 1. Frequency of source 9 'ik 1
The other parameters were obtained under the conditions shown in the figure and are a typical example of the emission spectrum of silane plasma observed in a parallel plate capacitively coupled glow discharge. FIG. 4 is an example of the emission spectrum of silane plasma observed when forming an amorphous silicon film t-a according to the present invention explained in FIG.

第4図は第2図における装置構成襞素を円筒状基板設置
電極17はφ220趨×450朋1円筒状金メツシュ2
0はφ200朋×450朋1円筒状高周波印加1.極1
4をφ140111#lX45011!III  高周
波電源90周波数!t13.56MHzとし、他のパラ
メータは図中に示した条件で得られたものである。プラ
ズマ発光スペクトルの微細構造は装置の構造などのパラ
メータにより影曽を受けるため、上記の如くプラズマ発
生条件を明確に示したが、装−の規倶に変更があっても
第4図の如きスペクトルは再現できるので基本構成が同
じであれば上記の設定条件はX発明に何らの制限を加え
るものではないO シランプラズマの発光スペクトルには第3図に示した例
の如く通常、多数の線スペクトルが現われるが、膜質と
強い相関性をもつものは414朋の発光種SiHによる
ものと656朋の発光稙Hによるものである。すなわち
、sLHとHのスペクトル強度比(H)/C3tH)が
小さい案件下において、膜中のSiH,結合のVB度が
低い投置のアモルファスシリコン族が製造されることが
経験則として知られている。本発明の製造方法において
は第4図の例の如く、発光asiHによる発光強度は充
分強いにもかかわらず発光種Hの発光種Hの発光強度は
測定不可能となるほど微弱である。このため[H)/[
5iH)がきわめて小さな状況下で腺の堆積が可能であ
る。このような状況下で製造されたアモルファスシリコ
ン膜の性質は以下に述べる如く非常に良好である@すな
わち、基板温度200〜250℃で堆積されたアモルフ
ァスシリコン全赤外分光法で分析した結果、5iH1結
合による210〇1 譚  の吸収はほぼ完全に消滅していた。また、これら
のアモルファスシリコン族の暗電気伝導皮は約lXl0
−”Ω−”m−”、光照射下の電気伝導皮は約3×lθ
 Ω 国  と良好な値を示した。
Fig. 4 shows the device configuration in Fig. 2, and the cylindrical substrate installed electrode 17 has a diameter of 220 mm x 450 mm, 1 cylindrical gold mesh, 2
0 is φ200 mm x 450 mm 1 cylindrical high frequency application 1. pole 1
4 to φ140111#lX45011! III High frequency power supply 90 frequencies! t13.56MHz, and other parameters were obtained under the conditions shown in the figure. Since the fine structure of the plasma emission spectrum is affected by parameters such as the structure of the device, the plasma generation conditions are clearly shown above, but even if the specifications of the device are changed, the spectrum as shown in Figure 4 will not change. can be reproduced, so as long as the basic configuration is the same, the above setting conditions do not impose any restrictions on the invention appears, but those that have a strong correlation with the film quality are those due to the luminescent species SiH in 414 Ho and the luminescent species H in 656 Ho. In other words, it is known as a rule of thumb that in cases where the spectral intensity ratio (H)/C3tH of sLH and H is small, an amorphous silicon group with a low degree of VB of SiH and bonding in the film is produced. There is. In the manufacturing method of the present invention, as shown in the example shown in FIG. 4, although the luminescence intensity of the luminescent species H is sufficiently strong, the luminescence intensity of the luminescent species H is so weak that it cannot be measured. For this reason [H)/[
Deposition of glands is possible under conditions where 5iH) is extremely small. The properties of the amorphous silicon film produced under these conditions are very good as described below. The absorption of 21001 Tan due to the combination had almost completely disappeared. In addition, the dark electrically conductive skin of these amorphous silicon groups is about lXl0
−”Ω−”m−”, the electrical conductivity skin under light irradiation is approximately 3×lθ
Ω country showed a good value.

さらに、膜の分布も該円筒状基板設置を極7−aの内壁
面積の80%で±5チ以内であり、通常の平行平板容量
結合型グロー放電装置によるものが70チで±10%程
度で゛あるのに比較して大幅に改善されたことも判る。
Furthermore, the distribution of the film is within ±5 inches at 80% of the inner wall area of pole 7-a when the cylindrical substrate is installed, and about ±10% at 70 inches when using a normal parallel plate capacitively coupled glow discharge device. It can also be seen that there has been a significant improvement compared to the previous version.

以上、実施例により詳細に説明したように本発明は新し
い着想と精密な分析にもとづくものであり、アモルファ
ス半導体膜の製造において膜質および生産性の向上に実
用価11大なる方法を提供するものである。
As explained above in detail using the examples, the present invention is based on a new idea and precise analysis, and provides a method with 11 great practical values for improving film quality and productivity in the production of amorphous semiconductor films. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の製造方法を説明するための図、第2図は
不発明に用いる製造装置を示す図、第3図は従来の製造
方法において観測される発光スペクトルの1例、第4図
は第2図の本発明の場合のシランプラズマの発光スペク
トルの1例でよ−1・・・・・・真空室、7・・・・・
・基板膜#w極、8°・団°基板、14・・・・・・円
筒状高周波印加電極、17・・・・・・円筒状基板設置
電極、20・・・・・・円筒状金属メツシュ。 l    −・I ℃。
Figure 1 is a diagram for explaining the conventional manufacturing method, Figure 2 is a diagram showing the manufacturing apparatus used in the invention, Figure 3 is an example of an emission spectrum observed in the conventional manufacturing method, and Figure 4 is an example of the emission spectrum of silane plasma in the case of the present invention shown in Figure 2.
・Substrate film #w pole, 8°・group substrate, 14... Cylindrical high frequency application electrode, 17... Cylindrical substrate installed electrode, 20... Cylindrical metal Metush. l −・I ℃.

Claims (1)

【特許請求の範囲】[Claims] グロー放電分解法によるアモルファス半導体膜の製造に
おいて、円筒状基板設置事極内壁面に基板を設置すると
ともに該円筒状基板設置鴇、極の内部に同軸状に円筒状
の金楓メヅシーと高周波印加電極を配置し、グロー放電
空間と該基板が位置する膜堆積空間を分離することを特
徴とするアモルファス半導体膜の製造方法。
In the production of amorphous semiconductor films by the glow discharge decomposition method, a cylindrical substrate is installed on the inner wall surface of the electrode, and a cylindrical gold maple wire and a high frequency application electrode are placed coaxially inside the electrode. A method for manufacturing an amorphous semiconductor film, characterized in that a glow discharge space is separated from a film deposition space in which the substrate is located.
JP57095543A 1982-06-03 1982-06-03 Manufacture of amorphous semiconductor film Pending JPS58212129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57095543A JPS58212129A (en) 1982-06-03 1982-06-03 Manufacture of amorphous semiconductor film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57095543A JPS58212129A (en) 1982-06-03 1982-06-03 Manufacture of amorphous semiconductor film

Publications (1)

Publication Number Publication Date
JPS58212129A true JPS58212129A (en) 1983-12-09

Family

ID=14140474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57095543A Pending JPS58212129A (en) 1982-06-03 1982-06-03 Manufacture of amorphous semiconductor film

Country Status (1)

Country Link
JP (1) JPS58212129A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2458256A (en) * 2006-05-10 2009-09-16 Univ Open Surface activation and direct bonding of semiconductor wafers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4925398A (en) * 1972-05-12 1974-03-06
JPS5698820A (en) * 1980-01-09 1981-08-08 Nec Corp Preparation of amorphous semiconductor film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4925398A (en) * 1972-05-12 1974-03-06
JPS5698820A (en) * 1980-01-09 1981-08-08 Nec Corp Preparation of amorphous semiconductor film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2458256A (en) * 2006-05-10 2009-09-16 Univ Open Surface activation and direct bonding of semiconductor wafers
GB2458256B (en) * 2006-05-10 2011-08-03 Univ Open Semiconductor bonding techiniques

Similar Documents

Publication Publication Date Title
JPH06287760A (en) Plasma treating device and treatment
JPS627272B2 (en)
TW200823977A (en) Plasma doping method and plasma doping apparatus
JP3499104B2 (en) Plasma processing apparatus and plasma processing method
KR20020021337A (en) Plasma processing method and apparatus
GB1585558A (en) Growing native semiconductor oxide layers
JPS6136589B2 (en)
JP2020517103A (en) High Deposition Rate High Quality Silicon Nitride Enabled by Remote Nitrogen Radical Source
JPS58212129A (en) Manufacture of amorphous semiconductor film
JP3243807B2 (en) Ion irradiation equipment
CN112582252A (en) Method for forming semiconductor structure and semiconductor structure
JP3082659B2 (en) Plasma processing equipment
JPS58100430A (en) Plasma processor
JPS6314862A (en) Surface treatment device
JP2798225B2 (en) High frequency plasma CVD equipment
JP2765788B2 (en) Plasma CVD equipment
JPS58212128A (en) Manufacture of amorphous semiconductor film
JP3615919B2 (en) Plasma CVD equipment
JPH05315292A (en) Semiconductor manufacturing device and manufacture of semiconductor device
JP2649331B2 (en) Plasma processing method
JPS58210165A (en) Sputtering device
JPS60115220A (en) Three-electrode glow discharge type surface processing apparatus
JPH06120140A (en) Semiconductor manufacturing method and equipment
JP2776866B2 (en) Microwave plasma processing equipment
JPH0456449B2 (en)