JPS58210769A - Malfunction preventing circuit - Google Patents

Malfunction preventing circuit

Info

Publication number
JPS58210769A
JPS58210769A JP57095459A JP9545982A JPS58210769A JP S58210769 A JPS58210769 A JP S58210769A JP 57095459 A JP57095459 A JP 57095459A JP 9545982 A JP9545982 A JP 9545982A JP S58210769 A JPS58210769 A JP S58210769A
Authority
JP
Japan
Prior art keywords
microcomputer
power
power supply
reset
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57095459A
Other languages
Japanese (ja)
Inventor
Masateru Ito
伊藤　正輝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57095459A priority Critical patent/JPS58210769A/en
Publication of JPS58210769A publication Critical patent/JPS58210769A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Electromechanical Clocks (AREA)
  • Television Receiver Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Power Conversion In General (AREA)

Abstract

PURPOSE:To prevent an equipment from malfunctioning during an instantaneous power failure securely by detecting a drop of the power supply voltage to a memory element and resetting a microcomputer by a pulse signal generated by the voltage drop. CONSTITUTION:Once the memory element 12 is powered off, the voltage at a power supply terminal 1 drops and then the base voltage of a transistor TR2 also drops according to the time constant depending upon a resistance 6 and a capacitor 7. Charges in a capacitor 10, on the other hand, flow from the emitter to the base of the TR2 by the discharge stopping operation of a diode 5, so that the TR2 turns on for a specific time. Then, a pulse signal is generated at the collector of the TR2 by its specific-time on operation and applied to the base of a TR3, which turns on. Consequently, a reset signal is supplied to the reset terminal 4 of the microcomputer 11, which is reset to power off a television receiver. Thus, a voltage drop dueing an instantaneous break of power supply is detected to reset and power off the microcomputer before malfunction occurs, preventing the malfunction of the receiver securely.

Description

【発明の詳細な説明】 この発明はたとえばテレビジョン受信機などＫおける誤
動作防止回路に関し、とくに瞬時停電があった場合の誤
動作を防止するための回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for preventing malfunction in a television receiver or the like, and particularly to a circuit for preventing malfunction in the event of a momentary power outage.

′従来のテレビジョン受信機はマイクロコンピュータの
ようなメモリ機能をもつ素子をあまり使用していなかっ
たため、瞬時の停電が起ζつても再び電圧が印加されれ
ば正規の状態に復帰することが可能であった。しかし最
近のようにマイクロコンピュータなどのメモリ機能をも
った素子が多用されるようになると、素子の電源が２つ
以上存在する場合、両者のタイミングにより瞬時停電時
にテレビジョン受信−が誤動作する可能性がでてきた。'Conventional television receivers did not often use elements with memory functions such as microcomputers, so even if a momentary power outage occurred, they could return to normal status when voltage was applied again. Met. However, recently, devices with memory functions such as microcomputers have come into widespread use, and if there are two or more power sources for the device, there is a possibility that television reception will malfunction in the event of a momentary power outage depending on the timing of both. has appeared.

　　　　　′ この発明は仁のような集信にかんがみ、瞬時停電時にお
ける機器の誤動作を防止するための誤動作防止回路を提
供することを目的としている。' The present invention is intended to provide a malfunction prevention circuit for preventing equipment malfunctions during instantaneous power outages, in view of the power transmission.

以下、この発明の実施例をテレビジョン受信機に適用し
た場合について説明する。図において、ＤＩ）はテレビ
ジョン受信機の電源のＯＮ、ＯＦＦを制御する機能をも
つマイクロコンピュータ、（均は他の機能をもつＲＡＭ
などのメモリ素子、（１）はメモリ素子（ロ）の電源端
子、（４）はマイクロコンピュータ（ロ）のリセット端
子である。Hereinafter, a case where an embodiment of the present invention is applied to a television receiver will be described. In the figure, DI) is a microcomputer with the function of controlling the power on and off of the television receiver,
(1) is the power supply terminal of the memory element (b), and (4) is the reset terminal of the microcomputer (b).

（２）　、　（３）はそれぞれパルス整形用およびスイ
ッチング用のトランジスタで、これらのトフンシス１１
（２）　、　（３）によってスイッチング回路が構成さ
れる。(2) and (3) are transistors for pulse shaping and switching, respectively.
A switching circuit is configured by (2) and (3).

トランジスタ（２）のベースは抵抗（６）を介して電源
端子（１）に接続されているとともにコンデンサ（７）
を介して接地されている。また、トランジスタ（２）の
エミッタはダイオード（５）および抵抗（８）の直列回
路を介して電源端子（１）に接続されているとともにコ
ンデンサＱ◇を介して接地されている。さらに、トラン
ジスタ（２）のコレクタは抵抗（９）を介して接地され
ているトドもにトランジスタ（３）のペースに接続され
ている。トランジスタ（３）のエミッタは接地されてお
シ、コレクタはマイクロコンピュータ（ロ）のリセット
端子（４）に接続されている。The base of the transistor (2) is connected to the power supply terminal (1) via a resistor (6) and a capacitor (7).
is grounded through. Further, the emitter of the transistor (2) is connected to the power supply terminal (1) via a series circuit of a diode (5) and a resistor (8), and is also grounded via a capacitor Q◇. Further, the collector of the transistor (2) is connected to the grounded base of the transistor (3) via a resistor (9). The emitter of the transistor (3) is grounded, and the collector is connected to the reset terminal (4) of the microcomputer (b).

つぎに動作について説明する。いまメモリ素子（至）の
電源が断たれたとすると、電源端子（１）の電圧が立下
り、これにともなってトランジスタ（２）のベースハ抵
抗（６）とコンデンサ（７）の時定数にしたがって電圧
が下がる。一方、コンデンサａｔ）ＩＣ充電されている
電荷は、ダイオード（６）の放電阻止作用によシトラン
ジスタ（２）のエミッタからベースを通じて流れ、との
ためトランジスタ（２）は一定時１［ＯＮする。トラン
ジスタ（２）が一定時間ＯＮすることによってそのコレ
クタにはバ／ｌ／ヌ信号が発生し、とのバルヌ信号ハト
ランジスタ（３）のベースに加えられてトランジスタ（
３）をＯＮさせる。トランジスタ（３）がＯＮすると、
マイクロコンピュータａ力のリセット端子（４）にリセ
ット信号が与えられるので、マイクロコンピュータＱυ
はリセットされ、テレビジョン受信機の電源がＯＦＦと
なる。このように、電源の瞬時の立下シを検出して、誤
動作が起こる前にマイクロコンピュータをリセットして
電源をＯＦＦすることにより受信機の誤動作を確実に防
止することができる。Next, the operation will be explained. Assuming that the power to the memory element (to) is cut off, the voltage at the power supply terminal (1) falls, and as a result, the voltage at the base of the transistor (2) increases according to the time constant of the resistor (6) and capacitor (7). goes down. On the other hand, the electric charge charged in the capacitor at) IC flows from the emitter to the base of the transistor (2) due to the discharging blocking action of the diode (6), so that the transistor (2) is turned on at a certain time. When the transistor (2) is turned on for a certain period of time, a bar/l/nu signal is generated at its collector, and the barnu signal is added to the base of the transistor (3), causing the transistor (
3) Turn on. When transistor (3) turns on,
Since the reset signal is given to the reset terminal (4) of the microcomputer a, the microcomputer Qυ
is reset, and the power to the television receiver is turned off. In this way, it is possible to reliably prevent receiver malfunctions by detecting instantaneous power failure and resetting the microcomputer and turning off the power before malfunctions occur.

なお、上記実施例においてはテレビジョン受信機の場合
について説明したが、この発明はテレビジョン受信機以
外にもたとえば時計や文字発生器などにも適用できるこ
とはいうまでもない。また、上記実施例ではマイクロコ
ンピュータ０υとは別のメモリ素子（ロ）の電源の立下
シを検出するようにしたが、マイクロコンピュータＱｌ
）自身のメモリ素子の電源を利用することも考えられる
。この場合は、入カバμスなどのタイミングにおける誤
動作を防止することができる。In the above embodiments, the case of a television receiver has been described, but it goes without saying that the present invention can be applied not only to television receivers but also to clocks, character generators, etc. In addition, in the above embodiment, the falling power of the memory element (b) which is different from the microcomputer 0υ is detected, but the microcomputer Ql
) It is also possible to use the power supply of the own memory element. In this case, malfunctions at timings such as input bus μ can be prevented.

以上実施例について述べたことから明らかなように、こ
の発明によれば、メモリ素子の電源電圧の立下シを検出
して、これによって発生するノ（ルス信号によシマイク
ロコンピュータをリセットするようにしたので、瞬時停
電時における機器の誤動作を確実に防止することができ
る効果がちゐ。As is clear from the above description of the embodiments, according to the present invention, the falling edge of the power supply voltage of the memory element is detected, and the microcomputer is reset using the noise signal generated thereby. This has the effect of reliably preventing equipment malfunctions during instantaneous power outages.

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの発明の一実施例を示す回路図である。 （１）・・・電源端子、　（２）　、　（３）・・・ト
ランジスタ、（４）・・・リセット端子、Ｑｌ）・・・
マイクロコンピュータ、＠・・・メモリ素子。 代理人　葛野信−（外１名）The drawing is a circuit diagram showing an embodiment of the present invention. (1)...power supply terminal, (2), (3)...transistor, (4)...reset terminal, Ql)...
Microcomputer, @...memory element. Agent Shin Kuzuno (1 other person)

Claims (1)

【特許請求の範囲】[Claims] （１）機器の電源のＯＮ、ＯＦＦを制御する機能をもつ
マイクロコンピュータと、他の機能をもつメモリ素子と
、このメモリ素子の電源電圧の立下υを検出してパルス
信号を発生するスイッチング回路とを有し、上記パルス
信号によシ上記マイクロコンピュータをリセットして機
器の電源をＯＦＦさせるようにしたことを特徴とする誤
動作防止回路。 ７（２）スイッチング回路は、所定の時間以上電源がＯ
ＦＦ　したときにパルス信号を発生する仁とを特徴とす
る特許請求の範囲第１項記載の誤動作防止回路。(1) A microcomputer that has the function of controlling the ON/OFF of the power supply of the device, a memory element that has other functions, and a switching circuit that detects the fall υ of the power supply voltage of this memory element and generates a pulse signal. A malfunction prevention circuit characterized in that the pulse signal resets the microcomputer and turns off the power of the device. 7(2) The switching circuit shall not be powered on for a specified period of time or more.
The malfunction prevention circuit according to claim 1, characterized in that the circuit generates a pulse signal when an FF is applied.
JP57095459A 1982-06-01 1982-06-01 Malfunction preventing circuit Pending JPS58210769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57095459A JPS58210769A (en) 1982-06-01 1982-06-01 Malfunction preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57095459A JPS58210769A (en) 1982-06-01 1982-06-01 Malfunction preventing circuit

Publications (1)

Publication Number Publication Date
JPS58210769A true JPS58210769A (en) 1983-12-08

Family

ID=14138255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57095459A Pending JPS58210769A (en) 1982-06-01 1982-06-01 Malfunction preventing circuit

Country Status (1)

Country Link
JP (1) JPS58210769A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0798728A1 (en) * 1996-03-29 1997-10-01 STMicroelectronics S.r.l. Power-on reset signal generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0798728A1 (en) * 1996-03-29 1997-10-01 STMicroelectronics S.r.l. Power-on reset signal generating circuit
US5959476A (en) * 1996-03-29 1999-09-28 Sgs-Thomson Microelectronics S.R.L. Circuit and method for generating a power-on reset signal

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