JPH0132367Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a latch-up presetting circuit for a semiconductor integrated circuit that automatically resets a latch-up that occurs in a semiconductor integrated circuit.

Background Art Various semiconductor integrated circuits are used in television receivers. For example, semiconductor integrated circuits for microcomputers that control power on/off, channel selection, volume adjustment, etc. are used in picture tubes. may latch up due to discharge. This latch-up occurs when a parasitic thyristor existing in the device structure of a CMOSIC is triggered by an external surge, and can be said to be a dangerous condition that can lead to overcurrent destruction.

In order to prevent this overcurrent breakdown, conventionally, for example, as shown in FIG.
A method is adopted in which a current limiting resistor R ₀ is interposed between V _DD and the power supply circuit 2 to limit the current.

However, although this conventional method can prevent overcurrent damage, once a latch-up occurs, the latch-up cannot be released unless the power supply circuit 2 itself is turned off.
Particularly, when a microcomputer with a timer mechanism is used in the above-mentioned television receiver, etc., the microcomputer becomes inoperable due to the occurrence of this latch-up. Normally, the switch that turns off all power to a television receiver is often located on the back of the cabinet in order to ensure power is supplied to the microcomputer that has a timer function. , the timer function can be restored by turning off the power switch on the back of the cabinet, but users who do not know this may assume that there is a failure, and even if a service person can repair it, There were drawbacks such as the tendency for users to lose trust in the product.

DISCLOSURE OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and detects latch-ups occurring in semiconductor integrated circuits.
After grounding the power supply terminal of the semiconductor integrated circuit,
It is an object of the present invention to provide a latch-up reset circuit for a semiconductor integrated circuit, which automates the reset of a latch-up by releasing the ground.

In order to achieve this objective, the present invention provides a semiconductor integrated circuit which cannot be reset without turning off the power supply when a latch-up occurs, and a semiconductor integrated circuit that is connected to the power supply terminal of the semiconductor integrated circuit, Detects and operates,
The main feature is that the power supply terminal is grounded and includes a reset circuit that releases the grounding as time elapses after the power terminal is grounded.

According to the present invention, a reset circuit is connected to the power supply terminal of the semiconductor integrated circuit, detects the occurrence of latch-up, grounds the power supply terminal, and releases the grounding as time elapses after grounding.
For example, if a parasitic thyristor existing in the device structure of a semiconductor integrated circuit is triggered by an external surge and a latch-up occurs, the power to the semiconductor integrated circuit can be effectively turned off even if the power is not turned off once. It is possible to return to normal operation without any help from the user, and is therefore suitable for semiconductor integrated circuits for television receivers, where latch-up due to discharge of the picture tube is expected. be effective.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the invention will be described with reference to FIG. 2. FIG. 2 is a circuit diagram showing an embodiment of the latch-up preset circuit of the semiconductor integrated circuit of the present invention. In FIG. 2, the same components as in FIG. 1 are given the same reference numerals.

In FIG. 2, 11 is a reset circuit connected to both ends of the current limiting resistor _R0 . This reset circuit 11 has a transistor Q ₁ for detecting a latch-up occurring in the semiconductor integrated circuit 1 and a transistor Q ₂ for connecting the power supply terminal V _DD of the semiconductor integrated circuit 1 . Transistor Q ₁ has emitter and base terminals connected to resistors R ₁ and R ₂ respectively.
The collector terminal is connected to the base terminal of the transistor _Q2 . The corctor terminal of the transistor _Q2 is connected to the power supply terminal _VDD , and the emitter terminal is grounded. An electrolytic capacitor C is connected between the power supply terminal _VDD and the base terminal of the transistor _Q1 .

Suppose now that the parasitic thyristor in the semiconductor integrated circuit 1 is triggered by an external surge and a latch-up occurs. In this case, as the latch-up occurs, the current flowing through the power supply terminal V _DD increases significantly, so the potential of the power supply terminal V _DD drops. As a result, the base potential of the transistor Q ₁ also decreases via the electrolytic capacitor C, and the transistor Q ₁ becomes conductive first. And transistor Q ₁
Following the conduction of Q 2 , transistor Q ₂ conducts;
Power supply terminal V _DD is grounded. As a result, the semiconductor integrated circuit 1 is substantially turned off, so that the latch-up is reset.

When the latch-up is reset, the semiconductor integrated circuit 1 returns to normal operation, but the power supply terminal _VDD is still grounded. But transistor Q ₂
After grounding by, the electrolytic capacitor C starts to charge through the low resistor _R2 , so the transistor
The base potential of Q ₁ is gradually recovering. Therefore, over time, when the base voltage of transistor Q ₁ exceeds a certain value, transistor Q ₁
At the same time, the transistor Q ₂ is also rendered non-conductive, and at the same time, the power supply terminal V _DD is also released from the grounded state. Thereby, the latch-up of the semiconductor integrated circuit 1 is automatically reset without bothering the user.

In this way, the reset circuit 11 is suitable for the semiconductor integrated circuit 1 where latch-up is expected.
It is particularly suitable for semiconductor integrated circuits incorporated in microcomputers for channel selection, volume adjustment, etc., which are susceptible to surges due to discharge from picture tubes.

As explained above, according to the reset circuit for the semiconductor integrated circuit having the above configuration, the reset circuit 11 is connected to the power supply terminal V _DD of the semiconductor integrated circuit 1,
Since the structure is configured to detect the occurrence of latch-up, ground the power supply terminal V _DD , and release the grounding as time passes after the grounding, for example, a parasitic thyristor that exists in the device structure of the semiconductor integrated circuit 1 can be removed from the outside. If a latch-up occurs due to a surge in the semiconductor integrated circuit 1, the power supply circuit 2 of the semiconductor integrated circuit 1 can be effectively turned off without having to be turned off once, and normal operation can be resumed without any user intervention. Therefore, it is suitable for semiconductor integrated circuits for television receivers in which latch-up due to discharge of a picture tube is expected, for example.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram showing an example of a semiconductor integrated circuit with conventional overcurrent prevention measures, and Figure 2 is
1 is a circuit configuration diagram showing an embodiment of a latch-up preset circuit for a semiconductor integrated circuit according to the present invention; FIG. 1... Semiconductor integrated circuit, 2... Power supply circuit, 11
...Reset circuit, V _DD ...Power supply terminal.

Claims (1)

[Scope of utility model registration request] When a latch-up occurs, the latch-up cannot be reset unless the power supply is turned off once.It is connected to the semiconductor integrated circuit and the power supply terminal of the semiconductor integrated circuit, and is activated upon detecting the occurrence of the latch-up, and resets the power supply terminal. A latch-up preset circuit for a semiconductor integrated circuit comprising a reset circuit that is grounded and then released from the ground as time passes after grounding.