JPS58210588A - Electronic timepiece capable of trimming - Google Patents

Electronic timepiece capable of trimming

Info

Publication number
JPS58210588A
JPS58210588A JP9419482A JP9419482A JPS58210588A JP S58210588 A JPS58210588 A JP S58210588A JP 9419482 A JP9419482 A JP 9419482A JP 9419482 A JP9419482 A JP 9419482A JP S58210588 A JPS58210588 A JP S58210588A
Authority
JP
Japan
Prior art keywords
circuit
current
voltage
current limiting
oscillation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9419482A
Other languages
Japanese (ja)
Other versions
JPH0318157B2 (en
Inventor
Yoshiaki Matsuura
松浦 義昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP9419482A priority Critical patent/JPS58210588A/en
Publication of JPS58210588A publication Critical patent/JPS58210588A/en
Publication of JPH0318157B2 publication Critical patent/JPH0318157B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G19/00Electric power supply circuits specially adapted for use in electronic time-pieces
    • G04G19/02Conversion or regulation of current or voltage
    • G04G19/06Regulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromechanical Clocks (AREA)

Abstract

PURPOSE:To drive an electronic timepiece with minimum necessary electric power by selecting a current limiting element and trimming the limit value of a current to a desired value. CONSTITUTION:N type MOS transistor (TR) 26a-26c forming current limiting elements applied with a bias voltage through a constnat voltage circuit 27 have mutually different saturation currents. When TRs 26a-26c are turned on selectuvely through switches 32a-32c, the current limit value of the oscillator 22 and frequency divider 23 of a timer circuit is trimmed to a desired value. Therefore, the electronic timepiece is driven with minimum necessary electric power according to variance of characterisitcs among constitutent elements.

Description

【発明の詳細な説明】 本発明はトリミング可能な電子時計に関し、更に詳細に
述べると、電子時針の主要回路部に供給される電力か所
要の最低消費縫となるようにトリミングすることができ
る電子時計に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a trimmable electronic timepiece, and more specifically, the present invention relates to a trimmable electronic timepiece, and more specifically, the present invention relates to an electronic timepiece that can be trimmed so that the power supplied to the main circuit section of the electronic hour hand consumes the minimum required stitches. Regarding watches.

電子時計においてQよ、水晶発振回路及びその発JR出
力を分周する分周回路で消費される電力全極力小さくす
ることが要求される。この要求を満たすため、最近、第
1図に示す構成の電子時計が提案されている。第1図に
示されている電子時計1は、電池20両端に足電圧源3
を接続し、その出力4により電流制限素子5を接続し、
発伽回路6と分周回路7の電源の交点8と電流制限素子
5の曲端とを接続し、発振回路6と分周回路70曲の、
電源端子は電池2の曲端9に接続されて成っている。電
流制限素子5はM O8FETで作られ1発振回路6.
は、PチャンネルMaSトランジスタとNチャンネルM
OSトランジスタを互いに直列に接続して成の相補型M
OEIインバータで構成されの。
In electronic watches, it is required to minimize the power consumed by the crystal oscillator circuit and the frequency divider circuit that divides the frequency of the oscillator output. In order to meet this demand, an electronic timepiece having the configuration shown in FIG. 1 has recently been proposed. The electronic watch 1 shown in FIG.
, and its output 4 connects the current limiting element 5,
The intersection 8 of the power supplies of the oscillation circuit 6 and the frequency division circuit 7 is connected to the curved end of the current limiting element 5, and the oscillation circuit 6 and the frequency division circuit 70 are connected to each other.
The power terminal is connected to the bent end 9 of the battery 2. The current limiting element 5 is made of MO8FET, and the 1 oscillation circuit 6.
is a P-channel MaS transistor and an N-channel M
Complementary type M formed by connecting OS transistors in series
Consists of OEI inverter.

次に、第1図に示した回路の仮作について説明する。第
2図に示すように、インバータを構成するPチャンネル
MOSトランジスタ(図示せず)のスレッショールド電
圧v’rp  とNチャンネルMo8 トランジスタ(
図示せず)のスレッショールド電圧VTN  にPチャ
ンネルMOSトランジスタとNチャンネルMO8)ラン
ジスタが両方ONにlる重圧Voが加わった重圧V D
2か、第1図の電源ライン8との間に加わる事が、発振
開始時に於いては必要になる。
Next, a tentative construction of the circuit shown in FIG. 1 will be explained. As shown in FIG. 2, the threshold voltage v'rp of the P-channel MOS transistor (not shown) constituting the inverter and the N-channel Mo8 transistor (
A heavy pressure V D is added to the threshold voltage VTN of the P-channel MOS transistor (not shown) and the heavy pressure Vo that turns on both the P-channel MOS transistor and the N-channel MO transistor (8).
2 or between it and the power supply line 8 shown in FIG. 1 is required at the start of oscillation.

発振開始時点のηを圧VT+2を(1)式で表わす。η at the time of starting oscillation is expressed as pressure VT+2 by equation (1).

VD2 ≧  IV、TT’l   −ト  V T’
   +  Vo    −−tl)発振を開始してし
まうと、(1)式の11係は(2)式の関係になる。発
揚を維持する為の重圧をV’DIとすると、 VD、≧VDl≧ l Vrp I  + VTN −
−−−−−(21第3図に、第1図の電流制限素子5を
MO8−FETで構成する場合のMOSFETのソース
ドレイン間電圧VD日 とドレイン市、流よりの関係を
示す。第1図の基準電圧回路5からの出力4の電圧をV
a  とすると、8f!5図はその時のソースドレイン
間電圧VDBとドレイン電流IDの関係を表わす事にな
る。第1図の電、池2の両端9,10にかかる重圧をV
DDとすると、’R(池の一端9と交点8との間にかか
る電、EF:、 V D  と市1m電圧VDDとの差
の電圧がM O8F E Tの飽和ソースドレイン間電
圧v8以上の場合は、i4を流よりは一定帥よりIなる
電流が流れ、それ釣下の場合は、ソースドレイン間電圧
VIg の減少と共に減少するID27zる電流が流れ
る。
VD2 ≧ IV, TT'l - VT'
+Vo --tl) Once oscillation has started, the 11th equation of equation (1) becomes the relationship of equation (2). If the pressure to maintain lift is V'DI, then VD, ≧VDl≧ l Vrp I + VTN −
-------(21) Figure 3 shows the relationship between the source-drain voltage VD of the MOSFET and the drain level and current level when the current limiting element 5 in Figure 1 is configured with an MO8-FET. The voltage of the output 4 from the reference voltage circuit 5 in the figure is V
If it is a, then 8f! FIG. 5 shows the relationship between the source-drain voltage VDB and the drain current ID at that time. The heavy pressure applied to both ends 9 and 10 of the battery and battery 2 in Figure 1 is V
If DD, 'R (the electric current applied between one end 9 of the pond and the intersection 8, EF:, the voltage difference between V D and the city 1m voltage VDD is greater than or equal to the saturated source-drain voltage v8 of M O8 F ET In this case, a current of I flows at a constant level rather than a current through i4, and when it is lower than that, a current of ID27z flows which decreases as the source-drain voltage VIg decreases.

VDD −VD > Vs  の場合はより=IDl一
定値 VDD −VD (Va  #  #  より = I
D。
If VDD - VD > Vs, then = IDl constant value VDD - VD (from Va # # = I
D.

可変値 第1図に於いて発振開始時点を考えると、分周回路は動
作しτいないのでその時の分周回路の消費電流をI’D
IVとすると、その値は極めて少ない。
Variable Value Considering the point at which oscillation starts in Figure 1, the frequency divider circuit is not operating τ, so the current consumption of the frequency divider circuit at that time is I'D.
When it comes to IV, the value is extremely small.

その為、電流制限素子に流れる電流の最大値のIDIの
ほとんどを発振回路が使える事になる。発振開始時点の
発振回路の電流をl’osc  とすると、IDI ”
: I’oec  なる関係が成立する。発掘開始に必
要な電圧が、第3図に示す電源電圧VDDと、MO−日
電流制限素子の飽和ソースドレイン電圧VS  の差工
り大きな電圧が必讐になる場合は、第1図の電源の一端
9と交点8にかかる電圧VD が自動的に嶋くなり1発
振開始に必要な電圧vn2になる。
Therefore, most of the maximum value IDI of the current flowing through the current limiting element can be used by the oscillation circuit. If the current of the oscillation circuit at the time of starting oscillation is l'osc, then IDI"
: I'oec holds true. If the voltage required to start excavation is a large difference between the power supply voltage VDD shown in Figure 3 and the saturated source-drain voltage VS of the MO-current limiting element, the power supply voltage shown in Figure 1 must be The voltage VD applied to one end 9 and the intersection 8 automatically decreases to a voltage vn2 required to start one oscillation.

この時、電流制限素子5に流れる電流は、VDの増加と
共に少なくなる。
At this time, the current flowing through the current limiting element 5 decreases as VD increases.

ざ1も掘開始の条件としては、相補型Mo8インバータ
を使う場合には、印加%17圧が条件を満足するη1が
第一条件になる。第二売件としては1発振開始に必要な
電流が条件を満足する事が条件となるので、発揚回路6
と分周回路7とにががる重圧VDし1、上記の2条件を
満足する宙、力M +31式の点まで。
When using a complementary Mo8 inverter, the first condition for starting digging is η1, which satisfies the condition of applied %17 pressure. The second selling point is that the current required to start one oscillation satisfies the conditions, so the oscillation circuit 6
and the frequency dividing circuit 7 and the heavy pressure VD1, which satisfies the above two conditions, until the point of the force M +31 equation.

m圧VD が増加し、電流制限素子の電流ちが減少する
。K苓:発振開始に必要な電力積とすると、VD・ID
≧K・・・・・・・・・・・・・・・(3)が成立する
ところまで、自動的にバイアスが変化する。
The mpressure VD increases and the current of the current limiting element decreases. K: Assuming the power product required to start oscillation, VD・ID
≧K The bias is automatically changed until (3) is satisfied.

発掘開始に必要な電圧が、電源電圧VDDと電流制限素
子のソースドレイン間電圧VS  との差以下の電1圧
の場合け、電流制限素子の飽和電流工)を発振開始tl
’、R,I’ oθCと分周回路の!fff、工/n、
 v  で分ける事になり、(4)式が成立する。
If the voltage required to start excavation is less than the difference between the power supply voltage VDD and the source-drain voltage VS of the current limiting element, the saturation current of the current limiting element starts to oscillate.
', R, I' oθC and frequency divider circuit! fff, 工/n,
It is divided by v, and equation (4) is established.

IDI = I’o日a + 1’bl v ・= −
−−f41以上から、発振が正常に開始すると、分周に
必要な軍、流庖Vが増加して発振回路の電流l6scが
減少して、それぞれ発掘維持の発据回路屯流Ioscが
止常発珈時の分周回路の紙流工qv[yzす、ぞの和は
変化しないので、+51. (61,+71式の関係が
成シ立つ。
IDI = I'o day a + 1'bl v ・= −
--When oscillation starts normally from f41 or above, the power and current V required for frequency division increase, the oscillation circuit current l6sc decreases, and the oscillation circuit current Iosc for excavation and maintenance stops. Since the sum of the frequency dividing circuit qv [yz and zo] at the time of firing does not change, +51. (The relationship of formulas 61 and +71 holds true.

IDI v >  I’DI v  ・・・・・・・・
・・・・・・・・・・・・・(5)工osc ) I’
osc   ・・・……・・・・・・・・・…(6)I
DI =Iosc+よりl v = I’osc + 
I’DI v ・・−・・・(71これらの動作は、電
流制限素子5により供給される電流な分周回路7と発振
回路6の両方で配分する構成である為、発掘開始時点と
安定発揚時点で必要な電流の比率が、発振回路と分周回
路でそれぞれ異なる事を、積極的に利用している。又、
電圧を制御する方式でないので、発振回路と分周回路に
印加される電圧が自動的に可変されて、最適な電圧で駆
動出来る為に、電圧制御の方式のように発掘開始したか
どうかを判定する回路が必要でなくなり、開シー1での
動作となる。従って一度安定な動作条件が設定されると
、安定動作を持続する事が可能になる。
IDI v >I'DI v ・・・・・・・・・
・・・・・・・・・・・・・・・(5) 工OSC)I'
osc ・・・・・・・・・・・・・・・・・・(6)I
Since DI = Iosc +, l v = I'osc +
I'DI v... (71) These operations are configured so that the current supplied by the current limiting element 5 is distributed by both the frequency divider circuit 7 and the oscillation circuit 6. We actively utilize the fact that the ratio of current required at the time of launch is different between the oscillation circuit and the frequency dividing circuit.Also,
Since this is not a method that controls voltage, the voltage applied to the oscillation circuit and frequency divider circuit is automatically varied and can be driven at the optimal voltage, so it is judged whether or not excavation has started, like in the voltage control method. There is no longer a need for a circuit to do this, and the operation is performed in open sea mode 1. Therefore, once stable operating conditions are set, stable operation can be maintained.

ところで、定電圧源3と電流制限素子5とは。By the way, what are the constant voltage source 3 and the current limiting element 5?

例えば第4図に示す回路構成のものが用いられるが、こ
の回路を工C化する場合にバラツキが生じ、第5図に示
した電流\電圧特性が所望の状態から外れ、神々の不具
合いを生ずるという間鴨点を有している。特に、電流値
■Dlの大きさにバラツキを生じ、IDIの値が予定の
電流範囲工す大きな値となると分周回路7が作動障?l
e−起し、正常な動作を行なわ〃る#よか、IDIが所
定1市以下となると回路の動作が停止することとなる。
For example, the circuit configuration shown in Fig. 4 is used, but when converting this circuit into a circuit, variations occur and the current/voltage characteristics shown in Fig. 5 deviate from the desired state, resulting in a divine malfunction. It has an intermediate point called arising. In particular, if there is variation in the magnitude of the current value Dl and the value of IDI exceeds the expected current range, the frequency divider circuit 7 may malfunction. l
If the IDI falls below the predetermined value of 1, the operation of the circuit will stop.

また、ll)lの大きさが回路の作動可能範囲内に人っ
ていたとしても、必ずしも、定常動作状腕Vこおいて必
要最小限のηi力供給状態を実視できない場合も生じ、
このような電力制御回路を付加した意味が没却される場
合も生じていた。
In addition, even if there is a person whose size ll)l is within the operable range of the circuit, it may not necessarily be possible to actually see the necessary minimum ηi force supply state with the arm V in steady motion,
In some cases, the purpose of adding such a power control circuit has been lost.

本発明の目的は、従って、電流制限素子による′Ft(
流の制限値の値をトリミングにニジ所望の範囲内に収め
ることができ、必要最小限の電力で回路を作動させるこ
とができるJうにした、トリミング可能な電子時計を提
供することにある。
Therefore, the object of the present invention is to provide 'Ft(
To provide a trimmable electronic timepiece in which a current limit value can be kept within a desired range for trimming and a circuit can be operated with the minimum necessary power.

以下、本発明を図示の実施例により詳細に駁明する。Hereinafter, the present invention will be explained in detail by means of illustrated embodiments.

第5図にtま、本発明による’rJi子時計の構成図が
示されている。電子時計21 &、i、水晶発掘回路2
2゜分周回路23及び演算表示回路24を備え、これら
の各回路の一方の電源端子は電池25の十極端子に接続
されている。演η、表示回路24の四方の電源端子はア
ースされ、一方、水晶発掘回路22及び分周回路25の
各地方の電源端子は共通に接続され、電流制限用のNチ
ャンネルMOSトランジスタ26a乃至26cの各ドレ
インに接続されている。MOS)ランラスタ26a乃至
26cの各ソースは共通にアースされ、各ゲートは共通
に接続されて定電圧発生回路27の出力ライン28に接
続される。
FIG. 5 shows a block diagram of the 'rJi slave clock according to the present invention. Electronic clock 21 &, i, crystal excavation circuit 2
A 2° frequency dividing circuit 23 and an arithmetic display circuit 24 are provided, and one power supply terminal of each of these circuits is connected to a ten-pole terminal of a battery 25. In operation, the power terminals on all four sides of the display circuit 24 are grounded, while the power terminals of each region of the crystal excavation circuit 22 and frequency dividing circuit 25 are connected in common, and the N-channel MOS transistors 26a to 26c for current limiting are connected to each other. Connected to each drain. The sources of the MOS) run rasters 26a to 26c are commonly grounded, and the gates of the MOS run rasters 26a to 26c are commonly connected to the output line 28 of the constant voltage generating circuit 27.

定電圧発生回路27は、ディツーし・ジョン型Nチャン
ネルMOSトランジスタ29とエンハンスメント型Nチ
ャンネルMO8)ランジスタ30とから成り、ドレイン
が%池25の十極端子に接続されているMOS)ランジ
スタ29のソースとゲートとは短絡され、MOS)ラン
ラスタ300ゲートとドレ(ンとに接続されている。M
osトランジスタ6Uのソースはアースさ)11両MO
8)ランジスタ29.30の材続点61に生じた一定Q
f汁がバイアス電EhVBと1〜で出力ライン28に生
じることになる。
The constant voltage generation circuit 27 consists of a detour type N-channel MOS transistor 29 and an enhancement type N-channel MO8) transistor 30, and the source of the MOS transistor 29 whose drain is connected to the ten-pole terminal of the transistor 25. and the gate are short-circuited, and connected to the MOS) run raster 300 gate and drain.M
The source of os transistor 6U is grounded) 11 MO
8) Constant Q generated at material connection point 61 of transistor 29.30
f juice will be generated in the output line 28 at the bias voltage EhVB and 1~.

定71i圧発生回路27と、藺OSトランジスタから成
る電流制限素子とにより、発掘回路ノ2及び分周回路2
5への供給ηを力が自動的にH¥節される動作は、第1
図乃至第4図により駁明j7/このと全く同一である。
The excavation circuit No. 2 and the frequency dividing circuit No. 2 are generated by the constant 71i pressure generating circuit 27 and the current limiting element consisting of an OS transistor.
The operation in which the force η supplied to 5 is automatically H
From Figures to Figure 4, it is exactly the same as Pierming j7/this.

この供給重力S周部動作が所期の通りT−+ irわり
、、目つ最小の電力で1p1路の動作を行なわ4tシめ
ることができるよう回路の1門′翳を?■なう目的で、
電流制限中のMOSトランジスタ26a乃至26cは、
ドレインソース開面H−が飽和した場合の各ドレイン1
@流IDa、 ITlb、 IDcが夫々異なるように
設計されている。そして、これら5つのMOS トラン
ジスタのうちの任意のトランジスタのみを電流制限素子
として作動させることができるように、MOS トラン
7スタ26a乃至26Cの各ドレイン回路には、トラン
ジスタ切離し用の配線部52 a 、 35゛b 、 
 56’ cが設けられており、これらの配線部を選択
的に切離すことにエリ、R「望のM OB )ランジス
タのみを菫、流制限素子として利用することができ、電
流制限特性を所望の特性に設定することができ/)。こ
のため、ただ1つの電流制限素子を用いて回路22.2
3に流れる電流を制限するのと異なり、製造」:の理由
で電流制限素子又は電圧発生回路27の特性にバラツキ
が生じても、配線部32a、32b、32cの切断箇所
を嘴択することにより、電流制限素子と[7て使用−す
るTA Q S )ランジスタの組合せ′ff:変え、
回路動作eこ支障を与えることなしに最も少ない消Q 
!、力で回路を動作させるMOS トランジスタの組合
せを膚ぶことかできる。
If this supply gravity S circumferential operation reaches T-+ir as expected, one gate of the circuit can be closed by 4t by performing 1p1 operation with the lowest power. ■For the purpose of now,
The MOS transistors 26a to 26c during current limitation are
Each drain 1 when the drain-source open plane H- is saturated
@style IDa, ITlb, and IDc are designed to be different. Then, in order to be able to operate only any transistor among these five MOS transistors as a current limiting element, each drain circuit of the MOS transistors 26a to 26C is provided with a wiring section 52a for disconnecting the transistor. 35゛b,
56'c is provided, and by selectively disconnecting these wiring parts, only the transistor (R) can be used as a current limiting element, and the current limiting characteristics can be adjusted as desired. Therefore, circuit 22.2 can be configured using only one current limiting element.
However, even if there are variations in the characteristics of the current limiting element or voltage generating circuit 27 due to manufacturing reasons, it is possible to limit the current flowing through the wiring parts 32a, 32b, and 32c. , the combination of the current limiting element and the [TAQS used in 7] transistor'ff: change,
Minimum loss of Q without interfering with circuit operation
! , a combination of MOS transistors can be used to operate a circuit using power.

配線部分52a乃至52cをどのように切断するかは、
ICの製造工程における各要素に′@つところが大きく
、その時のシリコンの不純物の濃度、酢化膜厚のバラツ
キに因るものである。従って、第6図に示す如く、ウニ
・・−41中の適宜の箇所にモニタ42a、42b、4
2c、42dを予め設けでおき、全ての工程が終了した
後に、これらのモニタを用いて評価を行ない、IDIを
所望の値とするために必要な配線R13の項内1状を別
に用意し、この切断用パターンにより所望のチックを最
終的に得るようにしてもよい。
How to cut the wiring portions 52a to 52c is as follows.
This largely depends on each element in the IC manufacturing process, and is due to variations in the concentration of silicon impurities and the thickness of the acetylated film at that time. Therefore, as shown in FIG. 6, monitors 42a, 42b, 4
2c and 42d are provided in advance, and after all the steps are completed, evaluate using these monitors and separately prepare the wiring R13 in the item 1 that is necessary to set the IDI to the desired value. This cutting pattern may ultimately provide the desired tick.

」−8シ二で佐↓、hp o S トランジスタ26a
、26’b。
”-8 Shijide sa↓, HP o S transistor 26a
, 26'b.

26cの各ドレイン?初め配線しておき、後から不要な
ものを切断する方法について述べたが、各MO8トラン
ジスタのドレイン紮予め配線せずに製造し、モンタで計
測した後に所望の結線を行なうようにしてもよいことは
勿論である。
Each drain of 26c? We have described the method of wiring first and cutting off unnecessary parts later, but it is also possible to manufacture the drains of each MO8 transistor without wiring them in advance and make the desired connections after measuring with a monitor. Of course.

このような構成にまれ目−1回路の動作に心情な最少の
電力を供給するようにトリミングできるので、歩留りが
著しく向上するのは勿論のこと、製造70+スにおける
特性のバラツキがあっても、消費電、力を最小f10に
抑え込むことが容易に行なえ、商品質の回路装置を安価
に、大曖にイル、給することができる。
In this configuration, it is possible to trim the circuit so that the minimum amount of power is supplied to the operation of the circuit, which not only significantly improves the yield, but also allows for even if there are variations in characteristics during the manufacturing process. Power consumption and force can be easily suppressed to the minimum f10, and commercial quality circuit devices can be supplied at low cost and in a large size.

本発明によれば、上述の如く、製造フーロセス上生じる
素子の特性のバラツキがあっても、トリミングにより、
供給電力の制#1値を所定の最小限度に調節jることか
でき、高品質の一1子時計を得ることができる。
According to the present invention, as described above, even if there are variations in the characteristics of the device caused by the manufacturing process, trimming can
The power supply limit #1 value can be adjusted to a predetermined minimum level, and a high quality child clock can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電子時計の構成を示すブロック図、第2
図は第1図にました水晶発掘回路の入力と出力の電圧の
関係を示すグラフ、第3図は第1図の電流制限水子のノ
ースドレイン間電圧VD8とドレイン電流より との関
係を示すグラフ、第4図は第1図に示した電流制御用回
路部の一具体例を示す回路図、第5図は本発明による電
子時計の構成ケ示すブロック図、946図は第5図の電
子時計用のICウェハーにモニタを設けた揚台の例を示
す平面図である。 21・・・lr、子時計、   22・・・水晶発掘回
路、25・・・分周回路、   25・・・電池、26
a、 26b、 26cm・・NチャンネルMO8)ラ
ンジスタ、       27・・・定電圧発生回路1
.52a、 62b、 32c ・−・配線部、VB・
・・バイアス實警、圧。 以   上 出願人 株式会社 第二精工舎
Figure 1 is a block diagram showing the configuration of a conventional electronic watch;
The figure is a graph showing the relationship between the input and output voltages of the crystal excavation circuit shown in Fig. 1, and Fig. 3 shows the relationship between the north-drain voltage VD8 of the current-limiting water element in Fig. 1 and the drain current. 4 is a circuit diagram showing a specific example of the current control circuit shown in FIG. 1, FIG. 5 is a block diagram showing the configuration of the electronic timepiece according to the present invention, and FIG. FIG. 2 is a plan view showing an example of a platform in which a monitor is provided on an IC wafer for a watch. 21...lr, child clock, 22...crystal excavation circuit, 25...frequency dividing circuit, 25...battery, 26
a, 26b, 26cm...N-channel MO8) transistor, 27...constant voltage generation circuit 1
.. 52a, 62b, 32c --- Wiring section, VB.
... Bias police, pressure. Applicant: Daini Seikosha Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 電流制御用素子として働く複数個のMOS トランジス
タと、これらのMOS )ランジスタに一定のバイアス
電圧を供給する回路と、発振・分周回路とを備え、前記
MO8)ランジヌタのうちの所要のMQ日トランジスタ
のみを1′舅択的に前配発撮・分周回路の電源供給路に
接続しうるようにしたことを特徴とするトリミング1J
能な電子時計0
It is equipped with a plurality of MOS transistors that serve as current control elements, a circuit that supplies a constant bias voltage to these MOS transistors, and an oscillation/frequency dividing circuit, and is equipped with a plurality of MOS transistors that function as current control elements, a circuit that supplies a constant bias voltage to these MOS transistors, and an oscillation/frequency dividing circuit. Trimming 1J is characterized in that only 1' of the 1' side can be selectively connected to the power supply path of the pre-distribution shooting/frequency dividing circuit.
Functional electronic clock 0
JP9419482A 1982-06-01 1982-06-01 Electronic timepiece capable of trimming Granted JPS58210588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9419482A JPS58210588A (en) 1982-06-01 1982-06-01 Electronic timepiece capable of trimming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9419482A JPS58210588A (en) 1982-06-01 1982-06-01 Electronic timepiece capable of trimming

Publications (2)

Publication Number Publication Date
JPS58210588A true JPS58210588A (en) 1983-12-07
JPH0318157B2 JPH0318157B2 (en) 1991-03-11

Family

ID=14103485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9419482A Granted JPS58210588A (en) 1982-06-01 1982-06-01 Electronic timepiece capable of trimming

Country Status (1)

Country Link
JP (1) JPS58210588A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5214461A (en) * 1975-07-24 1977-02-03 Seiko Instr & Electronics Ltd Low electric power consumption electronic watch
JPS54109876A (en) * 1978-02-16 1979-08-28 Citizen Watch Co Ltd Electronic watch
JPS54154357A (en) * 1978-05-25 1979-12-05 Nippon Precision Circuits Electronic timepiece
JPS5712390A (en) * 1980-06-24 1982-01-22 Citizen Watch Co Ltd Electronic timepiece
JPS5769278A (en) * 1980-10-20 1982-04-27 Citizen Watch Co Ltd Quartz oscillation type electronic watch

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5214461A (en) * 1975-07-24 1977-02-03 Seiko Instr & Electronics Ltd Low electric power consumption electronic watch
JPS54109876A (en) * 1978-02-16 1979-08-28 Citizen Watch Co Ltd Electronic watch
JPS54154357A (en) * 1978-05-25 1979-12-05 Nippon Precision Circuits Electronic timepiece
JPS5712390A (en) * 1980-06-24 1982-01-22 Citizen Watch Co Ltd Electronic timepiece
JPS5769278A (en) * 1980-10-20 1982-04-27 Citizen Watch Co Ltd Quartz oscillation type electronic watch

Also Published As

Publication number Publication date
JPH0318157B2 (en) 1991-03-11

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