JPS58209128A - Mounting method for package of semiconductor integrated circuit chip - Google Patents
Mounting method for package of semiconductor integrated circuit chipInfo
- Publication number
- JPS58209128A JPS58209128A JP57091218A JP9121882A JPS58209128A JP S58209128 A JPS58209128 A JP S58209128A JP 57091218 A JP57091218 A JP 57091218A JP 9121882 A JP9121882 A JP 9121882A JP S58209128 A JPS58209128 A JP S58209128A
- Authority
- JP
- Japan
- Prior art keywords
- jig
- ceramic substrate
- terminals
- substrate
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
Abstract
Description
【発明の詳細な説明】
本発明は半導体ICチップのセラミックパッケージ実装
工程間において・、セラミック基板をその治具から着脱
させることなく、上記工程を一貫して行う半導体ICチ
ップのパッケージ実装方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor IC chip package mounting method in which the above steps are performed consistently between the steps of semiconductor IC chip ceramic package mounting without attaching or detaching the ceramic substrate from the jig.
半導体ICチップはセラミック基板内に収納され、はん
だ溶誘接続、ツー)7クス除去洗浄、セラミックキャッ
プ気密封止等の各工程を経て、パッケージ実装工程を完
了する。この実装工程間において、セラミック基板はり
フロー治具に載置されるが、従来のす70−治具では上
記はんだ溶融接続工程後、セラミック基板をリフロー治
具より取外し、スラックス除去洗浄工程を行い、再びυ
70〜治具に載置して次工程を火流せねばならず、実装
工程間でセット、リセット寺のハンドリングが多く工程
の一負性を欠くのみならず、半導体ICyCツーの信頼
性等損う欠点を有していた。The semiconductor IC chip is housed in a ceramic substrate, and the package mounting process is completed after passing through various processes such as solder melt connection, cleaning to remove 7x, and hermetic sealing with a ceramic cap. During this mounting process, the ceramic substrate beam is placed on a flow jig, but in the conventional Su70 jig, after the solder melting and connection process, the ceramic board is removed from the reflow jig, and a slack removal cleaning process is performed. υ again
70~ It is necessary to place it on a jig and carry out the next process, and there is a lot of setting and resetting handling between mounting processes, which not only lacks the uniqueness of the process, but also impairs the reliability of the semiconductor ICyC2. It had drawbacks.
すなわち、第1図に示す如く、半導体ICチップ1(以
下IC′tツブと称呼する)は上方側を開放する箱体状
のセラミック基板2内に収納される。That is, as shown in FIG. 1, a semiconductor IC chip 1 (hereinafter referred to as an IC't tube) is housed in a box-shaped ceramic substrate 2 whose upper side is open.
セラミック基板2の両端面側には、これに治って複数個
の端子9が設けられ、これ等の端子9はセラミック基板
2の底面端部から延出している。A plurality of terminals 9 are provided on both end surfaces of the ceramic substrate 2, and these terminals 9 extend from the bottom end of the ceramic substrate 2.
従来、セラミック基板2を支持するりフロー治具6とし
ては、セラミツク基板20両側面に設けられた端子9間
距離Pよりやや小さ因横幅を形成よるチャンネル状のも
のが用いられ、セラミック夏板2はこのリフ・−治具の
上面側にその底面を載置されると共に、端子9間でリフ
ロー治具6の上記横幅を挾持するようにして支持される
。従って、リフロー治具6とセラミック基板2およびそ
の端子9間とは密接した状態に係合される。Conventionally, as the flow jig 6 for supporting the ceramic substrate 2, a channel-shaped one having a width slightly smaller than the distance P between the terminals 9 provided on both sides of the ceramic substrate 20 has been used. The bottom surface of the reflow jig 6 is placed on the upper surface side of the reflow jig 6, and the reflow jig 6 is supported so as to sandwich the width of the reflow jig 6 between the terminals 9. Therefore, the reflow jig 6 and the ceramic substrate 2 and its terminals 9 are closely engaged.
第2図に下す如く、ICチップ1には、はんだボール4
が形成されると共に、セラミック基板2側にもはんだペ
デスタル3が形成されている。As shown in FIG. 2, there are solder balls 4 on the IC chip 1.
is formed, and a solder pedestal 3 is also formed on the ceramic substrate 2 side.
まず、チップダイホンダ−等を用い、セラミック基板2
のはんだペデスタル3にICチップ1のはんだホール4
を仮付けする。次に、セラミック基板2をト記リフロー
治具6に載置し、連続型はんだリフロー炉等によシはん
だ溶融接続を行う。First, using a chip die Honda etc., the ceramic substrate 2 is
Solder hole 4 of IC chip 1 on solder pedestal 3 of
Attach temporarily. Next, the ceramic substrate 2 is placed on the reflow jig 6 described above, and solder melting connection is performed in a continuous solder reflow oven or the like.
次に、はんだ溶融接続によって生じたフラックスを除去
することになるが、上記の如く、セラミック基板2とす
70−治具6とは密接しているので、そのままではフラ
ックスを除去できない。そこで。Next, the flux generated by the solder melt connection is removed, but as described above, the ceramic substrate 2 and the jig 70-6 are in close contact with each other, so the flux cannot be removed as it is. Therefore.
セラミック基板2をリフロー治具6から取外し、その後
、フラックス除去洗浄を行う。次に、セラミック基板を
乾燥後、再びセラミック基板2をリフロー治具6に載W
/をする。The ceramic substrate 2 is removed from the reflow jig 6, and then cleaned to remove flux. Next, after drying the ceramic substrate, the ceramic substrate 2 is placed on the reflow jig 6 again.
/do.
次に、セラミック基板2の開放側の気密封止パターン部
5に図示していないセラミックキャップを載せ、ICテ
ップ1のはんだ浴融接続工程と同様に連続型リフロー炉
にて、はんだによりキャップ気密封止工程を行ない、セ
ラミツクツくツケージ実装工程を完了する。Next, a ceramic cap (not shown) is placed on the hermetic sealing pattern part 5 on the open side of the ceramic substrate 2, and the cap is hermetically sealed with solder in a continuous reflow oven in the same way as the solder bath fusion splicing process in IC step 1. A stop process is performed to complete the ceramic shoe cage mounting process.
以上のパッケージ実装工程l二おいて、上記の如く、リ
ンロー治$6へのセット、リセット等のノ九ンドリンク
が多く、工程の一貫性を匙し、生産性向上、作業効率向
上に問題を生ずるのみならず、上記ハンドリング中にI
Cチップに直接触れる機会が多くなり、半導体ICの特
性不良、その信頼性および寿命の劣化等の問題点が生じ
ていた。In the above package mounting process, as mentioned above, there are many links such as setting and resetting to Linroji $6, which improves the consistency of the process and causes problems in improving productivity and work efficiency. Not only does it occur, but also I
Opportunities for direct contact with C chips have increased, leading to problems such as poor characteristics of semiconductor ICs and deterioration of their reliability and life.
本発明は上記の問題点を解決すべく創案されたものであ
り、その目的はセラミックパッケージ実装工程間におけ
るー・ンドリンク動作をなくし、半導体ICパックージ
の製造歩留りを向上および製造工数の低減を可能とする
と共に、その信頼性および寿命を向上し得る半導体IC
チップのパッケージ実装方法を提供することにある。The present invention was devised to solve the above-mentioned problems, and its purpose is to eliminate the link operation between ceramic package mounting processes, improve the manufacturing yield of semiconductor IC packages, and reduce the manufacturing man-hours. Semiconductor IC that can improve reliability and lifespan
The purpose of the present invention is to provide a method for mounting a chip package.
本発明は上記の目的を達成4−るために、セラミック基
板を幅広のスリットの形成された治具上に載置し、セラ
ミック基板に形成され、その端部から延出する端子を上
6ビスリット間に挿入し、上記セラミック基板を上記治
具により、上記端子を懸吊した状態で支持し、パッケー
ジ実装工程を一賞して行うようにした半導体ICチップ
のパッケージ実装方法を特徴としたものである。In order to achieve the above-mentioned object, the present invention places a ceramic substrate on a jig in which wide slits are formed, and connects terminals formed on the ceramic substrate and extending from the ends thereof with six bislits. The semiconductor IC chip package mounting method is characterized in that the ceramic substrate is inserted between the terminals and the terminals are supported in a suspended state by the jig, and the package mounting process is carried out in one step. be.
以下、本発明の一実施例を図に基づき説明する。Hereinafter, one embodiment of the present invention will be described based on the drawings.
まず、本実施例の概要をa明する。First, an outline of this embodiment will be explained.
第3図に示す如く、治具7の上面には幅広のスリット8
が形成され、セラミック基板2の端子9が緩挿しうるよ
うになってhる。ICチップ1の仮付の終ったセラミッ
ク基板2を上6ピ治具7に載置すると共に、端子9をス
リット8内に挿入し、治具7によりセラミック基板を端
子9を懸吊し之状態で支持する。この状態で、上dとの
如くはんだ浴融接続工程を終了する。次に7ラツクス除
去洗浄工程は、治具7にスリット8が形成されている之
め、セラミック基板2を治具7上に載#(たままで7ラ
ツクス除去洗浄か行われる。従って、セット、リセット
のハンドリングは除かれる。そして、引続きキャップ気
密封止工程をそのま−fの状態で行ないパッケージ実装
工程を終了Tる。As shown in FIG. 3, there is a wide slit 8 on the top surface of the jig 7.
is formed, and the terminals 9 of the ceramic substrate 2 can be loosely inserted. The ceramic substrate 2 on which the IC chip 1 has been temporarily attached is placed on the upper 6-pin jig 7, the terminals 9 are inserted into the slits 8, and the terminals 9 of the ceramic substrate are suspended by the jig 7. I support it. In this state, the solder bath fusion splicing process is completed as shown in d above. Next, in the 7 lux removal cleaning process, since the slit 8 is formed in the jig 7, the 7 lux removal cleaning process is performed while the ceramic substrate 2 is placed on the jig 7. Then, the cap hermetic sealing step is performed in the same state as shown in FIG. 3, and the package mounting step is completed.
次に、本実施例を更に詳しく説明する。Next, this embodiment will be explained in more detail.
第3図に示す如く、治具7は熱伝導性が良く、腐食性に
凌れた金属、例えばアルミニウムの如き板部材をチャン
ネル状にしたものから形成され。As shown in FIG. 3, the jig 7 is made of a metal having good thermal conductivity and excellent corrosion resistance, such as a plate member such as aluminum, which is formed into a channel shape.
その上面側I/′i11数個のセラミック基板2を載置
し得るように幅広に形成されている。治具7の上面板7
aには複数個のスリット8が上面板7aの板厚を貰通し
、並設されて^る。そして、相隣接するスリット8間の
ピノfLは第1図に示すセラミック基板2の端子9間距
離Pとほぼ等しい寸法に形成される。又、スリット8の
幅すは、幅広に形成され、上記端子9が緩挿されるのみ
ならず、端子9間距離Pの異った他のセラミック基板2
にも共用し得るように形成されている。又、治具7の上
面板7aを支承する側面板7bの高さ寸法!は第1図に
示す端子9のセラミック基板2の端部からの延出長mよ
り高く形成されている。The upper surface side I/'i11 is formed wide so that several ceramic substrates 2 can be placed thereon. Top plate 7 of jig 7
A plurality of slits 8 pass through the thickness of the upper surface plate 7a and are arranged in parallel. The pinot fL between the adjacent slits 8 is formed to have a dimension substantially equal to the distance P between the terminals 9 of the ceramic substrate 2 shown in FIG. Further, the width of the slit 8 is formed wide, so that the terminal 9 is not only inserted loosely, but also other ceramic substrates 2 with different distances P between the terminals 9 are inserted.
It is designed so that it can be shared with other people. Also, the height dimension of the side plate 7b that supports the top plate 7a of the jig 7! is formed higher than the extension length m of the terminal 9 from the end of the ceramic substrate 2 shown in FIG.
ICチップ1をはんだ仮付した複数個のセラミック基板
2は、上記の延出する端子9をスリット8内に挿入した
状態で、治具7の上面板7aにより、その底面側を支持
される。従って、セラミック基板2は端子9を懸吊した
状態で治具7に載置される、この状態で連続型はんだリ
フロー炉等によりはんだ浴融接続工程が行われる。次に
、フラックス除去洗浄工程においては、スリット8を介
して、フラックス除去用洗浄液等が進入し、かつ、スリ
ット8が幅広のためセラミック基板2はスリット8内を
自由移動し得るため、セラミック基板2は治具7に載置
したままの状態で、7ラツクスの除去洗浄が行われる。A plurality of ceramic substrates 2 to which IC chips 1 are temporarily soldered are supported on their bottom sides by the top plate 7a of the jig 7, with the above-mentioned extending terminals 9 inserted into the slits 8. Therefore, the ceramic substrate 2 is placed on the jig 7 with the terminals 9 suspended, and in this state, a solder bath fusion splicing process is performed in a continuous solder reflow oven or the like. Next, in the flux removal cleaning step, the flux removal cleaning liquid etc. enters through the slit 8, and since the slit 8 is wide, the ceramic substrate 2 can move freely within the slit 8. While still placed on the jig 7, 7 lux removal cleaning is performed.
従って、従来技術の如く、セット替えを必要とせず、I
Cチップ1やセラミック基板2に直接接触する機会が生
じなめ0次に、セラミック基板2を冶JJ 7で支持し
た状態で乾燥工程後、上記の如く、連続型リフロー炉等
によりキャップ気密封止工程が行われ、rc”yツブの
パッケージ実装工程を完了する。Therefore, unlike the prior art, there is no need to change the set, and the I
After a drying process with the ceramic substrate 2 supported by JJ 7, where there is no chance of direct contact with the C chip 1 or the ceramic substrate 2, a cap hermetic sealing process is performed using a continuous reflow oven or the like as described above. is carried out, and the package mounting process of the rc"y tube is completed.
上Bピ実施例において、治具7のスリット8は端子9間
距離Pに対応するピッチLを有するものとしたが、端子
9がセラミック基板2の片側のみの場合、端子9間距@
pが一定でない場合等に応じ、適宜の形状、寸法のスリ
ット8としても構わない。In the upper B example, the slits 8 of the jig 7 had a pitch L corresponding to the distance P between the terminals 9, but if the terminals 9 are only on one side of the ceramic substrate 2, the distance between the terminals 9 @
Depending on the case where p is not constant, the slit 8 may have an appropriate shape and size.
又、治具7は第5図の如く四角形状のチャンネルでなく
ともよい。又、複数列のスリット8もそれぞれ並設され
たものでなくともよい。Furthermore, the jig 7 does not have to be a rectangular channel as shown in FIG. Further, the plurality of rows of slits 8 may not be arranged in parallel.
以上の説明によって明らかの如く、本発明によれば、I
Cチップのパッケージ実装工程を通じてセラミック基板
等のノ・ンドリング動作が除去されるので、半導体IC
パッケージの製造歩留シ向上と、製造工数の低減ができ
ると共に、その信頼性および寿命を向上し得る効果が上
けられる。As is clear from the above explanation, according to the present invention, I
Since the non-driving operation of ceramic substrates, etc. is eliminated through the C chip package mounting process, semiconductor IC
The production yield of the package can be improved, the number of manufacturing steps can be reduced, and the reliability and life of the package can be improved.
第1図は従来技術の半導体ICパッケージ実装に用いら
いられる治具等を示す斜視図、第2図は半導体ICチッ
プとセラミック基板のはんだ仮付状態を示′を説明図、
第3図は本発明一実施例の/%ッケージ実装に用いられ
る治具を示す斜視図である。
1・・・半導体ICチップ、2・・・セラミック基板、
7・・・治具、 8・・・スリット、 9・・・端
子。
才 / I1%1Fig. 1 is a perspective view showing a jig etc. used in conventional semiconductor IC package mounting, Fig. 2 is an explanatory view showing a state in which a semiconductor IC chip and a ceramic substrate are temporarily soldered;
FIG. 3 is a perspective view showing a jig used for package mounting according to an embodiment of the present invention. 1... Semiconductor IC chip, 2... Ceramic substrate,
7...Jig, 8...Slit, 9...Terminal. talent / I1%1
Claims (1)
だ溶融接続、7ラツクス除去洗浄およびキャップ気密封
止等の工程を行う半導体ICチップのパッケージ実装方
法において、上記セラミック基板を載置すると共に、該
セラミック基板に設けられ、その端部から延出する端子
が緩挿される幅広のスリットを形成する治具を設け、該
治具に上記セラミック基板を、上記端子を懸吊した状態
で支持し、上記セラミック基板を±gピ治治具支持した
まま上記工程を一貫して行うことを特徴とする半導体I
Cチップのパッケージ実装方法。In a semiconductor IC chip package mounting method in which a semiconductor I (J-tube is housed in a ceramic substrate and processes such as solder melting connection, 7 lux removal cleaning and cap hermetic sealing are carried out, the ceramic substrate is placed and A jig is provided on the ceramic substrate to form a wide slit into which a terminal extending from an end of the ceramic substrate is loosely inserted, and the ceramic substrate is supported on the jig with the terminal suspended therein; Semiconductor I characterized in that the above steps are consistently performed while the above ceramic substrate is supported by a ±g pip jig.
C-chip package mounting method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57091218A JPS58209128A (en) | 1982-05-31 | 1982-05-31 | Mounting method for package of semiconductor integrated circuit chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57091218A JPS58209128A (en) | 1982-05-31 | 1982-05-31 | Mounting method for package of semiconductor integrated circuit chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58209128A true JPS58209128A (en) | 1983-12-06 |
Family
ID=14020276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57091218A Pending JPS58209128A (en) | 1982-05-31 | 1982-05-31 | Mounting method for package of semiconductor integrated circuit chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58209128A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5565008A (en) * | 1990-07-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of raising a semiconductor device out of a pallet using a positioning rod |
CN101958230A (en) * | 2009-07-20 | 2011-01-26 | 昆山丘钛微电子科技有限公司 | Substrate-pressing jig |
-
1982
- 1982-05-31 JP JP57091218A patent/JPS58209128A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5565008A (en) * | 1990-07-17 | 1996-10-15 | Mitsubishi Denki Kabushiki Kaisha | Process of raising a semiconductor device out of a pallet using a positioning rod |
CN101958230A (en) * | 2009-07-20 | 2011-01-26 | 昆山丘钛微电子科技有限公司 | Substrate-pressing jig |
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