JPS58207678A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To control lateral diffusion of impurity by selectively implanting ion into substrate with the gate pattern consisting of material having thermal expansion coefficient which is almost equal to that of semiconductor substrate and by forming gate electrode on the exposed substrate. CONSTITUTION:A mask 12 having aperture is provided on a semi-insulating GaAs substrate 11 and ion is implanted to the region 13 having the Si gate. Next, the mask 12 is removed and a gate pattern 14 is formed by aluminum nitride having thermal coefficient which is almost equal to that of the GaAs substrate 11. Silicon is implanted in order to form high impurity concentration region 16 using the gate pattern 14 and mask 15 as the mask. Thereafter, the mask 15 is removed and SiO2 film 17 is provided, and the SiO2 film 17 where implanted ion is activated is removed. Next, an oxide insulating film 18 is formed, the insulating film 18 is removed until the gate pattern 14 is exposed by plasma etching. Thereafter, the source and drain electrodes 19 are formed. Then, the gate pattern 14 is selectively removed by etching, an aperture of gate pattern is provided on the insulating film 18 and the gate electrode 20 is formed. Thereby, the gate region can be formed with good controllability with restricted lateral diffusion of impurity.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in a method for manufacturing a gate region of a semiconductor device, particularly a Schottky barrier type wide-effect transistor.

(b) Technical Background It is believed that further improvements in the performance and cost performance of information processing devices are directly dependent on the semiconductor devices used in them, and improvements in the speed and power consumption of logical arithmetic devices and the reduction in power consumption of memory devices are essential. Larger capacity is being strongly promoted.

Currently, rough silicon (81) semiconductor devices are in practical use, but the speedup of Sl semiconductor devices is limited by the physical properties of Sl, such as carrier mobility in low electric fields and saturation drift velocity in strong electric fields. Therefore, in parallel with the development of ultra-large scale integrated circuit devices using St, gallium arsenide (GaAs) and other compound semiconductors were used as a substitute for Sl.
Efforts are being made to realize semiconductor devices with high speed and low power consumption that would otherwise be unattainable.

Due to the short lifetime of minority carriers in compound semiconductors, field effect transistors (hereinafter referred to as FETs) are currently the main target of development. Utilizing the advantage that the capacitance to ground can be reduced by 1'', the open-circuit key barrier type FET or junction gate type FET has become the mainstay.

(c) Conventional technology and problems In field effect transistors (FETs), gate electrodes are masked to increase speed and reduce power consumption by shortening the gate length, and to streamline the manufacturing process. Self-alignment line (5el) where impurity ions are implanted as part of the source and drain region formation
f alignment) method is extremely effective.

A conventional method for manufacturing a shut-key barrier type GaAs FET by the self-line method will be described with reference to cross-sectional views shown in FIGS. 1(a) to 1(e).

First, as shown in FIG. 1(a), a mask 2 having an opening made of aluminum nitride (CMN') or silicon dioxide (SiO), etc. is provided on a semi-insulating GaAs substrate 1, and the opening is Ions such as silicon (Sl') are implanted into the region where the gate active region 3 is to be provided.

Next, as shown in FIG. 1(b), the mask 2 is removed and the AA
A protective film 4 made of N or 5iot is provided, and the temperature is 8.
By performing a heat treatment at 50° C. for about 20 minutes, the implanted impurities are sufficiently activated to form the active region 3.

Next, as shown in FIG. 3(e), a part of the protective film 4 is removed and a high melting point metal such as titanium is deposited on the central part of the active region 3.
A gate electrode 5 is provided using tungsten silicide (TiWSi) or the like. After that, the source and drain 6 are formed using the gate electrode 5 and the remaining protective film 4 as a mask.
Ions such as St are implanted into the region.

After removing the d-retaining film 4, tap the MN as shown in FIG. 1(d).
Alternatively, provide a protective film 7 of 5 lots, etc., and connect the gate voltage @
In order to reduce metallurgical reactions, stress, etc. at the interface between 5 and the GaAs semiconductor substrate 1, the temperature 7 is relatively low.
Heat treatment is performed at about 50 (° C.) for about 20 minutes.

Next, as shown in FIG. 1(e), the protective film 7 is removed and, for example, gold/germanium (A) is deposited on the source and drain regions.
uGe) alloy/gold (Au) or the like is deposited, and by heat treatment after patterning, an alloy of the GaAs semiconductor and the AuGe or the like is formed to form the source and drain electrodes 8 in ohmic contact.

In the prior art example, the gate electrode 5 is formed of a high-melting point metal, especially its silicon compound 'rtwsi, etc., so that the gate/electrode 5 and the GaAs semiconductor substrate 1 are bonded during heat treatment to activate the implanted impurities. This suppresses metallurgical reactions at the interface with However, the difference in thermal expansion coefficient between the GaA+s substrate 1 and the gate electrode 5 (the GaAsQ thermal expansion coefficient is 7X 10-'Cdeg-
':], The thermal expansion coefficient of TiWSt is about 3 compared to that of SI.
X 10-'(deg-'), which is considered to be substantially closer to that than deg-', generates stress at this interface, and the lateral diffusion of impurities becomes particularly significant in the portion below the gate electrode 5. For this reason, the high impurity concentration region invades the region serving as the gate, increasing the parasitic capacitance, and when the gate length is set to, for example, 1 [μ] or less, it is possible that the source and drain may be short-circuited. FET due to this lateral diffusion
Difficulties in controlling characteristics are particularly important for enhancers (en).
-hancement) is significant in type FIIET.

A method has also been proposed in which the high impurity concentration regions to be used as sources and drains are formed by diffusion from the surface of the semiconductor substrate instead of the ion implantation and activation process described above, but this method does not solve the problem described above due to lateral diffusion of impurities. There is no difference in the accompanying points, and in order to solve this problem, it is necessary to invent a new manufacturing method.

(d) Object of the Invention The present invention provides a manufacturing method for a Schottky barrier field effect transistor that controls the lateral diffusion of implanted impurities that inhibit alignment between the gate electrode and the source and drain regions. purpose.

(e) Structure of the Invention The object of the present invention is to selectively form, on a semiconductor substrate, a gate pattern made of a material having a coefficient of thermal expansion substantially equal to that of the semiconductor substrate; and, using the gate pattern as a mask, This is accomplished by including the steps of selectively implanting ions into the semiconductor substrate, and forming a gate electrode on the semiconductor substrate exposed by removing the gate pattern.

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

FIGS. 2(a) to 2(h) are cross-sectional views showing an embodiment of the present invention regarding a GaAs Schottky barrier type FET.

As shown in FIG. 2, a mask 12 having an opening is provided on a semi-insulating GaAs substrate 11. For example, 81 is replaced with 60 (Ke
A region 13 to be used as a gate is passed through the opening of the mask 12 at a dose of 1xlO12 (ctm-') 8 degrees at V).
Inject into.

Next, as shown in FIG. 2(b), <,F]iJ mask 1
After removing the gate pattern 14, the gate pattern 14 is made of a material such as aluminum anion (AAN) having a coefficient of thermal expansion approximately equal to that of the GaAs substrate 11, as will be described in detail later, to a thickness of approximately 0.5 μm. It is formed on the base plate 11. At this time, the thermal expansion coefficient of GaAg is approximately 7 x 1
0-'(deg-') + that of AIN is approximately 4.8-
5.6 X 1 cr'(deg-'). This pattern 14 determines the pattern of the rectifying contact portion of the gate electrode, and the pattern is formed by providing an etching mask using the phosphorography method. A reactive ion etching method using carbon tetrafluoride (CF) or the like is used in which the gas pressure is adjusted so as to be perpendicular to the surface.

Using both the gate pattern 14 and the mask 15 made of a resist or the like as a mask, for example, Si 18
It is implanted at a dose of I x 10'' [-1 at 0 (KeV, 1).

In this embodiment, after the ion implantation is completed and the mask 1 is
After removing 5, as shown in Figure 2(e), chemical vapor deposition (
The gate pattern 14 is
A 5iot film 17 is provided on a substrate 11 containing
(° C.) for about 2 hours and 20 minutes, and may be carried out at an appropriate time before electrode formation as described after the main heat treatment.

Next, as shown in FIG. 2(d), the silicon oxide insulating film 1
8 is formed, and an example of the forming method is as follows.

Silicon hydroxide (St(OH)+) or its substituted product (RnSi(OH)+-nj, where RB organic 4
. By applying the coating at a high speed, the coating is applied so that the gate pattern 14 and the semiconductor substrate 11 are connected with a gentle slope. Next, heat treatment is performed at a temperature of about 300 (°C) to 400 (°C) for, for example, about 30 minutes, thereby causing condensation such as 81(OH)4→S i Ox + 2Ht O and S10. Three-dimensional polymerization between them is performed to form a silicon oxide insulating film 18.

When forming this insulating film 18, the liquid phase Si is transferred to the gate pattern 14 due to the surface tension of the liquid phase 8101 itself.
It has good layering properties due to the adhesion of O.
The insulating film formed by the D method grows on the gate pattern 14 to a thickness equal to or greater than that on the base 8i11 surface, but the film thickness on the gate pattern 14 can be made thinner. The difference in film thickness, that is, the inclined portion of the insulating film 18 can be adjusted by the viscosity of the solution and the rotation speed during spin coating.

Subsequently, as shown in FIG. 2(ct), plasma etching using, for example, methane trifluoride (CHF) is performed from above the insulating film 18 to remove the insulating film 18 until the gate pattern 14 is exposed.

Thereafter, source and drain electrodes 19 are formed as shown in FIG. 2(f). The formation method is, for example, by forming an opening in the insulating film 18 using a conventional technique, then vapor-depositing or sputtering a gold-germanium (AuGe) alloy and gold (Au), patterning it by a lift-off method, etc., and then heating it at a temperature of 450 ('C). Heat treatment is performed for approximately 2 hours and 90 seconds to form ohmic contact. Note that nickel (N1) may be inserted between the AuGe and the Burmese.

Next, as shown in FIG. 2C, the gate pattern 14 is selectively etched away using heated phosphoric acid (Hs PO4) or the like. As a result, an opening of a gate pattern is provided in the insulating film 18.

Subsequently, as shown in FIG. 2(h), a gate electrode 20 is formed. In this example, titanium, platinum, gold (TiP
tAu) is deposited and patterned using a lift-off method.

It is also possible to form the gate electrode 20 before the source and drain electrodes 19, and in this case, the method for forming each electrode may be the same as described above, but in this embodiment, the source and drain electrodes 19 temperature 450 [℃
Since the gate electrode 20 is formed after the alloying heat treatment in ), it is possible to use III/JrTiPtAu as the gate metal, for which the upper limit of heating is about 400 (° C.).

In the embodiments described above, the gate pattern 14 was formed using AIN, but the material for forming the gate pattern 14 was (a) as described above during the heat treatment for activating the implanted impurities. In order to suppress stress at the semiconductor interface, the thermal expansion coefficient should be as close as possible to the thermal expansion coefficient of the semiconductor, (b) no chemical reaction should occur with the semiconductor during this heat treatment, and (c) The silicon oxide insulating film 18 of the above embodiment or an insulating film made of another material for the same purpose can be selectively removed by etching, and there is no adverse effect due to knock-on during 6Y pure ion implantation. and (e) be advantageous in terms of workability and cost.

Examples of materials suitable for these conditions include silicon nitride (SisN+), tantalum nitride (TaN), boron nitride (BN), and niobium nitride (SisN+) in addition to AiN used in the examples.
As for GaAs, aluminum, gallium, arsenic (AtGaAs), etc. grown epitaxially thereon can be mentioned.

Further, although the above embodiment uses a GaAs compound semiconductor, the present invention can be practiced in the same manner with a trench type field effect transistor using other semiconductor materials.

Note that the silicon oxide insulating film used in the present invention has a gentle slope when there is a sudden step difference due to an electrode or the like in the underlying layer. It has the effect of preventing disorders.

(g) Effects of the Invention According to the present invention, as explained above, in a Schottky barrier FET, impurity ions are implanted in a self-aligned manner in the pattern of the rectifying contact portion of the gate electrode,
However, by suppressing the lateral diffusion of impurities during the heat treatment for impurity activation, it becomes possible to form the gate HJi region with good controllability, and the gate length can be shortened. Gate! Since it is now possible to select the electrode material without being restricted by heat treatment conditions, and improvements such as reduction in resistivity can be made, semiconductor devices including FETs can be made faster, have lower power consumption, and have higher integration. becomes possible.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing examples of prior art;
8g2 Figures (a) to (h) are cross-sectional views showing embodiments of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 3 is a gate active region, 5 is a gate electrode, 6 is a source and drain, and 8 is a semi-insulating GaAs substrate.
11 is a semi-insulating GaAs substrate, 13 is a gate region, 14 is a gate pattern, 16 is a source and drain high impurity concentration region, 18 is a silicon oxide insulating film, 19 is a source and drain electrode, 20 indicates the gate electrode. Figure 1 i, l l l I i Figure 2 I I 11

Claims (1)

[Claims] Manufacturing a semiconductor device, which includes the steps of selectively implanting ions into the semiconductor substrate, and forming a gate electrode on the semiconductor substrate exposed by removing the gate pattern. Method.