JPS582061A - Cmos integrated circuit - Google Patents

Cmos integrated circuit

Info

Publication number
JPS582061A
JPS582061A JP56100076A JP10007681A JPS582061A JP S582061 A JPS582061 A JP S582061A JP 56100076 A JP56100076 A JP 56100076A JP 10007681 A JP10007681 A JP 10007681A JP S582061 A JPS582061 A JP S582061A
Authority
JP
Japan
Prior art keywords
potential
substrate
type
integrated circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56100076A
Other languages
Japanese (ja)
Inventor
Yasutaka Nakasaki
中崎　泰貴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56100076A priority Critical patent/JPS582061A/en
Publication of JPS582061A publication Critical patent/JPS582061A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the mobility due to high integration by a method wherein a substrate bias circuit, with which the substrate potential of a P type MOSFET is brought up higher than the positive-side potential of the power source of the IC and the substrate potential of an N type MOSFET is brought down lower than the negative potential of the power source of the IC, is provided. CONSTITUTION:The potential, which is lower than the negative potential of the power source, is applied to the N type region of a substrate 401 using a substrate bias circuit, and the potential which is higher than the positive potential of the power source is applied to the P type region of a substrate 402. Accordingly, when the threshold potential of MOSFET is increased, the substrate density can be reduced and the modility can be increased. Also, as it is well known in general, the substrate bias circuit is used to apply a current, through the intermediary of a diode, to the substrate by shifting the biasing point and by having the oscillation signal of an oscillation circuit pass through a capacitor.

Description

【発明の詳細な説明】 本発明は、ＣＭＯ＆集積回路に関し、その集゛−回路の
高速化に関す為。従来ＣＭＯＢ集積回路に於いてけ、Ｐ
ｆｉＭ　ＯＢ　Ｆ　Ｉｆｆ　Ｔ　ノｉ［電位ｔｊ、ｔｍ
の正電位と同電位にし％１−ｔｔＭ型ＭＯ８ＦＥＴの基
板電位は、電源の負電位と同電位であった。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to CMO & integrated circuits, and to speeding up the integrated circuits. In conventional CMOB integrated circuits, P
fiM OB F Iff T noi [potential tj, tm
The substrate potential of the %1-ttM MO8FET was the same as the negative potential of the power supply.

これを１１１図のＣＭＯＢインバータ回路で説明すると
、１０１のＮ１１基Ｗａ、　皺基板上のｌ”ｇＭＯ８ν
Ｉｆ　Ｔ　１０７のソース電位１０３と同電位で電源の
正電位に接続し、１０２０ＰＩＮ拡散層（ｉｇｕｏｓｙ
ｌテ１０８の基板）は、該領域上の１１１１ＭＯ８ア丘
テ１０８のソース電位１０６と同電位で負電位に接続さ
れて込た。To explain this using the CMOB inverter circuit in Figure 111, 101 N11 groups Wa, l”gMO8ν on a wrinkled substrate.
Connected to the positive potential of the power supply at the same potential as the source potential 103 of IfT 107, and connected to the 1020 PIN diffusion layer (iguosy
The substrate of the first electrode 108) was connected to a negative potential at the same potential as the source potential 106 of the 1111 MO8 electrode 108 on the region.

これは従来の０Ｍ０８回路の一般的結線方法であゐが、
Ｍｏｌν１！が高集積さｆＬｌｌそのチャンネルが短か
くなるに従って、短チャンネル化にＬる高速化の効果が
生じＫ＜＜なゐ傾向が、現れてきた。これＦｉ、同一基
板濃度でチャ木ル長（Ｌｇ／／）を短かくしていくと、
そのＩＦＩＴの閾値電圧（ＶＴＲ）が低くなりことによ
る。（第２図にこの様子２− を示す、）つまり、　ＶＴＲが低くなるたぬに、　ＶＴ
Ｒを上げるには基板濃囲を高くな行れげならなＬ／′ｈ
。This is the general wiring method for the conventional 0M08 circuit,
Molν1! As the integration of fLll becomes higher and the channel becomes shorter, the shortening of the channel has the effect of increasing the speed L, and a tendency has appeared where K<<. This is Fi, if we shorten the wood length (Lg//) at the same substrate concentration,
This is because the threshold voltage (VTR) of the IFIT becomes low. (Figure 2 shows this situation.) In other words, as the VTR becomes lower, the VT
To increase R, the substrate concentration must be increased L/'h
.

しかし基板濃Ｋを上げると、荷電担体の表面移動層が下
がり結果的には、素子の動作速度が、その短チヤンネル
化程には効果が出ないためである。However, when the substrate concentration K is increased, the surface movement layer of charge carriers decreases, and as a result, the operating speed of the device is not as effective as the shortening of the channel.

本発明は、かかる高集積化による移動度の低下を防、ぐ
ために考案されたものである。The present invention was devised to prevent such a decrease in mobility due to high integration.

本発明では、第４図に示す基板バイアス発生回路により
４０１のＭ型基板には電源の負電位より低込電位と印加
し、４０２のＰ型領域には電源の正電位より１！Ａ−電
位を印加するものである。このよう和すると！５図に示
すが如（ＭＯ８１Ｆ１ｉＳテの１ｌｉ１箇電位が募〈な
０２基板＋１１ｆを低くすることができ、移動度を高く
できるものである。また第４図の基板バイアス回路は、
工（知られているように１発振回路の発振信号を容量を
通すことでバイアス点をシフトしダイオードを介して基
板に電流を流すものである。これは−例であって他にも
種々の（２）路があるが１本発明は、これらのｔ板バイ
アス論路をＣＭＯ＆集積回路のＰ型ＭＯ８Ｆ］！ｔＴの
基板３− ｂで、該ＣＭＯＢ集積回路を高速化するものである。特
に０Ｍ０１３回路は速質及び集積に、消脅電り等に優れ
た特性をもち、本発明を用する仁とにより更にすぐれｑ
、　ＣＭ　ＯＳ集積回路を提供できる。In the present invention, a lower potential than the negative potential of the power supply is applied to the M-type substrate 401 by the substrate bias generation circuit shown in FIG. 4, and a lower potential than the positive potential of the power supply is applied to the P-type region 402. A- potential is applied. When you sum it up like this! As shown in Fig. 5 (1li1 potential of MO81F1iS is low), it is possible to lower the 02 substrate + 11f and increase the mobility. Also, the substrate bias circuit of Fig. 4 is
(As is known, the oscillation signal of an oscillation circuit is passed through a capacitor to shift the bias point and cause current to flow through the board via the diode. This is just an example, and there are various other methods. (2) Although there are paths, the present invention is to increase the speed of the CMOB integrated circuit by connecting these T-plate bias logic circuits to the P-type MO8F]!tT substrate 3-b of the CMO & integrated circuit.Especially The 0M013 circuit has excellent characteristics such as speed, integration, and power consumption, and it can be made even better by using the present invention.
, can provide CMOS integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

Ｉｒ１図：従来の（：ＭＯＢインバーターの結縁方法を
示す図 第２図、第３図、ｆ１ｇ５図：ＭＯＥｉＰＩＴの％性図 第４図二本発明の構成を示す図 以　　　上 出願人　株式会社諏訪精工舎 代理人　弁理土量　上　　務 ４− 第２図 しｅｌｆ　　　　→４し ′−４３イ 羞脹飢−高 第４図 第６図　１Ir1 diagram: Conventional (: Diagram showing the connection method of MOB inverter. Figure 2, Figure 3, f1g5 diagram: % characteristic diagram of MOEiPIT. Figure 4.2 Diagram showing the configuration of the present invention. 4- Figure 2 Shielf →4 Shi'-43 I Humiliation Hunger-High Figure 4 Figure 6 1

Claims (1)

【特許請求の範囲】 １、　　ＰｇＭＯ８ＦＫ？とＷ型ＭＯ８Ｆｍ丁とが集積
化さｎて構反されるＣＭＯＢ集積回路に於いて、Ｐ型Ｍ
Ｏ８ＦＩｌｆテの基板電位を、集積回路の電源の正側電
位より高くし、かつＮ型ＭＯＢＦＩＴの基板電位を集積
−路の電源の負電位より低くする基板バイアス回路を儂
λたことを特１２１　トｆ　Ｌ　ＣＭＯ”　１％　ｆｌ
ｌ　ｍｌ　Ｗｒ　ｅ２、ＣＭＯＢインバータ回路と抵抗
、容量１から成る発振回路、Ｎ型拡散層とＰ型拡散層か
らなふダイオード、Ｐ型ＭＯ５ＦＩＴダ（＃−）”、　
　夏型ＭＯ８ＦＥＴダイオード、及び容量から構Ｊされ
る正電位基板バイアスｂｌ路と負電位基板２１７１回路
を同一基板上に構盾しｔことを特徴とする特許請求の範
囲第一項記載のＣＭＯＢ集積回路。 １−[Claims] 1. PgMO8FK? In a CMOB integrated circuit in which a W-type MO8Fm and a P-type M
It is noted that I have created a substrate bias circuit that makes the substrate potential of O8FIlf higher than the positive potential of the integrated circuit power supply and lowers the substrate potential of the N-type MOBFIT than the negative potential of the integrated circuit power supply. f L CMO” 1% fl
l ml Wr e2, an oscillation circuit consisting of a CMOB inverter circuit, a resistor, and a capacitance of 1, a diode consisting of an N-type diffusion layer and a P-type diffusion layer, a P-type MO5FIT da (#-)'',
CMOB integrated circuit according to claim 1, characterized in that a summer type MO8FET diode, a positive potential substrate bias line constructed from a capacitor, and a negative potential substrate 2171 circuit are constructed on the same substrate. . 1-
JP56100076A 1981-06-26 1981-06-26 Cmos integrated circuit Pending JPS582061A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56100076A JPS582061A (en) 1981-06-26 1981-06-26 Cmos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56100076A JPS582061A (en) 1981-06-26 1981-06-26 Cmos integrated circuit

Publications (1)

Publication Number Publication Date
JPS582061A true JPS582061A (en) 1983-01-07

Family

ID=14264351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56100076A Pending JPS582061A (en) 1981-06-26 1981-06-26 Cmos integrated circuit

Country Status (1)

Country Link
JP (1) JPS582061A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0116820A2 (en) * 1983-02-21 1984-08-29 Kabushiki Kaisha Toshiba Complementary MOS circuit
US4571505A (en) * 1983-11-16 1986-02-18 Inmos Corporation Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits
US4670668A (en) * 1985-05-09 1987-06-02 Advanced Micro Devices, Inc. Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up
US5043597A (en) * 1989-06-19 1991-08-27 Kabushiki Kaisha Toshiba Substrate bias generation circuit used in semiconductor integrated circuit
US5684321A (en) * 1994-11-10 1997-11-04 Kabushiki Kaisha Toshiba Semiconductor device having an input protection circuit
US5936282A (en) * 1994-04-13 1999-08-10 Kabushiki Kaisha Toshiba Semiconductor device having input protection circuit
US6094068A (en) * 1997-06-19 2000-07-25 Nec Corporation CMOS logic circuit and method of driving the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0116820A2 (en) * 1983-02-21 1984-08-29 Kabushiki Kaisha Toshiba Complementary MOS circuit
US4571505A (en) * 1983-11-16 1986-02-18 Inmos Corporation Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits
US4670668A (en) * 1985-05-09 1987-06-02 Advanced Micro Devices, Inc. Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up
US5043597A (en) * 1989-06-19 1991-08-27 Kabushiki Kaisha Toshiba Substrate bias generation circuit used in semiconductor integrated circuit
US5936282A (en) * 1994-04-13 1999-08-10 Kabushiki Kaisha Toshiba Semiconductor device having input protection circuit
US5684321A (en) * 1994-11-10 1997-11-04 Kabushiki Kaisha Toshiba Semiconductor device having an input protection circuit
US6094068A (en) * 1997-06-19 2000-07-25 Nec Corporation CMOS logic circuit and method of driving the same
DE19827454C2 (en) * 1997-06-19 2002-10-17 Nec Corp Logical CMOS circuit and driver method therefor

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