JPS58205994A - Non-volatile memory system - Google Patents
Non-volatile memory systemInfo
- Publication number
- JPS58205994A JPS58205994A JP57088292A JP8829282A JPS58205994A JP S58205994 A JPS58205994 A JP S58205994A JP 57088292 A JP57088292 A JP 57088292A JP 8829282 A JP8829282 A JP 8829282A JP S58205994 A JPS58205994 A JP S58205994A
- Authority
- JP
- Japan
- Prior art keywords
- volatile memory
- battery
- memory system
- power outage
- backup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はイく揮発性メモリシステムに関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to volatile memory systems.
従来の不揮発性メモリシステムを第1図に示す。A conventional nonvolatile memory system is shown in FIG.
図において、lは揮発性メモリであるダイナミックRA
M(以下DRAMと称する1、)、2は停電時にDRA
MIをバックブックするバックアップ用電池、3はDR
AMIのデータの伝送を行うCPUバスであるO
ト記装置の動作を第2図を用いて説明すると、通常時に
おいては、DRAt質1は図示しない通常電源によって
動作し、CPUバス3を介してデータの1き込みや読出
しが行われる。)DRAMlは揮発性であるため停電時
にその記憶データは全部破壊される3、そこで、時刻T
1において通常′電源が停電しその4圧が低下し7始め
るとバックアップ用電池2からI)RAMIへ電流が供
給されるようになる。このため、DRAMIのデータは
破壊されない。しかるに停電時間が゛長いと、例えば第
2図の時刻T、に示すようにバックアップ用電池2の容
量がなくなってその′電圧が低下し、D RA M 1
の記憶データは破壊される。このように従来の不揮発性
メモリシステムにおいては、電池容量より長い停電ンc
対してはメモリ内容の不揮発性を保つことができないと
いう欠点があった。In the figure, l is dynamic RA, which is volatile memory.
M (hereinafter referred to as DRAM 1 and 2) and 2 are DRAMs during power outage.
Backup battery to back up MI, 3 is DR
The operation of the device, which is the CPU bus that transmits AMI data, will be explained with reference to FIG. Writing and reading of data is performed. ) Since DRAM1 is volatile, all of its stored data will be destroyed in the event of a power outage3, so at time T
Normally, at 1, when the power supply is interrupted and the 4 voltage begins to drop, current is supplied from the backup battery 2 to I) RAMI. Therefore, the data in DRAMI is not destroyed. However, if the power outage is long, for example, as shown at time T in FIG. 2, the capacity of the backup battery 2 runs out and its voltage drops, causing the DRAM1
memory data will be destroyed. In this way, in conventional non-volatile memory systems, the power outage time c is longer than the battery capacity.
However, there was a drawback that the non-volatility of the memory contents could not be maintained.
本発明は上記の従来の欠点を除去するために成されたも
のであり、停電時に゛電池のエネルギでDRAMから不
揮発性メモリヘデ7夕を転送し、転送終了後自動的に電
池を切り離すことにより、少ない電池容量・であっても
長時間の停電にちして不揮発性を維持できる不揮発性メ
モリシスデムヲ提供することを目的とする。The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology.In the event of a power outage, data is transferred from the DRAM to the non-volatile memory using battery energy, and the battery is automatically disconnected after the transfer is completed. The purpose of the present invention is to provide a nonvolatile memory system that can maintain nonvolatility even after a long power outage even with a small battery capacity.
以下本発明の実姉1+lJを図面とともに説明する、。The real sister 1+lJ of the present invention will be explained below with reference to the drawings.
83.4図は本発明の第1の実施例を示し、4は不揮発
性メモリである磁気テープで、磁気テープ4は停゛一時
にDRA、Mlのデータを転送保存される4゜5は停電
時のデータ転送などを制御する汗電コントローラ、6は
AClooVの通常電源、7は通常電源6の出力を整流
する整流回路、8は整流回路7の出力電圧を調整する電
圧レギュレータで、電圧レギュレータ8の出力は電tO
R用ダイオード9を介してDRAMI、磁気テープ4お
よび停電コントローラ5に加えられる。loは電圧レギ
ュレータ8の出力と所定電圧を比較するコンパレータ、
11はリレーで、その接点11aは一端をバックアップ
用電池2に接続されるとともに他端は′電圧OR用ダイ
オード12を介してDRAMI、磁気テープ4および停
電コントローラ5に接続され、リレーのコイルllbは
バックアップ用電池2と停電コントローラ5との間に接
続される。。Figure 83.4 shows the first embodiment of the present invention, 4 is a magnetic tape which is a non-volatile memory, and the magnetic tape 4 is used to transfer and store DRA and M1 data at the same time. 6 is a normal power supply of AClooV, 7 is a rectifier circuit that rectifies the output of the normal power supply 6, 8 is a voltage regulator that adjusts the output voltage of the rectifier circuit 7, and voltage regulator 8 The output is electric tO
It is applied to the DRAMI, magnetic tape 4 and power failure controller 5 via the R diode 9. lo is a comparator that compares the output of the voltage regulator 8 with a predetermined voltage;
Reference numeral 11 denotes a relay, one end of which is connected to the backup battery 2, and the other end connected to the DRAMI, magnetic tape 4, and power outage controller 5 via a voltage OR diode 12, and the coil llb of the relay is It is connected between the backup battery 2 and the power outage controller 5. .
次に上ml装置の動作について説明する。まず、通常通
電中においては電圧レギュレータ8がら電圧が出力され
、この電圧がDRAMI、磁気テープ4および停電コン
トローラ5に供給される。次に通常電源6が停電になる
と電圧レギュレータ8からの出力電圧は低下する。コン
パレータ10は電圧レギュレータ8の出力が所定値以下
になったことを検知し、停電コントローラ5へ検知伯隻
を送る6、これによって、停電コントローラ5はff
’t ’tr感知し、リレーコイルllbに成流が流れ
るようにして接点11aをオンする。このため、 D
RA M I、磁気テープ4および停電コントローラ5
にはバソ・ クアツプ用電源2から給電が行わiする。Next, the operation of the upper ml device will be explained. First, during normal energization, a voltage is output from the voltage regulator 8, and this voltage is supplied to the DRAMI, the magnetic tape 4, and the power outage controller 5. Next, when the normal power supply 6 experiences a power outage, the output voltage from the voltage regulator 8 decreases. The comparator 10 detects that the output of the voltage regulator 8 has become below a predetermined value, and sends the detection signal to the power outage controller 5 6, whereby the power outage controller 5
't'tr is sensed, and the contact 11a is turned on by causing a current to flow through the relay coil llb. For this reason, D
RAM I, magnetic tape 4 and power outage controller 5
Power is supplied from the batho-cup power supply 2.
又停電コントローラ5からの指令によりDiζAMIに
記tはさバたデータが磁気テープ4に転送される。この
転送はバックアップ用′@i、池2のエネルギーを・こ
よりて行わノ1.る。転送が終了すると停電コントロー
ラaの作動によってリレーコイル11 b f流tし6
4Mcがしゃ断され、接点11aがオフとなる。このた
め、バックアップ用′也亀2からの給′(は浄土される
が、ガータは不揮発性メモリである磁気デ〜ゾ4に記憶
されているので破壊されることはない1、又、バックア
ップ用心也2がらの給電は停電になってからデータ転送
が終了するまでの短時間だけであるのでバックアップ1
fJ i池2は小さい谷はのもので良く、又ゴ〈時11
1j停電してもI’Jの支障もない、。Further, the data written in DiζAMI is transferred to the magnetic tape 4 according to a command from the power outage controller 5. This transfer is performed by using the energy of the backup pond 2. Ru. When the transfer is completed, relay coil 11 b f flows 6 by the operation of power outage controller a.
4Mc is cut off, and the contact 11a is turned off. For this reason, the backup 'Yakame 2 supply' (is sent to the Pure Land), but since it is stored in the magnetic disk 4, which is a non-volatile memory, it will not be destroyed. Backup 1 is necessary because the power supply to Yagara 2 is only for a short period of time after a power outage until the data transfer is completed.
fJ i Pond 2 may be one with a small valley;
1J Even if there is a power outage, there will be no problem with I'J.
回、停電が終了すると停電コントローラ5の作動ににり
磁気テープ4のデータは再びL)fζAΔ11へ転送さ
れる。Once the power outage ends, the power outage controller 5 is activated and the data on the magnetic tape 4 is again transferred to L)fζAΔ11.
’a’y ”a 、b +閾は本発明の第2の実施例を
示し、この例で)ま不揮発性メモリとしてバブルメモリ
13を用いた場合を示し、動作および効果は第1の実b
m例と同様である。'a'y ”a, b + threshold shows a second embodiment of the present invention, in which a bubble memory 13 is used as a non-volatile memory, and the operation and effect are the same as those of the first embodiment.
This is the same as example m.
第7,8図は本発明の第3の実施例を示し、この詞では
不揮発性メモリとしてフロッピーディスク14を用いた
一合を示し、動作および効果は第1の実施例と同様であ
る。7 and 8 show a third embodiment of the present invention, in which a floppy disk 14 is used as the nonvolatile memory, and the operation and effects are similar to those of the first embodiment.
尚、バックアップ用′亀池2は一次′嶋池るるいは光−
回路を付加した充電可能な二次゛電池のいずれでも良い
が、二次電池を用いれば′低電のh命が伸びることはビ
ワまでもない。In addition, the backup 'Kameike 2' is the primary 'Shimaike Rurui or Hikari.
Any rechargeable secondary battery with an added circuit may be used, but it goes without saying that using a secondary battery will extend the life of a low-voltage battery.
以にのように本元ゆjによtしば、停一時にバックアッ
プ用電池から夕1ナミツク■ζAMに給電するようにし
た不揮発性メ七り7スアムにお・いて、停電時ダイナミ
ックRA MのI・−りを不揮発性メモリに待避させる
とともに待避させた後にバックアップ用゛1池の給電を
町つようにしており、不揮発性メモリは給電を〜またれ
てもデータが破滅されないのでデータの破壊は生じない
。しかも、バックアップ用電池からの給′屯は停亀が生
じてからデータの待避が完了するまでの短い間であり、
籠池δ址が小さくてもあるいはW 屯が長時間であって
もiaJら支障は生じない。As described above, in the case of a power outage, the backup battery is used to supply power to the RAM from the backup battery.In the case of a power outage, dynamic RAM is The data is saved in a non-volatile memory and the power supply to the backup battery is turned off after being saved, and non-volatile memory does not destroy the data even if the power supply is interrupted. No destruction occurs. Moreover, the supply from the backup battery is only for a short period of time from the time a power outage occurs until the data has been saved.
Even if the basket pond delta is small or the W tunnel is long, no problem will occur.
第1,2図、・よ夫々従来の不揮発性メモリシステムの
構成図およびWt時のタイムチャート、A邦。
4図は夫々本発明の第1の夷殖クリに降る不揮発性メモ
リシステムの↑44図および亀@関係接続図、第5,6
図は夫々本発明の第2の実施例、C係るイ;揮発性メモ
リシステムの構成図および電源関係接続図、第7,8図
;は夫々本発明の毛3の人外vシに係る不揮発性メモリ
システムの構成図および也岸関係接続図。
1・・・タイナミツクKAΔ1(DRA〜1)、2・・
・バックアップ用邂池、3・・・C1’Uバス、 4・
・・磁気チー/、5・・・停電コントローラ、6・・・
通常亀諒、11・・・すL/−113・・・バブルメモ
IJ、14・・・フロツヒーテイス、り。
尚、図中同一符号は同−又は相当部分を示す。
代理人 葛 野 信 −Figures 1 and 2 are a configuration diagram of a conventional non-volatile memory system and a time chart at Wt, respectively. Figure 4 shows the ↑44 diagram of the non-volatile memory system that corresponds to the first imprint of the present invention, and the connection diagrams 5 and 6, respectively.
Figures 7 and 8 respectively show a second embodiment of the present invention; A; a configuration diagram of a volatile memory system and a power supply connection diagram; Figures 7 and 8 respectively show a non-volatile A configuration diagram of the sexual memory system and a connection diagram of the Yagishi relationship. 1... Tainamitsuku KAΔ1 (DRA~1), 2...
・Backup Oeike, 3...C1'U bus, 4.
...magnetic chi/, 5... power outage controller, 6...
Normal Turtle, 11...S L/-113...Bubble Memo IJ, 14...Flotshitis, Ri. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno −
Claims (4)
用電池からダイナミックRAMへ給電するようにした不
揮発性メモリシステムにおいて、停電時ターイナミツク
RAMに記憶されたデータをバックアップ用電池のエネ
ルギーにより不揮発性メモリに転送するとともに転送終
了後にバックアップ用電池をダイナミックRAMおよび
不揮発性メモリから切り離すようにしたことを特徴とす
る不揮発性メモリシステム。(1) In a non-volatile memory system equipped with a dynamic RAM, in which power is supplied to the dynamic RAM from a backup battery in the event of a power outage, data stored in the dynamic RAM is transferred to the non-volatile memory using the energy of the backup battery in the event of a power outage. A non-volatile memory system characterized in that a backup battery is separated from a dynamic RAM and a non-volatile memory after the transfer is completed.
ことを特徴とする特許請求の範囲第1項記載の不揮発性
メモリシステム。(2) The non-volatile memory system according to claim 1, wherein the non-volatile memory is constructed from a magnetic tape.
たことを特徴とする特許請求の範囲第1項記載の不揮発
性メモリシステム。(3) The nonvolatile memory system according to claim 1, wherein the nonvolatile memory is constituted by a bubble memory.
#l故tまたことを特徴とする特許請求の範囲第1項記
載の不揮発性メモリシステム。(4) The non-volatile memory system according to claim 1, wherein the non-volatile memory is stored on a floppy disk.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57088292A JPS58205994A (en) | 1982-05-25 | 1982-05-25 | Non-volatile memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57088292A JPS58205994A (en) | 1982-05-25 | 1982-05-25 | Non-volatile memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58205994A true JPS58205994A (en) | 1983-12-01 |
Family
ID=13938827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57088292A Pending JPS58205994A (en) | 1982-05-25 | 1982-05-25 | Non-volatile memory system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58205994A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62254222A (en) * | 1986-04-28 | 1987-11-06 | Sharp Corp | Protecting device against service interruption |
WO1990003611A2 (en) * | 1988-09-23 | 1990-04-05 | Henry Jamieson Riddoch | Computer memory backup system |
JPH05298197A (en) * | 1992-04-22 | 1993-11-12 | Uin Syst:Kk | Memory device and data backup method therefor |
JP2009153351A (en) * | 2007-12-21 | 2009-07-09 | Toshiba Tec Corp | Electrical device |
US8397012B2 (en) * | 2003-08-28 | 2013-03-12 | International Business Machines Corporation | Data storage systems |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53136442A (en) * | 1977-05-02 | 1978-11-29 | Toshiba Corp | Memory standby register |
JPS5730197A (en) * | 1980-07-29 | 1982-02-18 | Densei:Kk | Nonvolatile memory |
-
1982
- 1982-05-25 JP JP57088292A patent/JPS58205994A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53136442A (en) * | 1977-05-02 | 1978-11-29 | Toshiba Corp | Memory standby register |
JPS5730197A (en) * | 1980-07-29 | 1982-02-18 | Densei:Kk | Nonvolatile memory |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62254222A (en) * | 1986-04-28 | 1987-11-06 | Sharp Corp | Protecting device against service interruption |
WO1990003611A2 (en) * | 1988-09-23 | 1990-04-05 | Henry Jamieson Riddoch | Computer memory backup system |
JPH05298197A (en) * | 1992-04-22 | 1993-11-12 | Uin Syst:Kk | Memory device and data backup method therefor |
US8397012B2 (en) * | 2003-08-28 | 2013-03-12 | International Business Machines Corporation | Data storage systems |
JP2009153351A (en) * | 2007-12-21 | 2009-07-09 | Toshiba Tec Corp | Electrical device |
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