JPS6358522A - Data transfer device with back-up power supply - Google Patents

Abstract

PURPOSE:To ensure an easy and sure back-up for a data transfer device with time points by using a large capacity capacitor to back up a memory device and a timepiece device. CONSTITUTION:Each of the memory devices 1 and timepiece devices of a device which transmits data with time points is backed up in a service interruption mode, etc. by a back-up power supply 41 a large capacity capacitor of a farad unit which is charged by a DC power supply 5 which rectifies a commercial power supply, etc., and another back-up power supply 42 with which a back-up current is prevented from conducting to the device 1 via a diode 9. Thus it is possible to avoid such a case where the satisfactory recharging is impossible in the application mode of a long time like a case a rechargeable battery is used as a back-up power supply. Then the simple, stable and sure back-up is secured with a data transfer device.

Description

[Detailed Description of the Invention] [Summary] For a storage device/clock device using an integrated circuit of a data sending device that sends data with a time stamp attached to an information center,
This is a data transmission device that back-amps each device until power is restored by connecting backup power supplies using large-capacity capacitors in farad units.

[Industrial Application Field] The present invention relates to a data sending device in which a backup power source is connected to a storage device/clock device for sending data to an information center located in a remote location.

A backup power supply is connected to the data transmission device to prevent stored data from being lost in the event of a power outage, but there is a need for a power supply device that has a simple configuration and operates reliably.

[Prior Art] When a semiconductor integrated circuit is used as a data storage device in a data processing system, when the operating power is cut off due to a power outage or when a momentary voltage drop occurs, all of the stored data is volatile. Put it away. Therefore, a bank-up power supply is connected to the storage device to protect the data. FIG. 3 is a diagram showing the configuration of a conventional data sending device, in which 1 is a volatile storage device integrated circuit, 2 is a clock device integrated circuit for inserting time into data, 3 is a peripheral circuit of the storage device integrated circuit, 4 is a backup power source, such as a rechargeable battery such as a nickel-cadmium battery, 5 is a DC power source that rectifies commercial power to obtain DC, and 6 is a diode that connects from the backup power source 4 to the DC power source 5 in the event of a power outage. This prevents the backup power source 4 from being quickly consumed due to current flow.

A DC power supply 5 that obtains DC by rectifying a commercial power supply normally supplies a DC voltage, for example, +5V, to each circuit 1.2.3 to charge the back amplifier power supply. The clock device integrated circuit 2 is used to insert the time when data in the storage device integrated circuit 1 is sent to the center. When the DC power supply 5 is powered off, the backup power supply operates.

[Problems to be Solved by the Invention] In the backup power supply circuit shown in FIG. 3, since the common backup power supply 4 is connected to the storage device integrated circuit 1 and the clock device integrated circuit 2, it is difficult to solve the problem due to a power outage or the like. If the backup DC continued to flow and the bank amplifier could no longer operate, the entire system would stop. Also, if a rechargeable battery was used as a backup power source, it could not be recharged after long periods of use, making data protection impossible.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide a storage device using a backup power source that has a simple configuration and can protect data over a long period of time.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the basic configuration of a data sending device of the present invention. In FIG. 1, ■ is a volatile memory device integrated circuit (for example, one using a CMO3 type semiconductor element);
2 is a clock device integrated circuit (for example, one using a CMO3 type semiconductor element); 3 is a peripheral circuit of a memory device integrated circuit; 4 is a peripheral circuit of a memory device integrated circuit;
1 is a first backup power supply that uses a large capacity capacitor in farad units (for example, 0.5 farad is obtained with an electric double layer capacitor) and is connected to the storage device integrated circuit 1;
42 is a second backup power supply which also uses a large capacity capacitor in farad units and is connected to the clock device integrated circuit 2; 5 is a DC power supply that rectifies the commercial power supply to obtain DC;
Reference numeral 6 is a diode, and reference numerals 71, 72, and 73 are voltage detection circuits connected to the locations shown in the figure. Reference numeral 8 denotes a microprocessor of the data sending device, which controls the operation of the peripheral circuit 3 of the storage device integrated circuit and the clock device integrated circuit 2. A diode 9 prevents current from flowing from the second backup power source 42 to the power source 41 and prevents the backup power source 42 from being quickly consumed.

[Function] When the DC power supply 5 is operating normally, the large capacity capacitor is charged to approximately the DC voltage value of the DC power supply 5, for example, 5V. When the DC voltage of the DC power supply 5 decreases due to a power outage of the commercial power supply, etc., the storage device integrated circuit 1 and the peripheral circuit 3 are backed up by the backup power supply 41, and the clock device integrated circuit 2 is backed up by the backup power supply 42. That is, the voltage until the charged capacitor is discharged is set as the voltage of the backup power supply. Therefore, the data stored in the memory device integrated circuit does not immediately volatilize. Note that the current consumption from the backup power supply 42 is several μ.
Since A is very small, when a backup power supply is configured using capacitors of the same capacity, the backup power supply 4
1 voltage drop is faster.

The microprocessor 8 stops operating during a power outage, but
A voltage detection circuit 71.7 is installed in the flip-flop 51.52.
The second situation, that is, the backup power supply situation, is maintained. Therefore, when the power is restored from the power outage, the microprocessor 8 reads the output potentials of the flip-flops 51 and 52. If the microprocessor knows that the clock device 2 is still operating well, the subsequent microprocessor starts its own processing operation program to automatically start up the system.

As a result, the memory device integrated circuit 1 is ready for operation.

[Example] FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

In FIG. 2, reference numerals 51 and 52 are flip-flops that maintain the state of the voltage detection circuits 71 and 72, that is, the voltage state of the backup power source. Therefore, connect each terminal as shown. 53 is a transistor circuit, which operates in the same manner as the diode 6 in FIG. Other same reference numerals as in FIG. 1 indicate similar parts. The transistor circuit 53 constitutes a voltage dividing circuit with an input side resistor so that the lower transistor in the diagram is conductive during normal power supply voltage, and therefore the upper transistor is conductive during normal times. The potential drop between the emitter and collector of the upper transistor is smaller than the potential drop of the diode 6. and backup power supply 41.
42 capacitors are charged.

The operation at the time of power outage in FIG. 2 will be explained.

The voltage detection circuit 73 detects that the voltage of the DC power supply 5, for example, 5.
When the voltage drops below 5V (such as during a power outage), it is detected and the microprocessor 8 is notified. The microprocessor 8 receives a signal "L" indicating a voltage drop from the voltage detection circuit 73, and transfers necessary data from the internal RAM to the storage device 1. The microprocessor 8 then sends one clock pulse to the flip-flops 51 and 52.
The outputs Q of the forwarding flip-flops 51 and 52 are inverted and set to "H". Due to the voltage drop of the DC power supply 5, the lower transistor of the transistor circuit 53 is turned off, and the upper transistor is also turned off. Bank-up of the bank amplifier power supplies 41 and 42 for the storage device integrated circuit 1, the clock device integrated circuit 2, the storage device peripheral circuit 3, the flip-flops 51 and 52, and the voltage detection circuits 71 and 72 is started. Chip select signal C8 for storage device I and clock device 2
get. If the chip select signal C3 is applied to each integrated circuit, power consumption can be reduced. Since the voltage in the voltage detection circuits 71 and 72 is 2.5 or more, the output terminals Q of the flip-flops 51 and 52 remain at "H" when the power supply becomes normal again. At this time, if the backup power supply becomes 2.5V or less, when the power supply becomes normal again, the flip-flop output terminal Q will be "L".
Therefore, the microprocessor makes a judgment based on the potentials of the output terminals Q of the flip-flops 51 and 52.

During a power outage of the DC power supply 5, the storage device I and the clock device 2 continue to operate using the backup power supplies 41 and 42. That is, the data stored in the storage device 1 does not volatilize, and the clock device 2 continues its timekeeping operation.

As mentioned above, the backup amplifier power supply 41 wears out faster than the power supply 42, so if the power outage continues, the backup power supply 41
The voltage may drop below 2.5V. Therefore, the voltage detection circuit 71 sends a voltage drop detection signal to the preset terminal PR of the flip-flop 51, and when the power supply becomes normal again, the output terminal Q becomes "L'. At this time, the voltage of the backup source 42 decreases. It is assumed that the voltage has not decreased enough to be detected by the voltage detection circuit 72.

When the power outage is restored, the microprocessor 8 can start operating when the applied direct fL voltage reaches about 4■. At this time, the microprocessor 8 knows that the Q terminals of the flip-flops 51 and 52 are at "H" and the latter at "L". That is, it knows that the bank-up power supply 42 for the clock device 2 is in a normal state, reads the clock, and stores it in the internal RAM. Next, since the data in the storage device 1 is considered to be defective, the process is restarted by re-storing the data. Therefore, the processing operation program of the processor 8 is restarted.

Note that when signals indicating that both flip-flops 51 and 52 are normal are notified, the stored data can be used as is and proceed to the next process, such as being transmitted to the center.

If the signals from both flip-flops 51 and 52 indicate that the clock device 2 is defective, the clock device 2 is reset, and then the re-storing process is performed in the memory location 1.

[Effects of the Invention] As described above, the present invention has a simple configuration in which a large capacity capacitor is used for the bank associative power supply, and maintenance is not required even in the event of a fairly long power outage. Furthermore, since the buffer rough power supply for the clock device is provided separately from the back amplifier power supply for the main memory device, processing at the time of power failure recovery is facilitated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a conventional device. 1.-Storage device integrated circuit 2...Clock device integrated circuit 3.--Peripheral circuit of storage device integrated circuit 4.41.42..-Backup power supply 5..-Commercial power supply 8-..-Microprocessor 51.52・-Flip-flop 71.72--Voltage detection circuit patent applicant Fujitsu Ltd. representative Patent attorney Eisuke Suzuki Jōmi's lecture diagram Figure 3

Claims (1)

[Claims] I. Storage device (1)/clock device (2) using an integrated circuit
In a data transmission device that is equipped with
41) Storage device (1) and clock device (2) as (42)
A data transmission device having a backup power supply, characterized in that each of the data transmission devices is connected to a backup power source. II. Voltage detection circuit (71) (72) and microprocessor (8) for each backup power supply (41) (42)
and flip-flops (51) and (52), and when the power supply is restored from a power outage, the voltage detection circuit (71)
The flip-flop (51) holds the state (72).
) (52), the microprocessor (8) determines whether the clock device (2) is good or bad, and if the clock device (2) is good, the microprocessor (8) operates according to the subsequent operating program. A data transmission device having a backup power source according to claim 1.