1261163 九、發明說明： 【發明所屬之技術領域】 a本發明為-種微算機系統，更明確的說，為使用一不恆 足供電來源的低功率微算機系統。 【先前技術】 低功率的微算機㈣，—直是過去數十年以來研究人員 致力的目#。首先是各元件的省電改進，使得同等計算能 力《微算機系統功率消耗在1998到2⑼3間以大約每年百分 之十的下降率減少。其次，太陽能電池技術的進步也使得 可攜式微算機系統的使用時間增長，從199〇到2〇〇3年間， 太陽能電池的能量利用效率從14·8%增加到了 22·8%，但即 使如此’由於隨天候變化造成的供電不狀，纟陽能電池 在需要持續運轉的㈣中，域只能作為辅助的電力來 源。然而’為了某些用s ’我們可能會將太陽能電池作為 王要的电力來源，例如在長時間運作的無人探測儀器中， 在此種裝置内，由於使用時間以及所處環境的因素，故不 可能使用-般蓄電池或外接電源。又或者是，蝴亦可 作為在電池耗盡或電源中斷時，系_能保持最低限度運 轉的後備措施。 本發明提供了一種微算機系統，能僅以太陽能或其他不 :定電源維持系統的運作’於太陽能不足或内部蓄電池電 [低洛時’本系統能自動判斷並將處理中的程式資料暫存 至外邵記憶體中’待供電恢復時可繼續程式之運作，不因 典預期的供電中斷而使得處理中的資料流失。 93629.doc 1261163 【發明内容】 毛月為H肖耗功率之微算機系統及其運作方法，並 使用如太陽能或風力之類不怪定供電的電源、，又或者是:、 较衣置可作為㈣機之電力後備機制，在無預期電力中 斷不斷迅系統（UPS)等裝置電力耗盡之後，使用太陽能等 後備能源維持系統最基本的運作。 =先❿先說明，在此說明書（含申請專利範圍）中「連接」 和、「耦合」為不同之定義：連接僅指兩元件之間物理上之 相連而沒有信號的相連，故不能相互影響；轉合則定義了 信號的傳遞方向’例如「甲輕合至乙」，意指甲的信號可傳 遞給乙，但乙的訊號未傳遞給甲，故甲不知乙發生何事。 ^如果使iU f和乙相互♦馬合」，則指甲和乙訊息相通，可 以交互影響。 基本上’如圖卜本發明之低功率微算機系統包含一如太 陽能電池之類的不恆定電源及其整流電路，一蓄電池，一 控制電路，一電壓位準偵測電路，以及一包含外部記憶體 《王微算機電路(該記憶體内儲存之資料不因斷電而消 失），其中該電壓位準偵測電路扮演開關的角色，其具有一 參考電壓源，若蓄電池所提供的電職於該參考電壓源， 則將程式中斷位址及各暫存器之值存人外部記憶體中並進 入休眠狀態，直至電池充電完畢’再將系統從休眠模式中 唤醒並取回暫存於該外部記憶體中的資料繼續運作。該主 微算機電路主要由8〇51之類之單晶片微算機元件所組成， 該外部記憶體可為EEPRQM，而該控制電路和該主微算機 93629.doc 1261163 電路結合以支援該主微算機電路。 EEPROM為電流可消除可程式唯讀記憶體（Electrically Erasable & Programmable ROM)的簡稱，儲存於其中的資料 並不會因為電源切斷而消失。 如圖1 ’其中電源來自該不丨互定電源及該畜電池，該整流 電路連接至該蓄電池、該控制電路、該電壓位準電路，及 該主微算機電路，並耦合至該控制電路；該蓄電池接受該 整流電路之充電，並與該整流電路、該控制電路、該電壓 | 位準偵測電路、及該主微算機電路相連，並耦合至電壓位 準偵測電路及控制電路；該控制電路與該整流電路、該蓄 電池、與該電壓位準偵測電路相連，並與該主微算機電路 相互耦合；該電壓位準偵測電路和該蓄電池、該整流電路、 _ 該控制電路、及該主微算機電路相連，並與該主微算機電 路相互耦合；該主微算機電路和該整流電路、該蓄電池、 該控制電路、及該電壓位準偵測電路，並與該控制電路及 該電壓位準偵測電路相互耦合。該電壓位準偵測電路比較 φ 該參考電壓與蓄電池電壓，並在蓄電池電壓低於該參考電 壓時通知該主微算機電路進入一休眠狀態，並在該蓄電池 回到一預定標準或充電完成後，通知該主微算機電路將資 料取回，繼續作業。 除了上述的電路之外，見圖2，於一具體實施例中（詳後 述），還可包含一類比轉數位介面電路，功用在於將輸入的 類比信號轉為數位信號，以供主微算機電路使用。 為了增加該太陽能電池的集光效率，在該實施例中，於 93629.doc 1261163 太陽^池周圍设置反射鏡，如圖4所示。更由實驗得知， 當反射鏡4〇1與太陽能電池6〇1及太陽能電池601和光源4〇2 2間均為垂直的時候，可以得到一個最大的能量產出率， 實驗結果如圖5所+。妞诚奋μ 上、 、根據貝無，反射鏡可以延長操作時間 最佳達1.67倍。 【實施方式】 有關本發明之一具體實施例，請見圖2至圖3及圖6至圖 1〇 °该貫施例僅說明本發明之可能實施方式，以使本發明 更今易被瞭解，但其並不用以限制本發明之實施方式，熟 習此技藝者自然可以對實施方式作修改，但仍不脫離本發 明之精神與範疇。 見圖2，该具體實施例包含一太陽能電池含整流電路，一 蓄電池，一電壓位準偵測電路，一控制電路，一類比轉數 位"面電路（如ADC0804)，一單晶片微算機（如AT89C51)系 統及EEPROM和LCD數位顯示電路等。本實施例應用在太陽 能資料收集的用途，本實施例將收集到的太陽能一方面做 為供電來源，一方面記錄下太陽能的變化，並用LCD螢幕 供使用者觀看。 本貫施例之電源來自一太陽能電池6〇丨及一蓄電池3〇1， 泫太陽能電池601可為該蓄電池301充電，並接至該控制電 路、戎電壓位準偵測電路、及該類比轉數位介面電路。該 電壓位準偵測電路比較該參考電壓與蓄電池電壓，並在蓄 電池電壓低於該參考電壓時通知該Lcd顯示及EEPROM儲 存電路進入一休眠狀態。該類比轉數位介面電路接收由太 93629.doc 1261163 陽能電池傳來的類比電氣訊號後，經由該ADC0804轉換為 數位信號，並供給該AT89C51系統及EEPROM和LCD數位顯 示電路。 圖3之電路除EEPROM和LCD電路之夕卜，可分解為如圖6 之太陽能電池601含整流電路，圖7之電壓位準偵測電路， 圖8之控制電路，圖9之類比轉數位介面電路。以下將對上 述每一電路區塊作較詳細的解說。 請見圖6，本電路由齊納二極體602和射極隨耦器603組 成，更換圖中的齊納二極體602可得到不同的電壓輸出，二 極體左側之電容604選用10 //，此為一常見的濾波電容，而 電阻605可為1.2ΚΩ -20ΚΩ，在實施例中使用12K是為了平 衡工作點和降低電源消耗。在此電路右側輸出端除通往控 ‘ 制電路外，也並聯該蓄電池301，以對該蓄電池301做充電。 見圖7，為本實施例的電壓位準偵測電路部分，此電路可 配合不同設計，一般來說使用TTL logic的電路，要使其動 作正常，其判斷位準電壓為3.5V以上，在本實施例中參考 $ 電壓701選用4.5¥，故乂0：(31在4¥時，即可斷電，於5.1¥左 右時，恢復供電。基極電阻702的選擇範圍可為3.3ΚΩ -33K Ω Μ為了減少電流損耗故使用33ΚΩ。在圖7的電路中，包 含兩組ΡΝΡ及ΝΡΝ電晶體，靠左半邊的一組ΡΝΡ及ΝΡΝ電晶 體703偵測電壓下降而通知系統斷電，右半邊的一組ΡΝΡ及 ΝΡΝ電晶體704偵測電壓回升而使系統恢復供電。 見圖8，為本實施例的控制電路部分，此電路之AT89C5 1 為一省電型805 1，S 1即為前述之電壓位準偵測電路，電阻 93629.doc 1261163 801可為22ΚΩ-300ΚΩ之間，在此選定220ΚΩ，是考慮維 持電路之運作及減少電流損耗之後，較佳之設計值。此圖 中電容器C5為整流之用，與AT89C51之接地端802，因不為 電路重要部分，故皆不見於圖3之總圖中。 請見圖9，為本實施例之類比轉數位介面電路’本貫施例 因為有一輸入（太陽能變化），故需要此電路。為了完整解說 起見，AT89C51包含在此圖中，但並不代表AT89C51在本發 明其他沒有類比轉數位電路的實施例中便不存在。太陽能 變化值之輸入端請見圖9之右上角，此一部份於圖3之總圖 中為併於整流電路内，ADC0804為類比轉數位晶片，數位 化後之資訊即進入AT89C51中處理，其中900ΚΩ之電阻901 及100ΚΩ之電阻902只需維持9 : 1之比例即可，但為使 ADC0804可以正確得知電壓位準以及減少電流損耗，故選 用900ΚΩ及100ΚΩ，而與太陽能電池並聯之電阻903選為 200K Ω，係根據該太陽能電池之内阻以及所需之電流。 接下來請見圖10，為本實施例之動作流程圖，首先，本 系統第一步檢查進入外部EEPROM檢查是否進入過休眠 (powerdown)狀態，若未曾進入休眠狀態，則逕行初始化及 ADC0804(類比轉數位）之觸發；若進入過休眠狀態，則將程 式中斷位址，各暫存器之值自外部EEPROM取出，再逕行 初始化及ADC0804之觸發。 接著’將輸入ADC0804之太陽能訊號自類比説號轉為數 位信號，接著執行LCD顯示程式顯示太陽能之變化，在這 過程中，隨時檢查電池電壓是否低於位準電壓，如電池電 93629.doc -10- 1261163 壓低於位準電壓，則將程式中斷位址及各暫存器之值存入 外部EEPROM中，並進入休眠狀態。該系統將在休眠狀態 中監視電池之電壓與充電狀態，如電池充電完畢，則回到 流程之第一步，重新開始流程。 此實施例為根據本發明之意旨，所製成之一特殊實施 例，其可充分說明本發明之可實行性。 【圖式簡單說明】 圖1為本發明之基本電路設計方塊圖； 圖2為本發明一具體實施例之電路設計方塊圖； 圖3為本發明一具體實施例之總電路圖； 圖4為本發明一具體實施例中，加上反射鏡的太陽能電池 之典型空間擺設； 圖5為本發明一具體實施例中，太陽能電池功率與距離及 反射鏡角度間關係之立體特性曲線圖； 圖6為本發明一具體實施例中，太陽能電池含整流電路之 電路圖； 圖7為本發明一具體實施例中，電壓位準偵測電路之電路 圖； 圖8為本發明一具體實施例中，控制電路之電路圖； 圖9為本發明一具體實施例中，類比轉數位介面電路之電 路圖， 圖10為本發明一具體實施例之動作流程圖。 【主要元件符號說明】 301 蓄電池 93629.doc 1261163 401 反射鏡 402 光源 601 太陽能電池 602 齊納二極體 603 射極隨耦器 604 電容 605 電阻 701 參考電壓 702 基極電阻 703 一組PNP及NPN電晶體 704 一組PNP及NPN電晶體 801 電阻 802 接地端 901 電阻 902 電阻 903 電阻 93629.doc 12-1261163 IX. Description of the invention: [Technical field to which the invention pertains] a The present invention is a computer system, and more specifically, a low power microcomputer system that uses a source of power that is not constant. [Prior Art] Low-power microcomputers (4), which are the ones that researchers have been working on for decades. The first is the power-saving improvement of each component, which makes the equivalent computing power. The power consumption of the microcomputer system is reduced by about 10% per year between 1998 and 2(9)3. Secondly, advances in solar cell technology have also led to an increase in the use of portable computer systems. From 199 〇〇 to 2 〇〇 3 years, the energy efficiency of solar cells has increased from 14.8% to 22.8%, but even In this way, due to the power supply caused by the change of the weather, the solar battery can only be used as an auxiliary power source in the fourth (four) that needs continuous operation. However, 'for some use s' we may use solar cells as the source of power for the king, such as in long-running unmanned instruments, in this device, due to the time of use and the environment, It is possible to use a general battery or an external power supply. Or, the butterfly can also be used as a backup measure to keep the minimum operation when the battery is exhausted or the power is interrupted. The invention provides a computer system capable of maintaining the operation of the system only by solar energy or other non-determined power supply. 'Insufficient solar energy or internal battery power [low-lost] The system can automatically judge and temporarily process the program data in the process. Saved to the external memory. When the power supply is restored, the operation of the program can be continued. The data in the process is not lost due to the expected power interruption. 93629.doc 1261163 [Summary of the Invention] Maoyue is a computer power consumption system and its operation method, and uses a power source such as solar energy or wind power that does not blame power supply, or: As the power backup mechanism of the (4) machine, after the power of the uninterrupted power interruption system (UPS) is exhausted, the backup energy such as solar energy is used to maintain the most basic operation of the system. = First, in the description (including the scope of patent application), "connection" and "coupling" are different definitions: the connection only means that the two components are physically connected and there is no signal connection, so they cannot affect each other. Turning defines the direction of signal transmission 'for example, 'A light to B', the signal of the nail can be passed to B, but the signal of B is not transmitted to A, so A does not know what happened to B. ^If iU f and B are mutually spliced, the nail and B message are connected and can be interactively affected. Basically, the low-power microcomputer system of the present invention comprises a non-constant power source such as a solar battery and a rectifying circuit thereof, a battery, a control circuit, a voltage level detecting circuit, and an external unit. Memory "Wang Microcomputer circuit (the data stored in the memory does not disappear due to power failure), wherein the voltage level detection circuit plays the role of a switch, which has a reference voltage source, if the battery provides electricity When the reference voltage source is used, the program interrupt address and the value of each register are stored in the external memory and enter the sleep state until the battery is charged. Then the system wakes up from the sleep mode and retrieves the temporary storage. The data in this external memory continues to operate. The main microcomputer circuit is mainly composed of a single-chip microcomputer component such as 8〇51, and the external memory can be EEPRQM, and the control circuit is combined with the main microcomputer 93629.doc 1261163 circuit to support the The main computer circuit. The EEPROM is an abbreviation for Electrically Erasable & Programmable ROM. The data stored in it is not lost due to power interruption. As shown in FIG. 1 'where the power source comes from the independent power source and the battery, the rectifier circuit is connected to the battery, the control circuit, the voltage level circuit, and the main computer circuit, and is coupled to the control circuit The battery is charged by the rectifier circuit, and is connected to the rectifier circuit, the control circuit, the voltage | level detection circuit, and the main microcomputer circuit, and coupled to the voltage level detection circuit and the control circuit The control circuit is connected to the rectifier circuit, the battery, and the voltage level detecting circuit, and coupled to the main microcomputer circuit; the voltage level detecting circuit and the battery, the rectifying circuit, and the a control circuit, connected to the main microcomputer circuit, and coupled to the main microcomputer circuit; the main microcomputer circuit and the rectification circuit, the battery, the control circuit, and the voltage level detection circuit, And coupled to the control circuit and the voltage level detecting circuit. The voltage level detecting circuit compares the reference voltage with the battery voltage, and notifies the main computer circuit to enter a sleep state when the battery voltage is lower than the reference voltage, and returns to a predetermined standard or charging completion of the battery. After that, the main computer circuit is notified to retrieve the data and continue the operation. In addition to the above-mentioned circuit, as shown in FIG. 2, in an embodiment (described later), an analog-to-digital interface circuit may be included, which functions to convert an input analog signal into a digital signal for a primary computer. Circuit use. In order to increase the light collecting efficiency of the solar cell, in this embodiment, a mirror is disposed around the solar cell of 93629.doc 1261163, as shown in FIG. It is also known from experiments that when the mirror 4〇1 is perpendicular to the solar cell 6〇1 and the solar cell 601 and the light source 4〇2 2, a maximum energy yield can be obtained, and the experimental result is shown in FIG. 5. +. The girl is sincerely μ, and according to Bei, the mirror can extend the operating time to 1.67 times. [Embodiment] For a specific embodiment of the present invention, please refer to FIG. 2 to FIG. 3 and FIG. 6 to FIG. 1 to illustrate the possible embodiments of the present invention, so that the present invention is more easily understood. However, it is not intended to limit the embodiments of the present invention, and those skilled in the art can naturally modify the embodiments without departing from the spirit and scope of the invention. Referring to FIG. 2, the specific embodiment includes a solar cell including a rectifying circuit, a battery, a voltage level detecting circuit, a control circuit, an analog-to-digital digital circuit (such as ADC0804), and a single-chip microcomputer. (such as AT89C51) system and EEPROM and LCD digital display circuit. This embodiment is applied to the collection of solar energy data. In this embodiment, the collected solar energy is used as a power source, and the change of solar energy is recorded on the one hand, and the LCD screen is used for the user to watch. The power supply of the present embodiment is from a solar cell 6〇丨 and a battery 3〇1, and the solar cell 601 can charge the battery 301, and is connected to the control circuit, the voltage level detection circuit, and the like. Digital interface circuit. The voltage level detecting circuit compares the reference voltage with the battery voltage, and notifies the Lcd display and the EEPROM storage circuit to enter a sleep state when the battery voltage is lower than the reference voltage. The analog-to-digital interface circuit receives the analog electrical signal from the solar battery of the 93629.doc 1261163, converts it to a digital signal via the ADC0804, and supplies the AT89C51 system with the EEPROM and LCD digital display circuit. The circuit of Figure 3 can be decomposed into the rectifier circuit of the solar cell 601 of Figure 6, the voltage level detection circuit of Figure 7, the control circuit of Figure 8, and the analog-to-digital interface of Figure 9 except for the EEPROM and LCD circuits. Circuit. A detailed explanation of each of the above circuit blocks will be given below. Please refer to FIG. 6. The circuit is composed of a Zener diode 602 and an emitter follower 603. The Zener diode 602 in the figure can be replaced with different voltage outputs, and the capacitor 604 on the left side of the diode is selected as 10/ /, This is a common filter capacitor, and the resistor 605 can be 1.2 Κ -20 Κ Ω, which is used in the embodiment to balance the operating point and reduce power consumption. At the output of the right side of the circuit, in addition to the control circuit, the battery 301 is also connected in parallel to charge the battery 301. 7 is a voltage level detecting circuit part of the embodiment. This circuit can be used with different designs. Generally, a circuit using TTL logic is required to make its operation normal, and its judgment level voltage is 3.5V or more. In this embodiment, the voltage 701 is selected as 4.5¥, so 乂0: (31 at 4¥, the power can be cut off, and when the power is about 5.1¥, the power supply is restored. The base resistor 702 can be selected from 3.3ΚΩ -33K. Ω 使用 33 Ω is used to reduce the current loss. In the circuit of Figure 7, two sets of ΡΝΡ and ΝΡΝ transistors are included, and a group of ΡΝΡ and ΝΡΝ transistors 703 on the left half detect the voltage drop and notify the system to turn off the power, right half The set of ΡΝΡ and ΝΡΝ transistors 704 detects the voltage rise and restores the power supply to the system. See Fig. 8, which is the control circuit part of the embodiment, the AT89C5 1 of the circuit is a power-saving type 805 1, S 1 is the foregoing The voltage level detection circuit, the resistor 93629.doc 1261163 801 can be between 22 Κ Ω and 300 Κ Ω, and 220 Ω is selected here, which is a preferred design value after considering the operation of the circuit and reducing the current loss. In this figure, the capacitor C5 is Rectification The grounding terminal 802 of the AT89C51 is not an important part of the circuit, so it is not seen in the general drawing of Fig. 3. Please refer to Fig. 9, which is an analog-to-digital interface circuit of the present embodiment. This circuit is required. For the sake of complete explanation, AT89C51 is included in this figure, but it does not mean that AT89C51 does not exist in other embodiments of the present invention that do not have an analog-to-digital circuit. As shown in the upper right corner of Figure 9, this part is in the general diagram of Figure 3 and is in the rectifier circuit. The ADC0804 is an analog-to-digital chip. The digitalized information is processed into the AT89C51. The 900 Ω resistors are 901 and 100 Ω. The resistor 902 only needs to maintain a ratio of 9:1, but in order to make the ADC0804 correctly know the voltage level and reduce the current loss, 900 Κ Ω and 100 Κ Ω are selected, and the resistor 903 connected in parallel with the solar cell is selected as 200K Ω. According to the internal resistance of the solar cell and the required current. Next, please refer to FIG. 10, which is a flow chart of the operation of the embodiment. First, the first step of the system checks into the external EEPROM. Check whether the power-down state has been entered. If it has not entered the sleep state, it will be initialized and triggered by ADC0804 (analog-to-digital digit). If it enters the sleep state, the program will interrupt the address, and the value of each register will be external. The EEPROM is taken out, and then initialized and triggered by the ADC 0804. Then 'the solar signal input to the ADC0804 is converted from the analog number to the digital signal, and then the LCD display program is executed to display the change of the solar energy. In the process, the battery voltage is checked at any time. The level voltage, such as the battery power 93629.doc -10- 1261163 voltage is lower than the level voltage, the program interrupt address and the value of each register are stored in the external EEPROM, and enters the sleep state. The system will monitor the battery voltage and state of charge during sleep. If the battery is fully charged, return to the first step of the process and restart the process. This embodiment is a specific embodiment made in accordance with the teachings of the present invention, which fully demonstrates the practicability of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a basic circuit design of the present invention; FIG. 2 is a block diagram of a circuit design according to an embodiment of the present invention; FIG. 3 is a general circuit diagram of an embodiment of the present invention; In a specific embodiment of the invention, a typical space arrangement of a solar cell with a mirror is added; FIG. 5 is a three-dimensional characteristic diagram of the relationship between the power of the solar cell and the distance of the mirror and the angle of the mirror according to an embodiment of the present invention; In a specific embodiment of the present invention, a solar cell includes a circuit diagram of a rectifier circuit; FIG. 7 is a circuit diagram of a voltage level detecting circuit according to an embodiment of the present invention; FIG. 8 is a circuit diagram of a control circuit according to an embodiment of the present invention; FIG. 9 is a circuit diagram of an analog-to-digital interface circuit according to an embodiment of the present invention. FIG. 10 is a flow chart of an operation of an embodiment of the present invention. [Main component symbol description] 301 Battery 93629.doc 1261163 401 Mirror 402 Light source 601 Solar cell 602 Zener diode 603 Emitter follower 604 Capacitor 605 Resistor 701 Reference voltage 702 Base resistance 703 A group of PNP and NPN Crystal 704 A set of PNP and NPN transistor 801 resistor 802 ground terminal 901 resistor 902 resistor 903 resistor 93629.doc 12-