JPS58205869A - Method of testing logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a logic circuit, and more particularly to a method for determining the quality of a logic circuit.

Recently, with the development of microphone four processors, four chic circuits have also become more complex. Code analysis methods have been proposed to repair failures in these logic circuits. This code analysis method applies a predetermined logic pattern to a logic circuit under test (hereinafter abbreviated as CUT), and uses a special encoding circuit, such as a feedback shift register called a code generator, to generate data from each test point of the CUT. A code is generated by encoding the serial output during one pattern cycle of the circuit, the code from this encoding circuit is compared with the expected code, and the CUT
It is used to judge the quality of the product. If the output sign is different from the expected sign, it can be assumed that the previous stage of that test point has failed. This code analysis method is described in U.S. Pat. No. 3,976.
Since it is described in detail in Japanese Patent Publication No. 56-52345 corresponding to No. 864, detailed explanation thereof will be omitted here. Code analysis methods can effectively test CUTs and are applicable to a wide variety of quadric circuits, such as computer systems that include central processing units, kernels, buses, and the like.

However, in the case of such a code analysis method, the input terminal of the encoding circuit must be connected to each test point of the CUT, and a code must be generated from each test point, which is very troublesome, and also requires the testing of the CUT. There is a drawback that it takes a long time when there are many points. for example,
The address bus of the 6800 microprocessor system has 16 lines and its data and control bus.
Each bus has 8 lines, so 32 lines in total.
The quality of these buses must be determined by testing individual lines.

Accordingly, it is an object of the present invention to provide a method for effectively testing logic circuits having many test points or many lines to be tested.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a block diagram of a first embodiment according to the invention. In the same figure, the four-wheel generator α1
A first throttle signal is generated, and the frequency thereof is divided by N (natural number) by an N-ary counter a2 to obtain a second throttle signal. The second clock signal is therefore the carryout of the counter (I) and its frequency is N of the first clock signal. A predetermined logic pattern is generated, and a start/stop signal representing the start and stop times during one cycle of the logic pattern is generated.The logic pattern is supplied from the pattern generator I to the CUT (IQ, but which logic pattern are serial or parallel logic signals determined by the configuration of CUT(IQ).The pattern generator I may be provided in CUTQQ in advance.CUT(le&-!,
There are N test points or N output lines to be tested, where N is 4 in this example. Therefore, counter a3 is a quaternary counter, that is, a 2-bit binary counter. CUT(1(4 output lines A, B, C and D from 9) and 2 output lines from counter Q3
Depending on the pit output, each cycle of the first clock signal from clock generator a1 is selected successively by multiplexer a8. Multiplexer (Is is CUTQ
(The encoding circuit, that is, the code generator (A) may be connected to the clock terminal CLK of the clock generator α.
[, the start/stop signal from the pattern generator α, and the output of the data terminal DVc multiplexer α are received at the start/stop terminals 8/8, respectively.

FIG. 2 is a time chart for explaining the operation of FIG. 1, and here, FIGS. FIG. 2F shows the first and second clock signals, respectively, and FIG. 2G shows the contents of the output from multiplexer 0. CUT (161 system clock frequency is l
MHz, the frequencies of the first and second clock signals are 1 MHz and 4 MHz, respectively. In other words, the oscillation frequency of the clock generator a is determined by the system clock frequency of CUT (11) and N. In this embodiment, the pattern generator I receives the second clock signal F
generates components of a continuous logic pattern every two cycles of the signal E, so that the logic level on the two inputs A-D changes every eight cycles of the first signal E. however,
It should be noted that the pattern generator a4 may generate a component of the logic pattern at least every cycle of the second cylinder check signal F. The output q from the multiplexer α contains at least one component of the output pattern obtained on each line AD during one cycle of the second clock signal F. The code generator encodes the output q from the multiplexer a during the period from the start time to the stop time in synchronization with the first clock signal E, and generates this encoded signal or code. This code is displayed alphanumerically on a display provided within the code generator end, and compared automatically or manually with the expected code, CU'l'
(Judge whether 19 is good or bad.

Note that the output code of the code generator includes all test results of lines AD. According to the invention, therefore, many lines or test points can be tested with a single test point or output of multiplexer α, thus saving the repair person a lot of time.

[If the output sign is different from the expected sign, then each of lines A to D may be tested.

FIG. 3 shows a block diagram of a second embodiment of the present invention, in which the present invention is applied to a microcomputer system. The first one from the four-wheel generator α
The second clock signal from counter a2 is used as a system clock for the CPU and kernel circuit (23).The CPU and kernel circuit function as a central processing unit (CPU). For example, it has a 6800 type micro processor.CPU
The kernel part of the kernel circuit @ consists of a random access memory (RAM) that operates as a temporary memory for the CPU, and a read-only memory (ROM) that stores a program for controlling the CPU.

The CPU, RAM and ROM are interconnected by internal address, data and control buses.

An address bus (2), a data bus (c) and a controller connect external main buses consisting of one bus to corresponding five internal buses of the CPU and kernel circuits. Bus (24)
, as and (to) as a bidirectional buffer (30-r
l) and bus (24-n), (26-n) and (28-
Peripherals such as memory and keyboard (32-
rl) (n = 1) 2 and 3). The multiplexers (1B-1) to (1B-8) connect the buses (24-1) and
Buses (26-1) and (28-1), Bus (24-2),
Buses (26-2) and (28-2), Buses (24-3),
Buses (26-3) and (28-3), Bus 341. bus(
Select one of the lines c) and (to).

CPU and kernel times M (221 (7) CPU is 680
If there is a type 0, its system clock frequency is l MH
z, the address bus consists of 16 lines, and the data and control buses each consist of 8 lines.

Multiplexer (18-1), (18-3), (1
8-5) and (18-7) select one line of the address bus, and multiplexers (18-2) and (1
8-4), (18-6) and (18-8) select one line of the data and control bus combination.

Here, the natural number N is 16. Therefore, the frequency of the first clock signal is 16 MHz, and the counter α is a hexadecimal counter, or a 4-bit binary counter,
Its 4-bit output is sent from multiplexers (18-1) to (1
8-8) Used as a control signal for the IC. CPU and kernel circuit CI! The ROM 21 stores a special program and generates predetermined logic patterns and start/stop signals by the CPUK. This logic pattern is applied to address bus C:41. A data bus (c) and a control bus (to) k are supplied, and a start/stop signal is derived from the 16th address line, etc. The code generator has its clock terminal CLK
It receives the first clock signal from the clock generator α1, the start/stop signal from the start/stop terminal S/5lcCPU and the kernel circuit (22+), and the output from the output terminal from the data terminal. .

To test the address bus (24-1), output terminals (34-1) of the multiplexer (18-1)
-1). As discussed above in connection with FIGS. 1 and 2, the code generator generates a code corresponding to the output of terminal (34-1). Note that 16 lines can be tested using only one test terminal. The output terminal (34-2) of the multiplexer (18-2) is
Data bus (26-1) and control bus (28-
This is for testing 1). Other output terminals (34-3) ~
(34-8) is similar to terminals (34-1) and (34-2). If the output sign from terminal (34-1) or (34-2) matches the expected sign, it is preferable to test terminal (34-7) or (34-8).

FIG. 4 shows a block diagram of a third rear embodiment according to the present invention,
FIG. 5 is a time chart for explaining the operation of FIG. 4. In this embodiment, clock generator a [, counter α2 . Pattern generator (14) and code generator (sha)
The components other than the connection relationships between the two are the same as the first embodiment shown in FIG. Pattern generator (14+ is clock generator fi1
A predetermined logic pattern is generated by receiving the clock signal E from 24'7λ to 24'7λ to D, so that the logic level on 24'7λ to D changes every cycle of the clock signal. It should be noted that the oscillation frequency of the clock generator (I) is the same as the system clock frequency of the CUT (16). The counter α2 counts the start or stop signal H supplied from the pattern generator I and calculates the sign The carryout F is supplied to the start/stop terminal S/8 of the generator (to).The counter α is an N-ary counter, where N
is the number of output lines of CUTαe. In this example,
One code cycle is 5 to 4 clock cycles as shown in FIG. Therefore, the data terminals of the code generator 6 receive the logic signal on line A from the multiplexer (II) during the first code cycle, the logic signal on line B during the second code cycle, and the logic signal on line B during the third code cycle. C and, during the fourth code cycle, a logic signal on line D. Other operations are performed on the first
This embodiment is similar to the first embodiment shown in FIGS. This embodiment can also be applied to the second embodiment shown in FIG.

As can be seen from the above, the present invention can effectively test logic circuits such as buses having many test points or lines to test.

Although only the preferred embodiments of the present invention have been described in detail above, those skilled in the art will easily understand that many changes and modifications can be made without departing from the spirit of the present invention. For example, in the embodiment of FIG. 3, a single multiplexer may be used to sequentially select one line of all of the address, data and control buses. However, in this case, N is 32, the first clock frequency is 32 MHz, and the counter α is a 5-bit binary counter. Test procedures and expected codes may be clearly marked near the test points. Further, the code generator may include a multiplexer in which a plurality of input terminals are respectively connected to the blower 1.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a 25J! Block diagram showing the embodiment, No. 4
The figure is a block diagram showing a third embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation of FIG. 4. al is a clock generator, (1B is a counter, (14
) is the pattern generator, αe is the logic circuit under test, αI
& word multiplexer, 1 is the encoding circuit, (2 is the CPU
and a kernel circuit, (to) a buffer, and 0) a peripheral device. -J Different Ward D Be(Owl L) OLl xL 0 口(CQ u OLI L O

Claims (1)

[Claims] A predetermined logic pattern is supplied to the logic circuit under test according to the four-thick signal, and one of the N output logic signals (N is a natural number) generated in parallel from the above-mentioned thick circuit under test is continuously supplied. 1. A method for testing a logic circuit, comprising: selecting an output-sick signal, encoding the selected output-sick signal, and determining the acceptability of the sick circuit under test according to the encoded output-sick signal.