JPH0373829B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a logic circuit, and more particularly to a method for determining the quality of a logic circuit.

Recently, with the development of microprocessors, logic circuits have become more complex. Code analysis methods have been proposed to repair failures in these logic circuits. This code analysis method applies a predetermined logic pattern to a logic circuit under test (hereinafter abbreviated as CUT), and uses a special encoding circuit, such as a feedback shift register called a code generator, to detect each test point of the CUT. A certain code is generated by encoding the serial output during one pattern cycle from the encoder, and the code from this encoding circuit is compared with the expected code to judge whether the CUT is good or bad. If the output sign is different from the expected sign, it can be assumed that the previous stage of that test point has failed. This code analysis method is described in detail in Japanese Patent Publication No. 56-52345, which corresponds to U.S. Patent No. 3,976,864.
A detailed explanation thereof will be omitted here. Code analysis methods can effectively test CUTs and can be applied to a wide variety of logic circuits, such as computer systems, including central processing units, kernels, buses, etc.

However, in the case of such a code analysis method, the input terminal of the coding circuit must be connected to each test point of the CUT, and the code must be generated from each test point, which is very troublesome and requires
The drawback is that it takes a long time when there are many CUT test points. For example, the address bus of a 6800 microprocessor system has 16 lines, and its data and control buses each have 8 lines, so a total of 32 lines can be tested. It is necessary to judge whether the bus is good or bad.

Accordingly, it is an object of the present invention to provide a method for effectively testing logic circuits having many test points or many lines to be tested.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a block diagram of a first embodiment of the invention. In the figure, a first clock signal is generated from a clock generator 10, and its frequency is determined by an N-ary counter 12.
(natural number) to obtain a second clock signal.
The second clock signal is therefore the carry out of the counter 12 and its frequency is 1/N of the first clock signal. The pattern generator 14 generates a predetermined logic pattern according to or synchronously with the second clock signal and also generates start/stop signals representing start and stop times during one cycle of the logic pattern. Occur. Logic pattern from pattern generator 14
The logic pattern applied to the CUT 16 is a series or parallel logic signal determined by the configuration of the CUT 16. The pattern generator 14 may be provided in the CUT 16 in advance. CUT
16 has N test points or N output lines to be tested, and in this example, N is 4. Therefore, counter 12 is a quaternary or 2-bit binary counter. 4 output lines A, B, from CUT16
C and D are selected sequentially by multiplexer 18 on each cycle of the first clock signal from clock generator 10 in response to the two-bit output from counter 12. Multiplexer 18 is
It may also be mounted on CUT16. The encoding circuit or code generator 20 receives at its clock terminal CLK the first clock signal from the clock generator 10;
The start/stop signal from the pattern generator 14 is received at the start/stop terminal S/S, and the output of the multiplexer 18 is received at the data terminal D, respectively.

Figure 2 is a time chart for explaining the operation of Figure 1, and Figures 2A to 2D are
Indicates information on lines A to D from CUT16,
2E and 2F illustrate the first and second clock signals, respectively, and FIG. 2G illustrates the content of the output from multiplexer 18. CUT1
If the system clock frequency of 6 is 1MHz, the frequencies of the first and second clock signals are:
They are 4MHz and 1MHz, respectively. In other words, the oscillation frequency of clock generator 10 is determined by the system clock frequency of CUT 16 and N.
In this embodiment, the pattern generator 14 generates components of a continuous logic pattern every two cycles of the second clock signal F, so that the logic levels on lines AD are equal to those of the first clock signal E. Changes every 8 cycles. However, pattern generator 1
Note that 4 may generate a component of the logic pattern at least every cycle of the second clock signal F. The output G from multiplexer 18 includes at least one component of the output pattern obtained on each line AD during one cycle of second clock signal F. code generator 20
synchronized with the first clock signal E, encodes the output G from the multiplexer 18 during the period from the start time to the stop time and generates the encoded signal or code. This code is displayed in letters and numbers on a display provided in the code generator 20,
and compare automatically or manually with the expected sign,
Determine the quality of CUT16. Note that the output code of code generator 20 includes all test results for lines AD. Thus, according to the invention, many lines or test points can be tested with a single test point or output of multiplexer 18, thus saving the repair person a lot of time. And if the output sign is different from the expected sign, then line A
-D may be tested.

FIG. 3 shows a block diagram of a second embodiment of the present invention, in which the present invention is applied to a microcomputer system. A first clock signal from clock generator 10 is provided to an N-ary counter 12, and a second clock signal from counter 12 is used as the system clock for the CPU and kernel circuits 22. The CPU and kernel circuit 22 has a central processing unit (CPU), for example, a 6800 type microprocessor.
The kernel part of the CPU and kernel circuit 22 is as follows:
It consists of random access memory (RAM), which acts as temporary memory for the CPU, and read-only memory (ROM), which stores programs to control the CPU. CPU, RAM and ROM are
Interconnected by internal address, data and control buses. An external main bus consisting of an address bus 24, a data bus 26 and a control bus 28 is connected to corresponding internal buses of the CPU and kernel circuits 22. Buses 24, 26 and 2
8, bidirectional buffer 30-n and bus 24-
It is connected to peripheral devices 32-n, n=1, 2, and 3, such as memory and keyboard, through the terminals 32-n, 26-n, and 28-n. Multiplexer 18-1 to 18-8
According to the digital output from the counter 12,
Bus 24-1, Bus 26-1 and Bus 28- respectively.
1. Bus 24-2, Bus 26-2 and 28-2, Bus 24-3, Bus 26-3 and 28-3, Bus 2
4. Select one of the lines of buses 26 and 28.

If the CPU of the CPU and kernel circuit 22 is a 6800 type, its system clock frequency is 1 MHz, the address bus consists of 16 lines, and the data and control buses each consist of 8 lines.
Multiplexers 18-1, 18-3, 18-5 and 18-7 select one line of the address bus,
and multiplexer 18-2, 18-4, 18
-6 and 18-8 select one line of the data and control bus combination. Here, natural number N
is 16. Therefore, the frequency of the first clock signal is 16 MHz, and the counter 12 is a hexadecimal counter, or a 4-bit binary counter, whose 4-bit output is sent to the multiplexers 18-1 to 18-1.
It is used as a control signal for 8.
The ROM of the CPU and kernel circuit 22 stores special programs and generates predetermined logic patterns and start/stop signals by the CPU. This logic pattern is connected to the address bus 24,
It supplies data bus 26 and control bus 28, and derives start/stop signals from the 16th address line, etc. code generator 20
connects clock generator 1 to its clock terminal CLK.
0, a start/stop signal from the CPU and kernel circuit 22 to the start/stop terminal S/S, and a data terminal D.
receives the output from the probe 36.

To test address bus 24-1, probe 36 is connected to output terminal 3 of multiplexer 18-1.
Connect to 4-1. As discussed above in connection with FIGS. 1 and 2, code generator 20 is connected to terminal 34-1.
generates a code corresponding to the output of Note that 16 lines can be tested using only one test terminal. The output terminal 34-2 of the multiplexer 18-2 is for testing the data bus 26-1 and the control bus 28-1. Other output terminals 34-3 to 34-8 are similar to terminals 34-1 and 34-2. Terminal 34-1 or 3
If the output sign from 4-2 differs from the expected sign, it is preferable to test terminal 34-7 or 34-8.

FIG. 4 shows a block diagram of a third embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation of FIG. In this embodiment, a clock generator 10, a counter 12, a pattern generator 1
4 and the code generator 20 are the same as the first embodiment shown in FIG. Pattern generator 14 directly receives clock signal E from clock generator 10 and generates a predetermined logic pattern such that the logic levels on lines AD change with each cycle of the clock signal. Note that the oscillation frequency of clock generator 10 is the same as the system clock frequency of CUT 16. The counter 12 counts the start or stop signal H supplied from the pattern generator 14 and supplies a carry out F to the start/stop terminal S/S of the code generator 20. Counter 12 is N
is a base counter, where N is the number of output lines of CUT 16. In this embodiment, one code cycle is four clock cycles as shown in FIG. Therefore, the data terminal D of the code generator 20 is the first
receives a logic signal on line A from multiplexer 18 during a code cycle, receives a logic signal on line B during a second code cycle, receives a logic signal on line C during a third code cycle;
It then receives a logic signal on line D during the fourth code cycle. Other operations are similar to those of the first embodiment shown in FIGS. 1 and 2. This embodiment can also be applied to the second embodiment shown in FIG.

As can be seen from the above, the present invention can effectively test logic circuits such as buses having many test points or lines under test.

Although only the preferred embodiments of the present invention have been described above, those skilled in the art will easily understand that many changes and modifications can be made without departing from the gist of the present invention. For example, in the embodiment of FIG. 3, a single multiplexer may be used to sequentially select one line of all of the address, data and control buses. But in this case, N is 32 and the first clock frequency is
32MHz, and counter 12 is a 5-bit binary counter. Test procedures and expected codes may be clearly marked near the test points. Further, the code generator may include a multiplexer in which a plurality of input terminals are respectively connected to probes.

[Brief explanation of drawings]

1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing a second embodiment of the present invention. FIG. 4 is a block diagram showing a third embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation of FIG. 10 is a clock generator, 12 is a counter, 14
is a pattern generator, 16 is a logic circuit under test,
18 is a multiplexer, 20 is an encoding circuit, 22
is the CPU and kernel circuit, 30 is the buffer, 3
2 is a peripheral device.

Claims (1)

[Scope of Claims] 1. A predetermined logic pattern is supplied to a logic circuit under test in response to a clock signal, and N (N is a natural number) output logic signals generated in parallel from the logic circuit under test are different. one logic circuit under test is sequentially and continuously selected, the selected output logic signal is encoded, and the acceptability of the logic circuit under test is determined according to the encoded output logic signal. Test method for logic circuits.