JPS58202574A - Metal oxide semiconductor transistor - Google Patents

Abstract

PURPOSE:To form a low-concentration impurity diffusion layer to a section just under a gate oxide film through a comparatively simple method in which photoengraving and ion implantation processes are added, and to improve drain dielectric resistance by forming the diffusion layer extending from a drain region to the section just under the oxide film. CONSTITUTION:A source region 2, the drain region 3, a field oxide film 4 and the gate oxide film 5 are formed to a silicon substrate 1. For form the low- concentration impurity diffusion layer, the whole upper surface is coated with a photo-resist 8, an opening section 9 is bored to an upper section in the vicinity of a boundary section between the drain 3 and the gate oxide film 5, and an impurity 10 of the same conduction type as the source 2 and the drain 3 is introduced to a section adjacent to the drain 3 just under the gate oxide film 5 so as to extend from the drain 3 through ion implantation as the arrow I in the figure. The photo-resist 8 is removed, and the low-concentration impurity diffusion layer 11 is formed through thermal annealing for activating the impurity 10 implanted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS transistor, and more particularly to an improvement in a bridge structure for improving the drain breakdown voltage of the transistor.

In recent years, due to the high density integration of MO8 integrated circuits (MO8C), the impurity diffusion depth has become shallower and the pressure has been lowered due to Hiba's reduction law.However, on the other hand, in the peripheral circuits of MO8IO, , for example, a fluorescent display tube, which is often composed of elements that require a high driving voltage of several tens of volts. Therefore, the MOS transistor (
MO8T) is required to have a high drain breakdown voltage of several tens of volts.

Figure 1 is a sectional view showing a conventional basic MOEIT.
1) is a silicon substrate, (2) is a source region, (3) is a drain region, (4) is a field oxide film, (5) is a gate oxide film, and (6) is a gate electrode. Now, when the gate electrode (6) is set to the ground potential and the potential of the drain (3) is increased, the electric field strength increases at the boundary a (indicated by the broken line circle) between the drain (3) and the gate oxide film (5). is at its maximum, so the equipotential line near the drain (3) becomes as shown by a dashed-dotted line, and avalanche breakdown occurs first at this boundary a due to electric field concentration. Such electric field concentration depends on the diffusion depth of the drain (3), the thickness of the gate oxide film (5), the impurity concentration distribution of the aOp type and n type at the boundary, etc.
As the impurity diffusion depth becomes shallower and the gate oxide film becomes thinner due to higher density integration, the drain breakdown voltage is forced to decrease.

Figure 2 shows a prior art MOBT that alleviates the electric field concentration at the boundary a and improves the drain breakdown voltage.
In this cross-sectional view, the drain (3) is connected to the gate oxide film (5).
In addition to forming it so that it does not reach the part directly below the
A diffusion layer (7) having the same conductivity type as the source (2) and drain (3) and having a low concentration of cine particles is provided between the drain (3) and the portion immediately below the gate oxide film (5). , the drain voltage is absorbed by this diffusion layer (7), and the region a
The purpose is to soften the impurity concentration gradient in the wafer and to alleviate electric field concentration.

However, although MOBT with this structure can significantly improve drain breakdown voltage, the diffusion layer (7) with low impurity concentration
There is a drawback that the conductivity of the field oxide film (4) tends to fluctuate due to the influence of charges in the field oxide film (4) and the surface of the field oxide film (4). Another disadvantage was that the high-4 degree impurity diffusion in the source (2) and drain (3) and the low-concentration impurity diffusion in the diffusion layer (7) had to be performed independently, complicating the manufacturing process. .

This invention has been made in view of the above points, and by forming the low concentration diffusion j- directly under the gate oxide film, it is a relatively simple method that does not have the drawbacks of the above-mentioned conventional method. BIIO8T that can achieve high drain voltage breakdown
The purpose is to provide a structure for

FIG. 3A-0 is a sectional view showing the state at the main stage of the manufacturing process in order to deepen the understanding of the configuration of one embodiment of the present invention. First, as shown in FIG. A source region (2), a drain region (3), a field oxide film (4), and a gate oxide film (5) are formed on the silicon substrate (1) by repeating the steps of silicon oxide film formation, photoetching, impurity diffusion, etc. Form. Next, in order to form a low concentration impurity diffusion layer, which is a feature of the MOBT of the present invention, the entire upper surface is covered with a photoresist (8) as shown in FIG. 3B, and then the drain (3) and gate oxide film ( A hole (9) is formed in the upper part near the boundary with the source (2) by photolithography, and then ions are implanted as shown by arrow I in the figure to form the source (2).
, an impurity αQ having the same conductivity type as the drain (3) is introduced into a portion adjacent to the drain (3) immediately below the gate oxide film (5) so as to extend from the drain (3). Continuing,
As shown in FIG. 30, after removing the photoresist (8) and performing thermal annealing to activate the implanted impurity αQ to form a low concentration impurity diffusion layer αυ, the source (2) and drain (3) Opening of a contact hole (not shown) to
The MOBT of this example is completed through the steps of forming the same electrode (not shown) and the gate electrode (6).

In this MOBT, from the drain (3) to the gate oxide film (5
) of (/υ) Since the impurity concentration gradient in the region a near the tip of each low-concentration impurity diffusion layer extending directly below is relaxed, the electric field concentration in region a is weakened, and the drain breakdown voltage is improved. can be achieved.In this case, the drain breakdown voltage should be maximized.

For this purpose, the impurity concentration of the diffusion layer α and the thermal annealing conditions can be optimally selected.

In addition, in the above embodiment, metal gate/conventional MOB
Although the case where the present invention is applied to a T is described, the present invention can also be applied to a silicon gate/selective oxidation type MOBT.

As detailed above, in the MOBT according to the present invention, the low concentration impurity diffusion layer extending from the drain region is formed directly under the gate oxide film, which requires additional photolithography and ion implantation steps. It can be formed by a simple method and can improve the drain breakdown voltage, and the conductivity of this low concentration impurity diffusion layer does not change due to the influence of charges on the surface of the field oxide film.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing a conventional basic MOBT, Fig. 2 is a sectional view of a prior art MOBT with improved drain breakdown voltage, and Figs. FIG. 3 is a cross-sectional view showing the state at the main stages of the manufacturing process. In the figure, (1) is a silicon substrate, (2) is a source region, (3) is a drain region, (5) is a gate oxide film,
11) is a low concentration impurity diffusion layer. In addition, the same reference numerals in the figures indicate the same or equivalent parts. 0 Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) In a region immediately below the gate insulating film and adjacent to the drain region, an impurity diffusion layer having the same conductivity type as the drain region and having a lower concentration than the drain region is extended from the drain region. A MOS (MOS) transistor characterized by being provided in the.