JPS58201360A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the semiconductor device smaller in size by a method wherein the apertures of a gate electrode and the lead-out electrode of an Si substrate are formed simultaneously using a mask, thereby enabling to almost unnecessitate the allowance in the design. CONSTITUTION:A poly Si 24 is superposed on the region which is insulation-isolated 22 from a P type substrate 21 and covered by an SiO2 thin film, an etching is performed using an Si3N4 mask 28, poly Si layers 24a-24c are formed, and P-layers 24a-24d are formed by performing an ion implantation. The SiO2 film is covered on the side face of the poly Si, the films 28a, 28c and layers 24a, 24c and the SiO2 thin film are removed using a resist mask 25d on the poly Si layer 24b alone, and N-diffusion layers 21e and 21f are formed. An SiO2 film 29 is covered and the semiconductor device is completed. As the Si3N4 mask 28 can be formed using a photomask once, the allowance is made almost unnecessary when the aperture parts for gate electrode and a lead-out electrode are designed, thereby enabling to make the titled semiconductor device smaller in size.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention consists of 1. lIl! l# gate field effect type (hereinafter referred to as
Regarding the manufacturing method of M (JS type) semiconductor devices, in particular, as the devices become smaller, the margin required in the device design against manufacturing variations becomes relatively large. The purpose of the present invention is to provide a manufacturing method that makes it possible to make such a design margin smaller than in the past, when this becomes a dominant factor in preventing the occurrence of problems.

One of the major guidelines for technological progress in semiconductor devices, particularly MO8 type semiconductor devices, is to further miniaturize the devices. However, device miniaturization can present new manufacturing challenges.

For example, it can be ignored if the device is kept sufficiently large, but it gradually becomes more apparent as miniaturization progresses.

Conventionally, when semiconductor devices are manufactured, the manufactured devices always have manufacturing defects. For example, in terms of device performance, the actual performance is distributed around the designed value.

Such manufacturing variations are unavoidable, so in order to efficiently manufacture equipment, it is necessary to create a design margin that takes into account expected manufacturing variations at the equipment design stage. Must be included in the design.

Since manufacturing variations are constant if the manufacturing technology is maintained at a certain level, the above-mentioned design margin may also be within a certain range. However, as mentioned above, when advances in the design of semiconductor devices require further miniaturization of the devices, the above-mentioned design margin becomes a relatively large factor, which limits the miniaturization of the devices. It becomes the dominant factor.

Example 1-. MO shown in FIG. 1 (1) to (g)
First, as shown in FIG. 1(a), an element formation region 13 and an element isolation region are formed on one main surface of a -conductivity type single crystal silicon substrate 11. For example, an insulating film 1 made of silicon oxide
2tl- after forming 1, such as polycrystalline silicon,
A conductive substance 14 is deposited on the entire surface. then the first
As shown in Fig. (b), the photomask 151 is selectively left at a predetermined location using a photomask 161f, and a photoresist 151\r mask is used to form a polycrystalline film using a well-known method. The silicon film 14 is selectively etched away and a gate electrode 14a is formed.Subsequently, as shown in FIG. 1(e), using the gate electrode 14a marked # as a mask, a known impurity thermal diffusion method or impurity ion implantation method is performed. According to the above-mentioned conductivity type single crystal silicon/substrate 1
Impurity diffusion layers 11a and llb, which will become a source and a drain, are formed at predetermined locations of 1.

Thereafter, as shown in FIG. 1 d), interlayer insulation [117] is formed. Next, as shown in FIG. 1(e)K, I
T! Using photomasks 16b to 16e, seven photoresists 15b to 1Set are formed at predetermined locations on the interlayer insulation layer 117. These 7-layer resistors) 15b to 15e were formed in a spinning-conductivity type single crystal 7-recon substrate 11. Source/drain impurity diffusion layer 111 and ll
This is to provide an opening S in the interlayer insulating film 17 in which an extraction electrode is to be formed from the gate electrode T1.

FIG. 511(f) shows the state after openings 17a, 17b, and 17c for forming such extraction electrodes are provided.

Subsequently, as shown in FIG. 1(g), the third photonip puffer method is used to form pull-out electrodes 18m, 18b, and 18c made of, for example, aluminum.

Here, the design margin mentioned above! Regarding fK,
For the first photomask 16m shown in FIG. 1 (bl), the second 7 photomasks 16b to 1 shown in FIG.
6e is required to be manufactured with a design margin &-.

That is, the extraction electrode forming openings 17a, 17b, and 17c shown in FIG. 1 (fl) have a design margin σ.
1. For example, the opening 17m and the gate electrode 14
If the distance is 0, the photomasks 16b to t6e (M
(See Figure 1 (8)).

L10　・ It must be made with.

For example, if σ is about 1 μm, then L is about 5 μm.

L〉σ So, 1 degree #'i of σ doesn't really matter.

When it becomes L-1 to 2 μm, it becomes the same size as σ, and KsL<1. When it comes to am, equipment Fi, design margin l
[Further miniaturization is limited by σ.

It becomes meaningless.

An object of the present invention is to provide a method of manufacturing a semiconductor device that allows the design margin of 1 ft to be much smaller than that of the conventional method.

The present invention is characterized by - a step of forming an element formation region and an element isolation region on a conductivity type single crystal silicon/substrate;
! When the t-gate electrode is formed in a predetermined region, region 9, where the lead-out current #A from the single conductivity type single crystal silicon/substrate is formed at the same time, is also formed by the process of forming the same material as this gate electrode, and this gate electrode region. and - a semiconductor device comprising the steps of: forming an insulating film in a region other than an extraction electrode region from a conductive single crystal silicon substrate; and selectively removing the same material as the gate electrode in the extraction electrode forming portion. It is in the manufacturing method.

According to the invention, photomasks 16a, 16b to 161, for example, shown in FIGS. 1(b) and 1(e).

Since portions that require design margins are formed on one photomask, it is possible to manufacture semiconductor devices with further miniaturization.

An embodiment of the present invention will be described below with reference to the drawings. Figs. 2 (1) to 0+ show a method for manufacturing a semiconductor device based on the embodiment of the present invention in order of process.

First, as shown in FIG. 2 (al), on one main surface of a 1-conductivity type single crystal silicon/substrate 21, an element formation region 23 and an insulating film 22 made of 7-lico oxide for isolation between elements are formed. After that, a conductive material 24 made of, for example, polycrystalline silicon is deposited on the entire surface.As shown in FIG. An oxidizing film (hereinafter abbreviated as oxidation-resistant film) 28 is formed on the polycrystalline silicon/film 24.

Thereafter, as shown in FIG. 2(C), the photomask 26a
.

Photoresists 25m, 25b, and 25c 1 are formed at predetermined locations on the oxidation-resistant film 28 using photoresists 26b and 26c. In this case, the predetermined location is the gate electrode formation region 25b formed using a conventional method.

This refers to a region where an extraction electrode from the - conductivity type single crystal silicon/substrate 21 is formed.

After that, Figure 2 (dlO @ Ki 7 Otomask 25m
.

25b and 25c as masks, the oxidation-resistant film 28. The polycrystalline silicon/coating 24 is combined and etched to remove the area excluding the extraction electrode forming portions 24m, 24C, 28a, 28C and the gate electrodes 24b, 28b from the conductivity type single crystal silicon substrate 21. Remove.

After that, as shown in FIG. 2(e), the extraction electrode forming portions 24a, 24c, 28m, 28c and
-) using poles 24b and 28bi masks, - by a known zero impurity thermal diffusion method or an impurity ion implantation method.
Impurity diffusion layer 21' in the conductive type 1 single crystal substrate/substrate
, 21b, 21C, 21d t-form.

Next, as shown in FIG.
Cover the side areas of the 7-licon oxide.

After that, as shown in FIG. 2(g), the photomask 26d
to cover only the region of the gate electrode 24b.
Or, conversely, the photoresist 25d'j- is formed so as not to cover only the extraction electrode formation region.

In this case, the photomask 26d only needs to roughly cover the gate electrode 24b, and there is no need to take the above-mentioned design margin into consideration.

Then, as shown in FIG.
By selectively removing the oxidation-resistant film and the polycrystalline silicon film that are not covered with the lead-out electrode formation portion, the opening 27a for the lead-out electrode formation is formed from the conductivity type single crystal silicon substrate 21. , 27b. Next, impurities are diffused into the silico/substrate 21 from the primary openings 27m and 27b by a known impurity thermal diffusion method to form impurity diffusion layers 2s and 21f t-L7.
'E* (Fig. 2 (S) Covers the entire surface and insulates between the eyebrows @29f
;Form.

Using the most well-known photo-etch blowfish technique.

An opening for forming an extraction electrode is provided at a predetermined location of the layer separation 11JII29 formed in FIG. 2 (most), and then,
For example, 30 m of extraction electrodes made of Al1=Um, etc.
, 30b, and 30C.

In this way, in this embodiment, a photomask 16 for forming a gate electrode as shown in FIG.
Cocoon story shown in figure (・) - conductivity type single crystal silicon/substrate 11
Photomask 16bt for forming extraction electrodes from - one-time photomask 26m, 26b.

26C, and therefore Fig. 1 (-
photomask 161 and photomask 1 of FIG.
6b is not required at all.

When manufacturing an MOa type semiconductor device based on the present invention, as shown in FIG. Since it can be formed simultaneously using a mask,
There is almost no need for the design margin that was conventionally required, and it becomes possible to perform an optimal design for downsizing the device.

[Brief explanation of drawings]

FIGS. 1(1) to 1(g) show a conventional manufacturing method for MO8JIJ semiconductor devices. FIG. 2+11 to U> show examples based on the present invention in the order of manufacturing steps. In the figure, 11.21...- conductive single crystal silicon/substrate, 12.22... insulating film for isolation between elements, 13.23... element formation region , 14.
24... Polycrystalline silicon film, 15m, 15b
, 15C, 15d, 15e, 25a, 25b, 25c,
25d --- Photoresist, 16a, 16
b, 16C, 16d, 166.261. 26b, 26c, 26d...Photomask, 1
7.29...Interlayer insulating film, 27a, 27b, 1
71, 17b, 17C...Opening portion for extraction electrode % 181s18b, 18c. 301.30b, 30c...-'51@output electrode.

Claims (1)

[Claims] A method for manufacturing a semiconductor device includes a step of simultaneously providing a film having the same structure in a gate electrode formation region on a substrate and an extraction electrode formation region from the substrate, and a step of selectively removing the film in the extraction electrode formation region. A method of manufacturing a semiconductor device, comprising: