JPH05343670A - Offset structured mos transistor and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To avoid the deterioration in operational performances of the MOS transistor by a method wherein the extension of a depletion layer to an offset region is facilitated for adjusting the high voltage applied on a gate end when a high voltage is applied on a drain region while suppressing the stiffening resistance in an offset region. CONSTITUTION:This offset structured MOS transistor 1 provided on a semiconductor substrate 11 is formed of an offset region 16, the first impurity diffused region 20 in lower concentration than that of a drain region 17 and the second impurity diffused region 21 formed on a part of the upper layer of said region 20 in the impurity concentration between the first impurity diffused region 20 and the drain region 17 in the connecting state to the drain region 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset structure MO.
The present invention relates to an S transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional offset structure MOS transistor will be described with reference to the schematic sectional view of FIG. As shown in the figure, a gate insulating film 72 is formed on the upper surface of the semiconductor substrate 71.
A gate 73 is formed with a space in between. This gate 7
An offset region 74 and a source-side low-concentration diffusion region 75 are formed in the upper layer of the semiconductor substrate 71 on both sides of 3. A drain region 76 is formed in the upper layer of the semiconductor substrate 71 on one side of the gate 73 with the offset region 74 interposed therebetween. Further, in the upper layer of the semiconductor substrate 71 on the other side of the gate 73, the source region 77 is formed with the source-side low-concentration diffusion region 75 interposed therebetween. As mentioned above,
A MOS transistor 70 having an offset structure is formed.

Next, a method of forming the MOS transistor 70 having the offset structure will be described with reference to the manufacturing process chart of FIG. The first step will be described with reference to FIG. In this step, the gate insulating film 72 is formed on the upper surface of the semiconductor substrate 71 by a normal process, and then the gate insulating film 72 is formed.
A gate 73 is formed on the upper surface of the.

Then, a second step shown in FIG. 8B is performed. In this step, for example, by ion implantation, impurities are introduced into the upper layer of the semiconductor substrate 71 on both sides of the gate 73, and the offset region 74 is formed in at least the upper layer of the semiconductor substrate 71 on one side of the gate 73.

Subsequently, a third step shown in FIG. 8C is performed. In this step, an impurity introduction mask 81 made of a resist is formed on one side of the gate 73 in the vicinity of the gate 73 by a normal photolithography technique. After that, an impurity is introduced into the upper layer of the semiconductor substrate 71 on the other side of the gate 73 by an ion implantation method using the impurity introduction mask 81 to form the source-side low-concentration diffusion region 75.

After that, the impurity introducing mask 81 is removed by, for example, an asher process. Then, a fourth step shown in FIG. 8D is performed. In this step, the sidewalls 82 are formed on both sides of the gate 73 by a normal sidewall formation process. Further, the gate 73 is formed by a normal photolithography technique.
A drain region forming mask 83 made of a resist is formed on one side. After that, on one side of the gate 73,
A drain region 76 is formed deeper than the offset region 74 with a part of the offset region 74 interposed between the gate 73 and the gate region. At the same time, on the other side of the gate 73, the source region 77 is deeper than the source-side low-concentration diffusion region 75 with a part of the source-side low-concentration diffusion region 75 interposed between the gate 73 and the gate 73.
To form. As described above, the offset structure MOS
The transistor 70 is formed.

[0007]

In the above-mentioned offset structure MOS transistor, the voltage applied to the gate end is adjusted by extending the depletion layer in the offset region when a high voltage is applied to the drain region. However, in order to sufficiently reduce the voltage at the gate end, the impurity concentration in the offset region must be lowered.
However, if the impurity concentration in the offset region is lowered,
Since it is possible to reduce the voltage applied to the gate end, the breakdown voltage is improved, but the resistance in the offset region is increased and it becomes difficult for current to flow. Therefore, the operating performance of the MOS transistor is reduced.

Further, in the method of manufacturing the MOS transistor having the offset structure, since the offset region is formed by one-time ion implantation, the impurity concentration in the offset region cannot be changed stepwise. Therefore, it is difficult to form an offset region in which the voltage applied to the gate end can be adjusted while suppressing a decrease in the current value flowing in the offset region.

An object of the present invention is to provide a MOS transistor having an offset structure in which a current easily flows and an excellent gate breakdown voltage, and a manufacturing method thereof.

[0010]

SUMMARY OF THE INVENTION The present invention is a MOS transistor of an offset structure made to achieve the above object, wherein an offset region is a first impurity diffusion region having a concentration lower than that of a drain region. And a second impurity diffusion region formed in a part of an upper layer of the first impurity diffusion region in a state of having an impurity concentration between the first impurity diffusion region and the drain region and being connected to the drain region. ..

In the method of manufacturing a MOS transistor having the above-mentioned offset structure, in a first step, a gate insulating film and a gate are formed on an upper surface of a semiconductor substrate, and then in a second step, a semiconductor on one side of the gate is formed. A second impurity diffusion region is formed in the upper layer of the substrate. Then, in a third step, a first impurity diffusion region is formed in an upper layer of the second impurity diffusion region by introducing an impurity using a first impurity introduction mask formed on one side of the gate in the vicinity of the gate. To do. Then, in a fourth step, after the first impurity introduction mask is removed, a second impurity introduction mask is formed on one side of the gate and the source side low concentration is formed on the upper layer of the semiconductor substrate on the other side of the gate. Form a diffusion region. Then, in a fifth step, sidewalls are formed on both sides of the gate and a drain region forming mask is provided on one side of the gate, and then the drain region is left while leaving the first and second impurity diffusion regions on the gate side. And the source region is formed with the source side low concentration diffusion region on the gate side interposed therebetween. Or the above first,
After performing the second step, the fourth step is performed, then the third step is performed, and then the fifth step is performed.

In another manufacturing method, after performing the first step and the second step, in a third step, a source side low concentration diffusion region is formed on an upper layer of the semiconductor substrate on the other side of the gate. Then, in a fourth step, sidewalls are formed on both sides of the gate, and the sidewalls are used as a mask to introduce impurities into the upper layer of the semiconductor substrate on both sides of the gate.
A first impurity diffusion region is formed in an upper layer of the second impurity diffusion region on one side of the gate. Then in the fifth step,
A drain region that penetrates the first impurity diffusion region and the second impurity diffusion region is formed in the semiconductor substrate on one side of the gate, and the semiconductor substrate on the other side of the gate is deeper than the low concentration diffusion region on the source side. Form a source region. Alternatively, after the first step is performed, the third step is performed, and then the second step is performed.
Is performed, and then the fourth and fifth steps are performed.

In another offset structure MOS transistor, the offset region has an impurity concentration lower than that of the drain region and is formed on the drain region side of the offset region, and a first impurity diffusion region, The second impurity diffusion region has a lower impurity concentration than the first impurity diffusion region and is formed on the gate side of the offset region in a state of being connected to the first impurity diffusion region. ..

In another method for manufacturing a MOS transistor having an offset structure, a gate insulating film and a gate are formed on an upper surface of a semiconductor substrate in a first step, and then a semiconductor on both sides of the gate is formed in a second step. Impurities are introduced into the upper layer of the substrate to form a second impurity diffusion region in the upper layer of the semiconductor substrate on one side of the gate. Next, in a third step, a first impurity diffusion region deeper than the second impurity diffusion region is formed in the upper layer of the semiconductor substrate while leaving a part of the second impurity diffusion region on one side of the gate. Subsequently, in a fourth step, a source-side low-concentration diffusion region is formed in the upper layer of the semiconductor substrate on the other side of the gate. Then, in a fifth step, sidewalls are formed on both sides of the gate and a drain region formation mask is formed on one side of the gate, and then the first impurity diffusion region is connected to one side of the gate.
The drain region is formed deeper than the impurity diffusion region, and the source region is formed on the other side of the gate with a part of the source-side low-concentration diffusion region interposed between the gate and the other side. Alternatively, after performing the first and second steps, the fourth step is performed, then the third step is performed, and then the fifth step is performed.

Another manufacturing method, which comprises a first step and a second step
Then, in the third step, the source side low concentration diffusion region is formed in the upper layer of the semiconductor substrate on the other side of the gate. Next, in a fourth step, a first impurity diffusion region deeper than the second impurity diffusion region is formed in an upper layer of the semiconductor substrate while leaving the second impurity diffusion region at least on one side of the gate. To do. Then in the fifth step,
A drain region penetrating the first impurity diffusion region and the second impurity diffusion region is formed on the semiconductor substrate on one side of the gate, and a source region connected to the low concentration diffusion region is formed on the semiconductor substrate on the other side of the gate. Form. Alternatively, after performing the first step, the third step is performed, then the second step is performed, and then the fourth and fifth steps are performed.

[0016]

In the MOS transistor of the offset structure having the above structure, since the offset region is constituted by the first impurity diffusion region and the second impurity diffusion region having a lower impurity concentration than that, a high voltage is applied to the drain region. In this case, the depletion layer is extended to the second impurity diffusion region having a low impurity concentration. As a result, the voltage applied to the gate end decreases, and the breakdown voltage increases. Moreover, the resistance of the offset region is lowered by the first impurity diffusion region having a relatively high impurity concentration. For this reason, it becomes difficult for current to flow, and the operating performance of the MOS transistor is hardly reduced.

In the above manufacturing method, the first impurity diffusion region having a higher impurity concentration than that of the second impurity diffusion region is formed by introducing impurities by using the first impurity introduction mask or the sidewall as a mask. .. For this reason,
The length of the second impurity diffusion region on the gate side is determined by the length of the first impurity introduction mask or the thickness of the sidewall. In particular, the side wall is used for higher accuracy.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in the figure, the semiconductor substrate 11
A gate insulating film 14 is formed on a part of the surface of the semiconductor substrate 11 between the element isolation regions 12 and 13 formed in the upper layer. A gate 15 is formed on the upper surface of the gate insulating film 14. A drain region 17 is formed in the upper layer of the semiconductor substrate 11 on one side of the gate 15 with an offset region 16 in between. Also gate 15
On the other side of, the source region 19 is formed with the source side low concentration diffusion region 18 in between.

The offset region 16 is a first impurity diffusion region 20 having an impurity concentration lower than that of the drain region 17, and an upper layer of the first impurity diffusion region 20 in a state of being connected to the drain region 17. The second impurity diffusion region 21 is formed in a part. This second
The impurity diffusion region 21 is formed at a concentration higher than that of the first impurity diffusion region 20 and lower than that of the drain region 17. As described above, the MOS transistor 1 having the offset structure is constructed.

In the MOS transistor 1 having the offset structure having the above structure, when a high voltage is applied to the drain region 17, the depletion layer can be extended to the first impurity diffusion region 20 having a low impurity concentration. As a result, the voltage applied to the end of the gate 15 decreases, and the breakdown voltage increases. Moreover, the resistance of the offset region 16 is lowered by the second impurity diffusion region 21 having a relatively high impurity concentration. For this reason, it is possible to prevent the current from flowing, so that the MOS having the offset structure
The operating performance of the transistor 1 is hardly degraded.

Next, a method of manufacturing the MOS transistor 1 will be described with reference to the manufacturing process chart of FIG. In the description of this manufacturing method, the same components as those described with reference to FIG. The first step will be described with reference to FIG. In this step, the element isolation regions 12 and 13 are formed in the upper layer of the semiconductor substrate by, for example, a normal LOCOS method. Next, the gate insulating film 14 is formed on the upper surface of the semiconductor substrate 11 by a normal process technique, and then the gate 15 is formed on the upper surface of the gate insulating film 14.

Then, the second step shown in FIG. 2B is performed. In this step, impurities are introduced into the upper layer of the semiconductor substrate 11 on both sides of the gate 15 by a normal ion implantation method using the gate 15 as an ion implantation mask. Then, the first impurity diffusion region 20 is formed in the upper layer of the semiconductor substrate 11 on one side of the gate 15.

Subsequently, the third step shown in FIG. 2C is performed. In this step, the first impurity introduction mask 22 is formed of, for example, a resist in the vicinity of the gate 15 on one side of the gate 15 by, for example, an ordinary photolithography technique. At this time, the first impurity introduction mask 22 is also formed on the first impurity diffusion region 20 on the element isolation region 13 side. After that, the gate 15 is formed by a normal ion implantation method using the first impurity introduction mask 22.
Impurities are introduced into the upper layer of the semiconductor substrate 11 on both sides of. Then, the second impurity diffusion region 21 is formed in the upper layer of the first impurity diffusion region 20.

Subsequently, the first impurity introduction mask (22) is removed by, for example, an asher process. Then, a fourth step shown in (4) of FIG. 2 is performed. In this step, the first impurity introduction mask 22 is removed by, for example, a normal asher process. Subsequently, the second impurity introduction mask 23 is formed on one side of the gate 15 by using, for example, a resist by a normal photolithography technique. The second impurity introduction mask 23 covers the semiconductor substrate 11 between the gate 15 and the element isolation region 13. Then, by the usual ion implantation method,
Impurities are introduced into the upper layer of the semiconductor substrate 11 on the other side of the gate 15 to form the source-side low-concentration diffusion region 18.

Next, the second impurity introduction mask (23) is removed by, eg, asher treatment. Thereafter, the fifth step shown in (5) of FIG. 2 is performed. In this step, the sidewalls 24 are formed on both sides of the gate 15 by a normal sidewall formation technique, for example. Furthermore, by the usual photolithography technology,
The drain region forming mask 2 is provided on one side of the gate 15.
5 is formed of a resist, for example. At this time, the drain region forming mask 25 is also formed on the first impurity diffusion region 20 and the second impurity diffusion region 21 on the element isolation region 13 side.

After that, impurities are introduced into the semiconductor substrate 11 by an ordinary ion implantation method, and the first side is formed on one side of the gate 15.
With the impurity diffusion region 20 and the second impurity diffusion region 21 left, the drain region 17 is formed in a state deeper than the first impurity diffusion region 20. At the same time, the source side low concentration diffusion region 1 is provided on the other side of the gate 15 with a part of the source side low concentration diffusion region 18 interposed therebetween.
The source region 19 is formed in a state deeper than 8. Thus, the first impurity diffusion region 20 and the second impurity diffusion region 20 are formed in the upper layer of the semiconductor substrate 11 between the gate 15 and the drain region 17.
The offset region 16 including the impurity diffusion region 21 is formed. As described above, the offset structure MOS
The transistor 1 is formed.

In the method described with reference to FIG. 2, after the first step is performed, the third step is performed, and then the second step is performed, and then the fourth step and the fifth step. It is also possible to carry out steps.

In the above manufacturing method, impurities are introduced using the first impurity introduction mask 22 to form the second impurity diffusion regions 21 having an impurity concentration higher than that of the first impurity diffusion regions 20. Therefore, depending on the length of the first impurity introducing mask 22, the first
The length of the impurity diffusion region 20 is determined. That is, the first
The length of the impurity introduction mask 22 of the
In addition to setting the spread of the depletion layer when a high voltage is applied to, the resistance value of the offset region 16 is also set. Therefore, the length of the first impurity introduction mask 22 is set to a length such that the resistance value of the offset region 16 does not increase and a sufficient expansion of the depletion layer is obtained.

Next, another method of manufacturing the MOS transistor 1 having the offset structure will be described with reference to the manufacturing process chart of FIG. In the description of this manufacturing method, the same components as those described with reference to FIG. The first step and the second step are the same as those in the embodiment described with reference to FIG. 2 above, and thus the description thereof is omitted here.

After performing the above-mentioned first step and second step, the third step shown in FIG. 3A is performed. In this step, the gate 1 is formed by the usual photolithography technique.
An impurity introduction mask 26 is formed on one side of the resist layer 5 with a resist, for example. Then, by a normal ion implantation method, impurities are introduced into the upper layer of the semiconductor substrate 11 on the other side of the gate 15 to form the source-side low-concentration diffusion region 18.

Then, for example, by an asher process,
The impurity introducing mask (26) is removed. Next, the fourth step shown in FIG. 3B is performed. In this step, the sidewalls 27 are formed on both sides of the gate 15 by the usual sidewall formation method. Then, impurities are introduced into the upper layer of the semiconductor substrate 11 on both sides of the gate 15 by the normal ion implantation method using the sidewalls 27 as a mask, and the second layer is formed in the upper layer of the first impurity diffusion region 20 on one side of the gate 15. The impurity diffusion region 21 is formed.

Next, a fifth step shown in FIG. 3C is performed. In this step, a mask 28 for forming a drain region is formed on one side of the gate 15 with a resist, for example, by a normal photolithography technique. At this time, the drain region forming mask 28 is also formed on the first impurity diffusion region 20 and the second impurity diffusion region 21 on the element isolation region 13 side. After that, the first impurity diffusion region 20 and the second impurity diffusion region 2 are formed in the semiconductor substrate 11 on one side of the gate 15 by a normal ion implantation method.
The drain region 17 is formed so as to penetrate through 1 and 1.
At this time, at the same time, the semiconductor substrate 1 on the other side of the gate 15 is also
1, the source region 19 is formed in a state deeper than the source side low concentration diffusion region 18. In this way, the gate 15
On the upper layer of the semiconductor substrate 11 between the drain region 17 and
First impurity diffusion region 20 and second impurity diffusion region 21
And the offset region 16 is formed.

In the manufacturing method described with reference to FIG. 3, the first step and the second step are performed, the fourth step is performed, and then the third step is performed and then the third step is performed. It is also possible to perform step 5 and step 5.

The method described with reference to FIG. 3 requires one less photolithography step than the method described with reference to FIG. 2, so that the throughput can be improved. In addition, by introducing impurities using the sidewalls 27, the first
A second impurity diffusion region 21 having an impurity concentration higher than that of the impurity diffusion region 20 is formed. Therefore, the width of the sidewall 27 determines the length of the first impurity diffusion region 20 on the gate 15 side. The width of the sidewall 27 sets the expansion of the depletion layer when a high voltage is applied to the drain region 17, and the offset region 16
Also set the resistance value of. Therefore, the sidewall 27
Is set to such a length that a sufficient expansion of the depletion layer can be obtained without increasing the resistance value of the offset region 16.

Next, a second embodiment will be described with reference to the schematic sectional view of the structure shown in FIG. As shown in the figure, the semiconductor substrate 11
A gate insulating film 14 is formed on a part of the surface of the semiconductor substrate 11 between the element isolation regions 12 and 13 formed in the upper layer. A gate 15 is formed on the upper surface of the gate insulating film 14. A drain region 17 is formed in the upper layer of the semiconductor substrate 11 on one side of the gate 15 with an offset region 16 in between. Also gate 15
On the other side of, the source region 19 is formed with the source side low concentration diffusion region 18 in between.

The offset region 16 includes a first impurity diffusion region 31 formed on the gate 15 side of the offset region 16 and a drain region 1 of the offset region 16.
The second impurity diffusion region 32 is formed on the 7 side so as to be connected to the first impurity diffusion region 31 and the drain region 17. The second impurity diffusion region 32 is
The impurity concentration is lower than that of the drain region 17. The first impurity diffusion region 31 has an impurity concentration lower than that of the second impurity diffusion region 32. As described above, the offset structure MOS
The transistor 2 is configured.

In the MOS transistor 2 having the offset structure having the above structure, when a high voltage is applied to the drain region 17, the depletion layer can be extended to the first impurity diffusion region 31 having a low impurity concentration. As a result, the voltage applied to the end of the gate 15 decreases, and the breakdown voltage increases. Moreover, the resistance of the offset region 16 is lowered by the second impurity diffusion region 32 having a relatively high impurity concentration. For this reason, it is possible to prevent the current from flowing, so that the MOS having the offset structure
The operating performance of the transistor 2 is hardly degraded.

Next, a method of manufacturing the MOS transistor 2 will be described with reference to the manufacturing process chart of FIG. The same components as those shown in FIG. 4 are designated by the same reference numerals. The first step will be described with reference to FIG. In this step, the gate insulating film 14 is formed on the upper surface of the semiconductor substrate 11 by a known process technique, and then the gate 15 is formed on the upper surface of the gate insulating film 14.

Then, the second step shown in FIG. 5B is performed. In this step, impurities are introduced into the upper layer of the semiconductor substrate 11 on both sides of the gate 15 by a normal ion implantation method using the gate 15 as an ion implantation mask. And
A first layer is formed on the upper side of the semiconductor substrate 11 on one side of the gate 15.
The impurity diffusion region 31 is formed.

Subsequently, the third step shown in FIG. 5C is performed. In this step, by a normal photolithography technique, on one side of the gate 15 in the vicinity of the gate 15,
The first impurity introduction mask 33 is formed of, for example, a resist. At this time, the first impurity introduction mask 33
Is also formed on the first impurity diffusion region 31 on the element isolation region 13 side. After that, impurities are introduced into the upper layer of the semiconductor substrate 11 on both sides of the gate 15 by a normal ion implantation method. Then, in the state where a part of the first impurity diffusion region 31 is left on one side of the gate 15, the semiconductor substrate 1
A second impurity diffusion region 32 is formed in the upper layer of 1 in a state deeper than the first impurity diffusion region 31.

After that, the first impurity introduction mask (33) is removed by, for example, an asher process. Then, a fourth step shown in FIG. 5D is performed. In this step, the gate 15 is formed by a normal photolithography technique.
A second impurity introduction mask 34 is formed on one side of the resist, for example. Then, the gate 1 is formed by a normal ion implantation method using the second impurity introduction mask 34.
A source-side low-concentration diffusion region 18 is formed in the upper layer of the semiconductor substrate 11 on the other side of 5.

Then, the second impurity introduction mask (34) is removed by, eg, asher treatment. Thereafter, a fifth step shown in (5) of FIG. 5 is performed. In this step, the sidewalls 35 are formed on both sides of the gate 15 by the usual sidewall formation technique. Then, a drain region forming mask 36 is formed on one side of the gate 15 by a normal photolithography technique. At this time, on the first impurity diffusion region 31 on the element isolation region 13 side and the second impurity diffusion region 31 side.
The drain region forming mask 36 is also formed on the impurity diffusion region 32. After that, the drain region 17 is formed on one side of the gate 15 by a normal ion implantation method so as to be connected to the second impurity diffusion region 32 and deeper than the second impurity diffusion region 32. At the same time,
A source region 19 is formed on the semiconductor substrate 11 on the other side of the gate 15 with a portion of the source-side low-concentration diffusion region 18 interposed between the gate 15 and the semiconductor substrate 11. Thus, the offset region 16 including the first impurity diffusion region 31 and the second impurity diffusion region 32 is formed in the upper layer of the semiconductor substrate 11 between the gate 15 and the drain region 17.

In the manufacturing method described with reference to FIG. 5, the first step and the second step are performed, the fourth step is performed, and then the third step is performed and then the third step is performed. It is also possible to perform step 5 and step 5.

In the above manufacturing method, impurities are introduced using the first impurity introduction mask 33 to form the second impurity diffusion regions 32 having an impurity concentration higher than that of the first impurity diffusion regions 31. Therefore, depending on the length of the first impurity introduction mask 33, the first
The length of the impurity diffusion region 31 is determined. That is,
The length of the first impurity introduction mask 33 sets the spread of the depletion layer when a high voltage is applied to the drain region 17, and also sets the resistance value of the offset region 16. For this reason, the length of the first impurity introduction mask 33 is set to a length such that the resistance value of the offset region 16 does not increase and a sufficient expansion of the depletion layer is obtained.

Next, another manufacturing method of the MOS transistor 2 will be described with reference to the manufacturing process chart of FIG. The same components as those shown in FIG. 4 are designated by the same reference numerals. The first step and the second step are the same as those described with reference to FIG. 5, and thus the description thereof will be omitted here.

After carrying out the first and second steps, the third step shown in FIG. 6A is carried out. In this step, an impurity introducing mask 37 is formed on one side of the gate 15 by using a normal photolithography technique, for example, a resist. Then, by a normal ion implantation method using the impurity introduction mask 37, impurities are introduced into the upper layer of the semiconductor substrate 11 on the other side of the gate 15 to form the source-side low-concentration diffusion region 18.

After that, the impurity introducing mask (37) is removed by, for example, an asher process. Next, the fourth step shown in FIG. 6B is performed. In this step, the gate 1 is formed by the usual sidewall formation technique.
Sidewalls 38 are formed on both sides of 5. After that, impurities are introduced into the upper layer of the semiconductor substrate 11 on both sides of the gate 15 by a normal ion implantation method using the sidewall 38 as a mask. Then, with the first impurity diffusion region 31 left on one side of the gate 15, the second impurity diffusion region 32 is formed in the upper layer of the semiconductor substrate 11 in a state deeper than the first impurity diffusion region 31. To do.

After that, a fifth step shown in FIG. 6C is performed. In this step, a mask 39 for forming a drain region is formed on one side of the gate 15 with a resist, for example, by a normal photolithography technique. At this time, the drain region forming mask 39 is also formed on the first impurity diffusion region 31 and the second impurity diffusion region 32 on the element isolation region 13 side.

Then, by a normal ion implantation method, the second impurity diffusion region 31 and the second impurity diffusion region 32 are formed on the semiconductor substrate 11 on one side of the gate 15 with the first impurity diffusion region 31 and a part of the second impurity diffusion region 32 interposed therebetween. The drain region 17 penetrating the impurity diffusion region 32 is formed. At the same time, above gate 1
In the semiconductor substrate 11 on the other side of 5, the source region 19 penetrating the source-side low-concentration diffusion region 18 is formed on the gate 15 side with a part of the source-side low-concentration diffusion region 18 interposed therebetween. Thus, the offset region 16 including the first impurity diffusion region 31 and the second impurity diffusion region 32 is formed in the upper layer of the semiconductor substrate 11 between the gate 15 and the drain region 17.

In the manufacturing method described with reference to FIG. 6, the first step is performed, the third step is performed, and then the second step is performed, and then the fourth step and the fifth step. It is also possible to perform the steps of and.

The method described with reference to FIG. 6 requires one photolithography step less than the method described with reference to FIG. 2, so that the throughput can be improved. Further, by introducing impurities using the sidewall 38, the second impurity diffusion region 32 having a higher impurity concentration than the first impurity diffusion region 31 is formed. Therefore, the sidewall 3
The width of 8 determines the length of the first impurity diffusion region 31 on the gate 15 side. The width of the sidewall 38 sets the expansion of the depletion layer when a high voltage is applied to the drain region 17, and the offset region 16
Also set the resistance value of. Therefore, the sidewall 38
Is set to such a length that a sufficient expansion of the depletion layer can be obtained without increasing the resistance value of the offset region 16.

[0052]

As described above, according to the MOS transistor of the offset structure of the present invention, when a high voltage is applied to the drain region, the depletion layer extends to the first impurity diffusion region having a low impurity concentration. As a result, the voltage applied to the end of the gate decreases. Therefore, the gate breakdown voltage can be improved, and the reliability can be improved. Moreover, since the resistance of the offset region is lowered by the second impurity diffusion region having a relatively high impurity concentration, it is possible to prevent the current from flowing. Therefore, the MO of the offset structure
The high speed operation performance of the S transistor can be maintained.

According to the above-described manufacturing method, the impurity is introduced using the first impurity introduction mask or the sidewall as a mask, so that the second impurity diffusion region having an impurity concentration higher than that of the first impurity diffusion region is formed. Form. Therefore, the length of the first impurity diffusion region on the gate side is set by the length of the first impurity introduction mask or the thickness of the sidewall. In particular, when the side wall is used, the length of the first impurity diffusion region can be set by the thickness of the side wall, so that the first impurity diffusion region is longer than that when the first impurity introduction mask is used. The length of the area can be set with high accuracy.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram of the first embodiment.

FIG. 3 is another manufacturing process diagram of the first embodiment.

FIG. 4 is a schematic configuration sectional view of a second embodiment.

FIG. 5 is a manufacturing process diagram of the second embodiment.

FIG. 6 is another manufacturing process diagram of the second embodiment.

FIG. 7 is a schematic configuration sectional view of a conventional example.

FIG. 8 is a manufacturing process diagram of a conventional example.

[Explanation of symbols]

 1 MOS Transistor with Offset Structure 2 MOS Transistor with Offset Structure 11 Semiconductor Substrate 14 Gate Insulating Film 15 Gate 16 Offset Region 17 Drain Region 18 Source Side Low Concentration Diffusion Region 19 Source Region 20 First Impurity Diffusion Region 21 Second Impurity Diffusion Region 22 First Impurity Introducing Mask 23 Second Impurity Introducing Mask 24 Sidewall 25 Drain Region Forming Mask 26 Impurity Introducing Mask 27 Sidewall 28 Drain Region Forming Mask 31 First Impurity Diffusing Region 32 Second Impurity diffusion region 33 First impurity introducing mask 34 Second impurity introducing mask 35 Sidewall 36 Drain region forming mask 37 Impurity introducing mask 38 Sidewall 39 Drain region forming mask

Claims (10)

[Claims] 1. A MOS transistor having an offset structure having an offset region between a gate and a drain region, wherein the offset region includes a first impurity diffusion region having a lower concentration than the drain region, and the first impurity diffusion region. The impurity concentration is higher than that of the impurity diffusion region and lower than that of the drain region, and is formed in a part of an upper layer of the first impurity diffusion region in a state of being connected to the drain region. A MOS transistor having an offset structure, which is configured by a second impurity diffusion region. 2. A method of manufacturing a MOS transistor having an offset structure, comprising: a first step of forming a gate insulating film on an upper surface of a semiconductor substrate, and then forming a gate on the upper surface of the gate insulating film; A second step of introducing an impurity into an upper layer of the semiconductor substrate on one side to form a second impurity diffusion region, and after forming a first impurity introduction mask near the gate on one side of the gate An impurity is introduced into the upper layer of the semiconductor substrate on both sides of the gate using the first impurity introduction mask, and the first impurity is introduced into the upper layer of the second impurity diffusion region.
And a second step of forming the second impurity introduction mask on one side of the gate and removing the first impurity introduction mask, and then forming a second impurity introduction region on the other side of the semiconductor substrate. A fourth step of forming a source-side low-concentration diffusion region in the upper layer, forming sidewalls on both sides of the gate and forming a drain region forming mask on one side of the gate, and then forming one side of the gate A drain region that is deeper than the first impurity diffusion region is formed while leaving the first impurity diffusion region and the second impurity diffusion region left, and the source side is provided on the other side of the gate. And a fifth step of forming a source region deeper than the source-side low-concentration diffusion region with a part of the low-concentration diffusion region interposed therebetween. Method of manufacturing a Njisuta. 3. A MOS having an offset structure according to claim 2.
In the method for manufacturing a transistor, after performing the first step, performing the third step, then performing the second step, and then performing the fourth step and the fifth step. A method for manufacturing a MOS transistor having a characteristic offset structure. 4. A MOS having an offset structure according to claim 1.
A method of manufacturing a transistor, comprising: a first step of forming a gate insulating film on the upper surface of a semiconductor substrate, and then forming a gate on the upper surface of the gate insulating film; And a second step of forming a second impurity diffusion region, and after forming an impurity introduction mask on one side of the gate, introducing impurities into the upper layer of the semiconductor substrate on the other side of the gate. A third step of forming a source-side low-concentration diffusion region; and, after removing the impurity introduction mask, forming sidewalls on both sides of the gate, and using the sidewalls as masks, semiconductor substrates on both sides of the gate A fourth step of introducing impurities into the upper layer of the gate and forming a first impurity diffusion region in the upper layer of the second impurity diffusion region on one side of the gate; and a drain on one side of the gate. After forming a mask for forming a drain region, a drain region penetrating the first impurity diffusion region and the second impurity diffusion region is formed in the semiconductor substrate on one side of the gate, and the other side of the gate is formed. And a fifth step of forming a source region deeper than the source-side low-concentration diffusion region on the semiconductor substrate on the side, the method for manufacturing a MOS transistor having an offset structure. 5. A MOS having an offset structure according to claim 4.
In the method of manufacturing a transistor, after performing the first step and the second step, performing the fourth step, then performing the third step, and then performing the fifth step. And a method for manufacturing an MOS transistor having an offset structure. 6. A MOS transistor having an offset structure having an offset region between a gate and a drain region, wherein the offset region has an impurity concentration lower than that of the drain region and is located on the drain region side of the offset region. And the first impurity diffusion region formed on the first impurity diffusion region and having a lower impurity concentration than that of the first impurity diffusion region and being connected to the first impurity diffusion region on the gate side of the offset region. A MOS transistor having an offset structure, which is configured by a second impurity diffusion region. 7. The offset structure MOS according to claim 6.
A method of manufacturing a transistor, comprising: a first step of forming a gate insulating film on the upper surface of a semiconductor substrate, and then forming a gate on the upper surface of the gate insulating film; And a second step of forming a second impurity diffusion region, and after forming a first impurity introduction mask near one side of the gate near the gate, the first impurity introduction mask Is used to introduce impurities into the upper layer of the semiconductor substrate on both sides of the gate, while leaving a portion of the second impurity diffusion region on one side of the gate, the second impurity is added to the upper layer of the semiconductor substrate. A third step of forming a first impurity diffusion region deeper than the diffusion region, and a second impurity introduction mask is formed on one side of the gate after removing the first impurity introduction mask, The gate A fourth step of forming a source-side low-concentration diffusion region in the upper layer of the semiconductor substrate on the other side, and after forming sidewalls on both sides of the gate and forming a drain region formation mask on one side of the gate. , A drain region that is connected to the first impurity diffusion region on one side of the gate and is deeper than the first impurity diffusion region, and on the other side of the gate, the source side low concentration with respect to the gate. A fifth step of forming a source region with a part of the diffusion region interposed therebetween, and a method of manufacturing a MOS transistor having an offset structure. 8. The method of manufacturing a MOS transistor according to claim 7, wherein the fourth step is performed after the first step and the second step, and then the third step is performed. A method of manufacturing a MOS transistor having an offset structure, characterized in that the fifth step is performed after that. 9. The offset structure MOS according to claim 6.
A method of manufacturing a transistor, comprising: a first step of forming a gate insulating film on the upper surface of a semiconductor substrate, and then forming a gate on the upper surface of the gate insulating film; And a second step of forming a second impurity diffusion region, and after forming an impurity introduction mask on one side of the gate, introducing impurities into the upper layer of the semiconductor substrate on the other side of the gate. A third step of forming a source-side low-concentration diffusion region, and after forming sidewalls on both sides of the gate, using the sidewalls as a mask to introduce impurities into the upper layer of the semiconductor substrate on both sides of the gate. A first deeper than the second impurity diffusion region above the semiconductor substrate with the second impurity diffusion region left on one side of the gate;
And a second step of forming a drain region forming mask on one side of the gate, and then forming the first impurity diffusion region and the second region on the semiconductor substrate on one side of the gate. A fifth step of forming a drain region penetrating the impurity diffusion region and a source region connected to the low concentration diffusion region in the semiconductor substrate on the other side of the gate. Of manufacturing offset structure MOS transistor. 10. The MO of the offset structure according to claim 9.
In the method of manufacturing an S-transistor, after performing the first step, performing the third step, and then performing the second step, and then performing the fourth step and the fifth step. And a method for manufacturing an MOS transistor having an offset structure.