JPS58200366A - デ−タ転送方式 - Google Patents

デ−タ転送方式

Info

Publication number
JPS58200366A
JPS58200366A JP57083632A JP8363282A JPS58200366A JP S58200366 A JPS58200366 A JP S58200366A JP 57083632 A JP57083632 A JP 57083632A JP 8363282 A JP8363282 A JP 8363282A JP S58200366 A JPS58200366 A JP S58200366A
Authority
JP
Japan
Prior art keywords
processor
mode
data transfer
load
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57083632A
Other languages
English (en)
Japanese (ja)
Other versions
JPS631633B2 (cg-RX-API-DMAC7.html
Inventor
Tadashi Naruse
正 成瀬
Masato Amamiya
雨宮　真人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57083632A priority Critical patent/JPS58200366A/ja
Publication of JPS58200366A publication Critical patent/JPS58200366A/ja
Publication of JPS631633B2 publication Critical patent/JPS631633B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP57083632A 1982-05-18 1982-05-18 デ−タ転送方式 Granted JPS58200366A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57083632A JPS58200366A (ja) 1982-05-18 1982-05-18 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57083632A JPS58200366A (ja) 1982-05-18 1982-05-18 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS58200366A true JPS58200366A (ja) 1983-11-21
JPS631633B2 JPS631633B2 (cg-RX-API-DMAC7.html) 1988-01-13

Family

ID=13807836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57083632A Granted JPS58200366A (ja) 1982-05-18 1982-05-18 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS58200366A (cg-RX-API-DMAC7.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227856A (ja) * 1985-07-30 1987-02-05 Agency Of Ind Science & Technol 負荷分散装置
WO2009131007A1 (ja) * 2008-04-22 2009-10-29 日本電気株式会社 Ｓｉｍｄ型並列計算機システム、ｓｉｍｄ型並列計算方法及び制御プログラム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227856A (ja) * 1985-07-30 1987-02-05 Agency Of Ind Science & Technol 負荷分散装置
WO2009131007A1 (ja) * 2008-04-22 2009-10-29 日本電気株式会社 Ｓｉｍｄ型並列計算機システム、ｓｉｍｄ型並列計算方法及び制御プログラム
US8769244B2 (en) 2008-04-22 2014-07-01 Nec Corporation SIMD parallel computer system, SIMD parallel computing method, and control program

Also Published As

Publication number Publication date
JPS631633B2 (cg-RX-API-DMAC7.html) 1988-01-13

Similar Documents

Publication Publication Date Title
JP2682770B2 (ja) 仮想計算機システムのｃｐｕ制御方式
US5710549A (en) Routing arbitration for shared resources
KR102539574B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
KR102539572B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
KR102539573B1 (ko) 네트워크 온칩 데이터 처리 방법 및 장치
JPH0752420B2 (ja) 入出力装置アドレス方式
JPS58200366A (ja) デ−タ転送方式
CN113438171B (zh) 一种低功耗存算一体系统的多芯片连接方法
CN100361084C (zh) 用于利用门管理器维护实体顺序的方法和装置
CN114518940A (zh) 任务调度电路、方法、电子设备及计算机可读存储介质
WO2017111780A1 (en) Apparatus and method for distribution of congestion information in a switch
Wah et al. Distributed scheduling of resources on interconnection networks
CN119440627B (zh) 一种寄存器资源管理方法及其相关装置
JPS6227856A (ja) 負荷分散装置
JP3982077B2 (ja) マルチプロセッサシステム
US20070248097A1 (en) Message switching system
US12169466B2 (en) Distributed arbitration for shared data path
JPH1063607A (ja) Ｄｍａコントローラ
CN111260046A (zh) 运算方法、装置及相关产品
JPH0442342A (ja) バス調停回路
JP2648062B2 (ja) 並列処理装置
CN120825446A (zh) 数据传输方法、装置、介质、电子设备及程序产品
JPS61182158A (ja) コモンバス占有方式
CN105743803A (zh) 一种共享缓存的数据处理装置
JP3383940B2 (ja) クロスバネットワーク